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authorAnson Bridges <bridges.anson@gmail.com>2026-02-17 11:24:06 -0800
committerAnson Bridges <bridges.anson@gmail.com>2026-02-17 11:24:06 -0800
commit6e952fe110c2a48204c8cb0a836309ab97e5979a (patch)
tree64f87be87311dc3d62fb06da4fe23059a55de195 /electrical/EDA_data/ul_5034801000
added files
Diffstat (limited to 'electrical/EDA_data/ul_5034801000')
-rw-r--r--electrical/EDA_data/ul_5034801000/ImportGuides.html96
-rw-r--r--electrical/EDA_data/ul_5034801000/KiCADv6/2025-10-16_00-04-19.kicad_sym766
-rw-r--r--electrical/EDA_data/ul_5034801000/KiCADv6/ImportGuide.html98
-rw-r--r--electrical/EDA_data/ul_5034801000/KiCADv6/footprints.pretty/CON_5034801000_MOL.kicad_mod51
-rw-r--r--electrical/EDA_data/ul_5034801000/readme.txt9
5 files changed, 1020 insertions, 0 deletions
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+ <p>You can find detailed instructions on how to import your download by following the link for that tool found below</p>
+ <p><p><a href="https://app.ultralibrarian.com/content/help?kicad.htm">KiCAD - KiCAD v6+</a></p></p>
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diff --git a/electrical/EDA_data/ul_5034801000/KiCADv6/2025-10-16_00-04-19.kicad_sym b/electrical/EDA_data/ul_5034801000/KiCADv6/2025-10-16_00-04-19.kicad_sym
new file mode 100644
index 0000000..0977b3e
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+ <g>
+ <path class="st0" d="M255.6,89H254v-0.6h4V89h-1.6v4.8h-0.7L255.6,89L255.6,89z"/>
+ <path class="st0" d="M263.1,91.5c0-0.8-0.1-1.7-0.1-2.3l0,0c-0.2,0.6-0.4,1.3-0.7,2l-1,2.6h-0.5l-0.9-2.6
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+ </g>
+ </g>
+ </svg>
+ </div>
+ <div style="padding:30px;">
+ <p>If you are not redirected you can find detailed instructions on how to import your download by following the link for that tool found below</p>
+ <p><a href=https://app.ultralibrarian.com/content/help?kicad.htm>https://app.ultralibrarian.com/content/help?kicad.htm</a></p>
+ </div>
+ </body>
+</html> \ No newline at end of file
diff --git a/electrical/EDA_data/ul_5034801000/KiCADv6/footprints.pretty/CON_5034801000_MOL.kicad_mod b/electrical/EDA_data/ul_5034801000/KiCADv6/footprints.pretty/CON_5034801000_MOL.kicad_mod
new file mode 100644
index 0000000..09c423b
--- /dev/null
+++ b/electrical/EDA_data/ul_5034801000/KiCADv6/footprints.pretty/CON_5034801000_MOL.kicad_mod
@@ -0,0 +1,51 @@
+(footprint "CON_5034801000_MOL" (version 20211014) (generator pcbnew)
+ (layer "F.Cu")
+ (tags "5034801000 ")
+ (attr smd)
+ (fp_text reference "REF**" (at 0 -5.08 unlocked) (layer F.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text value CON_5034801000_MOL (at 0 -5.08 unlocked) (layer F.Fab)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text user "${REFERENCE}" (at 0 -5.08 unlocked) (layer F.Fab)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_line (start -4.619993 -3.07) (end -4.619993 3.07) (layer "F.CrtYd") (width 0.127))
+ (fp_line (start -4.619993 3.07) (end 4.619993 3.07) (layer "F.CrtYd") (width 0.127))
+ (fp_line (start 4.619993 3.07) (end 4.619993 -3.07) (layer "F.CrtYd") (width 0.127))
+ (fp_line (start 4.619993 -3.07) (end -4.619993 -3.07) (layer "F.CrtYd") (width 0.127))
+ (fp_line (start -3.603993 -1.8) (end -4.873993 -2.435) (layer "F.Fab") (width 0.127))
+ (fp_line (start -4.873993 -2.435) (end -4.873993 -1.165) (layer "F.Fab") (width 0.127))
+ (fp_line (start -4.873993 -1.165) (end -3.603993 -1.8) (layer "F.Fab") (width 0.127))
+ (fp_line (start -3.603993 -1.8) (end -4.873993 -2.435) (layer "F.SilkS") (width 0.1524))
+ (fp_line (start -4.873993 -2.435) (end -4.873993 -1.165) (layer "F.SilkS") (width 0.1524))
+ (fp_line (start -4.873993 -1.165) (end -3.603993 -1.8) (layer "F.SilkS") (width 0.1524))
+ (fp_line (start -3.349993 -1.8) (end -3.349993 0.372826) (layer "F.SilkS") (width 0.1524))
+ (fp_line (start -2.607282 1.8) (end 2.607283 1.8) (layer "F.SilkS") (width 0.1524))
+ (fp_line (start 3.349993 0.372825) (end 3.349993 -1.8) (layer "F.SilkS") (width 0.1524))
+ (fp_line (start 3.349993 -1.8) (end 2.720046 -1.8) (layer "F.SilkS") (width 0.1524))
+ (fp_text user "5034801000" (at 0 -7.62 unlocked) (layer "F.Fab")
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text user "5034801000" (at 0 -7.62 unlocked) (layer "F.SilkS")
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_line (start -3.349993 1.8) (end 3.349993 1.8) (layer "F.Fab") (width 0.127))
+ (fp_line (start 3.349993 1.8) (end 3.349993 -1.8) (layer "F.Fab") (width 0.127))
+ (fp_line (start 3.349993 -1.8) (end -3.349993 -1.8) (layer "F.Fab") (width 0.127))
+ (fp_line (start -3.349993 -1.8) (end -3.349993 1.8) (layer "F.Fab") (width 0.127))
+ (fp_line (start -2.720033 -1.8) (end -3.349993 -1.8) (layer "F.SilkS") (width 0.1524))
+ (pad "1" smd rect (at -2.249993 -1.5) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask"))
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+ (pad "6" smd rect (at 0.250007 -1.5) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask"))
+ (pad "7" smd rect (at 0.750006 -1.5) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask"))
+ (pad "8" smd rect (at 1.250008 -1.5) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask"))
+ (pad "9" smd rect (at 1.750007 -1.5) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask"))
+ (pad "10" smd rect (at 2.250006 -1.5) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask"))
+ (pad "P1" smd rect (at -3.039993 1.15) (size 0.3 1) (layers "F.Cu" "F.Paste" "F.Mask"))
+ (pad "P2" smd rect (at 3.039994 1.15) (size 0.3 1) (layers "F.Cu" "F.Paste" "F.Mask"))
+)
diff --git a/electrical/EDA_data/ul_5034801000/readme.txt b/electrical/EDA_data/ul_5034801000/readme.txt
new file mode 100644
index 0000000..1b4946d
--- /dev/null
+++ b/electrical/EDA_data/ul_5034801000/readme.txt
@@ -0,0 +1,9 @@
+Notes:
+
+1. All drill sizes are the maximum size provided by the manufacture (as required to calculate the minimum pad size).
+2. All dimensions in building footprints are the maximum (including any tolerance) as defined by the manufacturer with the exception of row pitch (which is always nominal). If only the normal sizing is provided we will input that dimension in mils, rounded to the nearest mil per our standards.
+3. Slots are currently identified as entities describing the size of the slot (arcs, lines, etc.) on the board outline layer. The extremities are identified with a via at each end. These slots will either need to be:
+ a. identified and dimensioned on your fabrication document
+ b. or they will need to be converted to slots (assuming the targeted tool has a slot capability) using the process defined in your cad tool for identifying a padstack as a slot.
+ i. Typically this is only capable of a width and length of the slot and a size of the mill radius that creates the slot.
+ ii. Choosing to use the native tool slots will require removing entities on the board outline and the associated pads in the footprint. \ No newline at end of file