diff options
| author | Anson Bridges <bridges.anson@gmail.com> | 2026-02-17 11:24:06 -0800 |
|---|---|---|
| committer | Anson Bridges <bridges.anson@gmail.com> | 2026-02-17 11:24:06 -0800 |
| commit | 6e952fe110c2a48204c8cb0a836309ab97e5979a (patch) | |
| tree | 64f87be87311dc3d62fb06da4fe23059a55de195 /electrical/EDA_data/ul_CSD23381F4 | |
added files
Diffstat (limited to 'electrical/EDA_data/ul_CSD23381F4')
7 files changed, 380 insertions, 0 deletions
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+ <p>You can find detailed instructions on how to import your download by following the link for that tool found below</p>
+ <p><p><a href="https://app.ultralibrarian.com/content/help?kicad.htm">KiCAD - KiCAD v6+</a></p></p>
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+ <p><a href=https://app.ultralibrarian.com/content/help?kicad.htm>https://app.ultralibrarian.com/content/help?kicad.htm</a></p>
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+ (fp_line (start 1.0287 0.787) (end 1.0287 0.787) (layer "F.CrtYd") (width 0.1524))
+ (fp_line (start -1.0287 0.787) (end -1.0287 0.787) (layer "F.CrtYd") (width 0.1524))
+ (fp_line (start -1.0287 0.8255) (end -1.0287 0.787) (layer "F.CrtYd") (width 0.1524))
+ (fp_line (start -1.0287 -0.787) (end -1.0287 -0.8255) (layer "F.CrtYd") (width 0.1524))
+ (fp_line (start -1.0287 -0.8255) (end 1.0287 -0.8255) (layer "F.CrtYd") (width 0.1524))
+ (fp_line (start 1.0287 -0.8255) (end 1.0287 -0.787) (layer "F.CrtYd") (width 0.1524))
+ (fp_line (start 1.0287 0.787) (end 1.0287 0.8255) (layer "F.CrtYd") (width 0.1524))
+ (fp_line (start 1.0287 0.8255) (end -1.0287 0.8255) (layer "F.CrtYd") (width 0.1524))
+ (fp_circle (center 0 0) (end 0.0762 0) (layer "F.Fab") (width 0.0254) (fill none))
+ (fp_circle (center -1.6629 0) (end -1.5867 0) (layer "F.SilkS") (width 0.1524) (fill none))
+ (fp_line (start -0.5207 0.3175) (end 0.5207 0.3175) (layer "F.Fab") (width 0.0254))
+ (fp_line (start 0.5207 0.3175) (end 0.5207 -0.3175) (layer "F.Fab") (width 0.0254))
+ (fp_line (start 0.5207 -0.3175) (end -0.5207 -0.3175) (layer "F.Fab") (width 0.0254))
+ (fp_line (start -0.5207 -0.3175) (end -0.5207 0.3175) (layer "F.Fab") (width 0.0254))
+ (pad "1" smd rect (at -0.3302 -0.175001) (size 0.354 0.2024) (layers "F.Cu" "F.Paste" "F.Mask"))
+ (pad "2" smd rect (at -0.3302 0.175001) (size 0.354 0.2024) (layers "F.Cu" "F.Paste" "F.Mask"))
+ (pad "3" smd rect (at 0.3302 0) (size 0.354 0.558) (layers "F.Cu" "F.Paste" "F.Mask"))
+)
diff --git a/electrical/EDA_data/ul_CSD23381F4/KiCADv6/footprints.pretty/YJC0003A_TEX.kicad_mod b/electrical/EDA_data/ul_CSD23381F4/KiCADv6/footprints.pretty/YJC0003A_TEX.kicad_mod new file mode 100644 index 0000000..b856c6e --- /dev/null +++ b/electrical/EDA_data/ul_CSD23381F4/KiCADv6/footprints.pretty/YJC0003A_TEX.kicad_mod @@ -0,0 +1,35 @@ +(footprint "YJC0003A_TEX" (version 20211014) (generator pcbnew)
+ (layer "F.Cu")
+ (tags "CSD23381F4 ")
+ (attr smd)
+ (fp_text reference "REF**" (at 0 0 unlocked) (layer F.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text value YJC0003A_TEX (at 0 0 unlocked) (layer F.Fab)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text user "${REFERENCE}" (at 0 0 unlocked) (layer F.Fab)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_line (start -0.7747 0.508) (end -0.7747 -0.508) (layer "F.CrtYd") (width 0.1524))
+ (fp_line (start -0.7747 -0.508) (end -0.7747 -0.508) (layer "F.CrtYd") (width 0.1524))
+ (fp_line (start 0.7747 -0.508) (end 0.7747 -0.508) (layer "F.CrtYd") (width 0.1524))
+ (fp_line (start 0.7747 -0.508) (end 0.7747 0.508) (layer "F.CrtYd") (width 0.1524))
+ (fp_line (start 0.7747 0.508) (end 0.7747 0.508) (layer "F.CrtYd") (width 0.1524))
+ (fp_line (start -0.7747 0.508) (end -0.7747 0.508) (layer "F.CrtYd") (width 0.1524))
+ (fp_line (start -0.7747 0.5715) (end -0.7747 0.508) (layer "F.CrtYd") (width 0.1524))
+ (fp_line (start -0.7747 -0.508) (end -0.7747 -0.5715) (layer "F.CrtYd") (width 0.1524))
+ (fp_line (start -0.7747 -0.5715) (end 0.7747 -0.5715) (layer "F.CrtYd") (width 0.1524))
+ (fp_line (start 0.7747 -0.5715) (end 0.7747 -0.508) (layer "F.CrtYd") (width 0.1524))
+ (fp_line (start 0.7747 0.508) (end 0.7747 0.5715) (layer "F.CrtYd") (width 0.1524))
+ (fp_line (start 0.7747 0.5715) (end -0.7747 0.5715) (layer "F.CrtYd") (width 0.1524))
+ (fp_circle (center 0 0) (end 0.0762 0) (layer "F.Fab") (width 0.0254) (fill none))
+ (fp_circle (center -1.6129 0) (end -1.5367 0) (layer "F.SilkS") (width 0.1524) (fill none))
+ (fp_line (start -0.5207 0.3175) (end 0.5207 0.3175) (layer "F.Fab") (width 0.0254))
+ (fp_line (start 0.5207 0.3175) (end 0.5207 -0.3175) (layer "F.Fab") (width 0.0254))
+ (fp_line (start 0.5207 -0.3175) (end -0.5207 -0.3175) (layer "F.Fab") (width 0.0254))
+ (fp_line (start -0.5207 -0.3175) (end -0.5207 0.3175) (layer "F.Fab") (width 0.0254))
+ (pad "1" smd rect (at -0.3302 -0.175001) (size 0.254 0.1524) (layers "F.Cu" "F.Paste" "F.Mask"))
+ (pad "2" smd rect (at -0.3302 0.175001) (size 0.254 0.1524) (layers "F.Cu" "F.Paste" "F.Mask"))
+ (pad "3" smd rect (at 0.3302 0) (size 0.254 0.508) (layers "F.Cu" "F.Paste" "F.Mask"))
+)
diff --git a/electrical/EDA_data/ul_CSD23381F4/readme.txt b/electrical/EDA_data/ul_CSD23381F4/readme.txt new file mode 100644 index 0000000..1b4946d --- /dev/null +++ b/electrical/EDA_data/ul_CSD23381F4/readme.txt @@ -0,0 +1,9 @@ +Notes:
+
+1. All drill sizes are the maximum size provided by the manufacture (as required to calculate the minimum pad size).
+2. All dimensions in building footprints are the maximum (including any tolerance) as defined by the manufacturer with the exception of row pitch (which is always nominal). If only the normal sizing is provided we will input that dimension in mils, rounded to the nearest mil per our standards.
+3. Slots are currently identified as entities describing the size of the slot (arcs, lines, etc.) on the board outline layer. The extremities are identified with a via at each end. These slots will either need to be:
+ a. identified and dimensioned on your fabrication document
+ b. or they will need to be converted to slots (assuming the targeted tool has a slot capability) using the process defined in your cad tool for identifying a padstack as a slot.
+ i. Typically this is only capable of a width and length of the slot and a size of the mill radius that creates the slot.
+ ii. Choosing to use the native tool slots will require removing entities on the board outline and the associated pads in the footprint.
\ No newline at end of file |
