diff options
| author | Anson Bridges <bridges.anson@gmail.com> | 2026-02-17 11:37:50 -0800 |
|---|---|---|
| committer | Anson Bridges <bridges.anson@gmail.com> | 2026-02-17 11:37:50 -0800 |
| commit | fb1611c0ca99d9e609057c46507be2af8389bb7b (patch) | |
| tree | 646ac568fdad1e6cf9e1f5767295b183bc5c5441 /firmware/memory_chip_gone/Core/Src/stm32wbxx_it.c | |
| parent | 6e952fe110c2a48204c8cb0a836309ab97e5979a (diff) | |
Diffstat (limited to 'firmware/memory_chip_gone/Core/Src/stm32wbxx_it.c')
| -rw-r--r-- | firmware/memory_chip_gone/Core/Src/stm32wbxx_it.c | 245 |
1 files changed, 245 insertions, 0 deletions
diff --git a/firmware/memory_chip_gone/Core/Src/stm32wbxx_it.c b/firmware/memory_chip_gone/Core/Src/stm32wbxx_it.c new file mode 100644 index 0000000..d947843 --- /dev/null +++ b/firmware/memory_chip_gone/Core/Src/stm32wbxx_it.c @@ -0,0 +1,245 @@ +/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32wbxx_it.c
+ * @brief Interrupt Service Routines.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2026 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32wbxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern IPCC_HandleTypeDef hipcc;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/* Cortex Processor Interruption and Exception Handlers */
+/******************************************************************************/
+/**
+ * @brief This function handles Non maskable interrupt.
+ */
+void NMI_Handler(void)
+{
+ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+ /* USER CODE END NonMaskableInt_IRQn 0 */
+ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+ while (1)
+ {
+ }
+ /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Hard fault interrupt.
+ */
+void HardFault_Handler(void)
+{
+ /* USER CODE BEGIN HardFault_IRQn 0 */
+
+ /* USER CODE END HardFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+ /* USER CODE END W1_HardFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Memory management fault.
+ */
+void MemManage_Handler(void)
+{
+ /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+ /* USER CODE END MemoryManagement_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+ /* USER CODE END W1_MemoryManagement_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Prefetch fault, memory access fault.
+ */
+void BusFault_Handler(void)
+{
+ /* USER CODE BEGIN BusFault_IRQn 0 */
+
+ /* USER CODE END BusFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+ /* USER CODE END W1_BusFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Undefined instruction or illegal state.
+ */
+void UsageFault_Handler(void)
+{
+ /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+ /* USER CODE END UsageFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+ /* USER CODE END W1_UsageFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles System service call via SWI instruction.
+ */
+void SVC_Handler(void)
+{
+ /* USER CODE BEGIN SVCall_IRQn 0 */
+
+ /* USER CODE END SVCall_IRQn 0 */
+ /* USER CODE BEGIN SVCall_IRQn 1 */
+
+ /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Debug monitor.
+ */
+void DebugMon_Handler(void)
+{
+ /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+ /* USER CODE END DebugMonitor_IRQn 0 */
+ /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+ /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Pendable request for system service.
+ */
+void PendSV_Handler(void)
+{
+ /* USER CODE BEGIN PendSV_IRQn 0 */
+
+ /* USER CODE END PendSV_IRQn 0 */
+ /* USER CODE BEGIN PendSV_IRQn 1 */
+
+ /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+ * @brief This function handles System tick timer.
+ */
+void SysTick_Handler(void)
+{
+ /* USER CODE BEGIN SysTick_IRQn 0 */
+
+ /* USER CODE END SysTick_IRQn 0 */
+ HAL_IncTick();
+ /* USER CODE BEGIN SysTick_IRQn 1 */
+
+ /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32WBxx Peripheral Interrupt Handlers */
+/* Add here the Interrupt Handlers for the used peripherals. */
+/* For the available peripheral interrupt handler names, */
+/* please refer to the startup file (startup_stm32wbxx.s). */
+/******************************************************************************/
+
+/**
+ * @brief This function handles IPCC RX occupied interrupt.
+ */
+void IPCC_C1_RX_IRQHandler(void)
+{
+ /* USER CODE BEGIN IPCC_C1_RX_IRQn 0 */
+
+ /* USER CODE END IPCC_C1_RX_IRQn 0 */
+ HAL_IPCC_RX_IRQHandler(&hipcc);
+ /* USER CODE BEGIN IPCC_C1_RX_IRQn 1 */
+
+ /* USER CODE END IPCC_C1_RX_IRQn 1 */
+}
+
+/**
+ * @brief This function handles IPCC TX free interrupt.
+ */
+void IPCC_C1_TX_IRQHandler(void)
+{
+ /* USER CODE BEGIN IPCC_C1_TX_IRQn 0 */
+
+ /* USER CODE END IPCC_C1_TX_IRQn 0 */
+ HAL_IPCC_TX_IRQHandler(&hipcc);
+ /* USER CODE BEGIN IPCC_C1_TX_IRQn 1 */
+
+ /* USER CODE END IPCC_C1_TX_IRQn 1 */
+}
+
+/**
+ * @brief This function handles HSEM global interrupt.
+ */
+void HSEM_IRQHandler(void)
+{
+ /* USER CODE BEGIN HSEM_IRQn 0 */
+
+ /* USER CODE END HSEM_IRQn 0 */
+ HAL_HSEM_IRQHandler();
+ /* USER CODE BEGIN HSEM_IRQn 1 */
+
+ /* USER CODE END HSEM_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
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