diff options
Diffstat (limited to 'firmware/memory_chip_gone/Debug/memory_chip_gone.list')
| -rw-r--r-- | firmware/memory_chip_gone/Debug/memory_chip_gone.list | 21728 |
1 files changed, 21728 insertions, 0 deletions
diff --git a/firmware/memory_chip_gone/Debug/memory_chip_gone.list b/firmware/memory_chip_gone/Debug/memory_chip_gone.list new file mode 100644 index 0000000..01ef641 --- /dev/null +++ b/firmware/memory_chip_gone/Debug/memory_chip_gone.list @@ -0,0 +1,21728 @@ + +memory_chip_gone.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 0000013c 08000000 08000000 00001000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 00007a78 0800013c 0800013c 0000113c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 0000026c 08007bb4 08007bb4 00008bb4 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM 00000008 08007e20 08007e20 00008e20 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .init_array 00000004 08007e28 08007e28 00008e28 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .fini_array 00000004 08007e2c 08007e2c 00008e2c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 6 .data 00000024 20000008 08007e30 00009008 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 BLE_DRIVER_CONTEXT 0000003d 2000002c 08007e54 0000902c 2**2 + CONTENTS, ALLOC, LOAD, DATA + 8 SYSTEM_DRIVER_CONTEXT 00000011 2000006c 08007e91 0000906c 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 00000324 20000080 08007ea2 00009080 2**2 + ALLOC + 10 ._user_heap_stack 00000604 200003a4 08007ea2 000093a4 2**0 + ALLOC + 11 .ARM.attributes 00000030 00000000 00000000 00009a67 2**0 + CONTENTS, READONLY + 12 MAPPING_TABLE 00000028 20030000 20030000 0000a000 2**2 + ALLOC + 13 MB_MEM1 000001bb 20030028 20030028 0000a000 2**2 + ALLOC + 14 .MB_MEM2 00000883 200301e4 08007ea2 000091e4 2**2 + CONTENTS, ALLOC, LOAD, DATA + 15 .debug_info 000262b1 00000000 00000000 00009a97 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_abbrev 000053bb 00000000 00000000 0002fd48 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_aranges 00002470 00000000 00000000 00035108 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_rnglists 00001bc3 00000000 00000000 00037578 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_macro 0002ad32 00000000 00000000 0003913b 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_line 00025a3c 00000000 00000000 00063e6d 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_str 000f314c 00000000 00000000 000898a9 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .comment 00000043 00000000 00000000 0017c9f5 2**0 + CONTENTS, READONLY + 23 .debug_frame 000097bc 00000000 00000000 0017ca38 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_line_str 00000068 00000000 00000000 001861f4 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +0800013c <__do_global_dtors_aux>: + 800013c: b510 push {r4, lr} + 800013e: 4c05 ldr r4, [pc, #20] @ (8000154 <__do_global_dtors_aux+0x18>) + 8000140: 7823 ldrb r3, [r4, #0] + 8000142: b933 cbnz r3, 8000152 <__do_global_dtors_aux+0x16> + 8000144: 4b04 ldr r3, [pc, #16] @ (8000158 <__do_global_dtors_aux+0x1c>) + 8000146: b113 cbz r3, 800014e <__do_global_dtors_aux+0x12> + 8000148: 4804 ldr r0, [pc, #16] @ (800015c <__do_global_dtors_aux+0x20>) + 800014a: f3af 8000 nop.w + 800014e: 2301 movs r3, #1 + 8000150: 7023 strb r3, [r4, #0] + 8000152: bd10 pop {r4, pc} + 8000154: 20000080 .word 0x20000080 + 8000158: 00000000 .word 0x00000000 + 800015c: 08007b9c .word 0x08007b9c + +08000160 <frame_dummy>: + 8000160: b508 push {r3, lr} + 8000162: 4b03 ldr r3, [pc, #12] @ (8000170 <frame_dummy+0x10>) + 8000164: b11b cbz r3, 800016e <frame_dummy+0xe> + 8000166: 4903 ldr r1, [pc, #12] @ (8000174 <frame_dummy+0x14>) + 8000168: 4803 ldr r0, [pc, #12] @ (8000178 <frame_dummy+0x18>) + 800016a: f3af 8000 nop.w + 800016e: bd08 pop {r3, pc} + 8000170: 00000000 .word 0x00000000 + 8000174: 20000084 .word 0x20000084 + 8000178: 08007b9c .word 0x08007b9c + +0800017c <strlen>: + 800017c: 4603 mov r3, r0 + 800017e: f813 2b01 ldrb.w r2, [r3], #1 + 8000182: 2a00 cmp r2, #0 + 8000184: d1fb bne.n 800017e <strlen+0x2> + 8000186: 1a18 subs r0, r3, r0 + 8000188: 3801 subs r0, #1 + 800018a: 4770 bx lr + +0800018c <APPD_EnableCPU2>: +/* USER CODE END APPD_Init */ + return; +} + +void APPD_EnableCPU2( void ) +{ + 800018c: b5b0 push {r4, r5, r7, lr} + 800018e: b088 sub sp, #32 + 8000190: af00 add r7, sp, #0 +/* USER CODE BEGIN APPD_EnableCPU2 */ + SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket = + 8000192: 4b0b ldr r3, [pc, #44] @ (80001c0 <APPD_EnableCPU2+0x34>) + 8000194: 1d3c adds r4, r7, #4 + 8000196: 461d mov r5, r3 + 8000198: cd0f ldmia r5!, {r0, r1, r2, r3} + 800019a: c40f stmia r4!, {r0, r1, r2, r3} + 800019c: e895 0007 ldmia.w r5, {r0, r1, r2} + 80001a0: c403 stmia r4!, {r0, r1} + 80001a2: 8022 strh r2, [r4, #0] + 80001a4: 3402 adds r4, #2 + 80001a6: 0c13 lsrs r3, r2, #16 + 80001a8: 7023 strb r3, [r4, #0] + NBR_OF_TRACES_CONFIG_PARAMETERS, + NBR_OF_GENERAL_CONFIG_PARAMETERS} + }; + + /**< Traces channel initialization */ + TL_TRACES_Init( ); + 80001aa: f006 f9c5 bl 8006538 <TL_TRACES_Init> + + /** GPIO DEBUG Initialization */ + SHCI_C2_DEBUG_Init( &DebugCmdPacket ); + 80001ae: 1d3b adds r3, r7, #4 + 80001b0: 4618 mov r0, r3 + 80001b2: f005 fc52 bl 8005a5a <SHCI_C2_DEBUG_Init> + +/* USER CODE END APPD_EnableCPU2 */ + return; + 80001b6: bf00 nop +} + 80001b8: 3720 adds r7, #32 + 80001ba: 46bd mov sp, r7 + 80001bc: bdb0 pop {r4, r5, r7, pc} + 80001be: bf00 nop + 80001c0: 08007bb4 .word 0x08007bb4 + +080001c4 <LL_C2_PWR_SetPowerMode>: + * + * (*) Not available on devices STM32WB15xx, STM32WB10xx, STM32WB1Mxx + * @retval None + */ +__STATIC_INLINE void LL_C2_PWR_SetPowerMode(uint32_t LowPowerMode) +{ + 80001c4: b480 push {r7} + 80001c6: b083 sub sp, #12 + 80001c8: af00 add r7, sp, #0 + 80001ca: 6078 str r0, [r7, #4] + MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, LowPowerMode); + 80001cc: 4b07 ldr r3, [pc, #28] @ (80001ec <LL_C2_PWR_SetPowerMode+0x28>) + 80001ce: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 80001d2: f023 0207 bic.w r2, r3, #7 + 80001d6: 4905 ldr r1, [pc, #20] @ (80001ec <LL_C2_PWR_SetPowerMode+0x28>) + 80001d8: 687b ldr r3, [r7, #4] + 80001da: 4313 orrs r3, r2 + 80001dc: f8c1 3080 str.w r3, [r1, #128] @ 0x80 +} + 80001e0: bf00 nop + 80001e2: 370c adds r7, #12 + 80001e4: 46bd mov sp, r7 + 80001e6: f85d 7b04 ldr.w r7, [sp], #4 + 80001ea: 4770 bx lr + 80001ec: 58000400 .word 0x58000400 + +080001f0 <LL_EXTI_EnableIT_32_63>: + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) +{ + 80001f0: b480 push {r7} + 80001f2: b083 sub sp, #12 + 80001f4: af00 add r7, sp, #0 + 80001f6: 6078 str r0, [r7, #4] + SET_BIT(EXTI->IMR2, ExtiLine); + 80001f8: 4b06 ldr r3, [pc, #24] @ (8000214 <LL_EXTI_EnableIT_32_63+0x24>) + 80001fa: f8d3 2090 ldr.w r2, [r3, #144] @ 0x90 + 80001fe: 4905 ldr r1, [pc, #20] @ (8000214 <LL_EXTI_EnableIT_32_63+0x24>) + 8000200: 687b ldr r3, [r7, #4] + 8000202: 4313 orrs r3, r2 + 8000204: f8c1 3090 str.w r3, [r1, #144] @ 0x90 +} + 8000208: bf00 nop + 800020a: 370c adds r7, #12 + 800020c: 46bd mov sp, r7 + 800020e: f85d 7b04 ldr.w r7, [sp], #4 + 8000212: 4770 bx lr + 8000214: 58000800 .word 0x58000800 + +08000218 <LL_RCC_HSE_SetCapacitorTuning>: + * @rmtoll HSECR HSETUNE LL_RCC_HSE_SetCapacitorTuning + * @param Value Between Min_Data = 0 and Max_Data = 63 + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_SetCapacitorTuning(uint32_t Value) +{ + 8000218: b480 push {r7} + 800021a: b083 sub sp, #12 + 800021c: af00 add r7, sp, #0 + 800021e: 6078 str r0, [r7, #4] + WRITE_REG(RCC->HSECR, HSE_CONTROL_UNLOCK_KEY); + 8000220: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000224: 4a0a ldr r2, [pc, #40] @ (8000250 <LL_RCC_HSE_SetCapacitorTuning+0x38>) + 8000226: f8c3 209c str.w r2, [r3, #156] @ 0x9c + MODIFY_REG(RCC->HSECR, RCC_HSECR_HSETUNE, Value << RCC_HSECR_HSETUNE_Pos); + 800022a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800022e: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c + 8000232: f423 527c bic.w r2, r3, #16128 @ 0x3f00 + 8000236: 687b ldr r3, [r7, #4] + 8000238: 021b lsls r3, r3, #8 + 800023a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800023e: 4313 orrs r3, r2 + 8000240: f8c1 309c str.w r3, [r1, #156] @ 0x9c +} + 8000244: bf00 nop + 8000246: 370c adds r7, #12 + 8000248: 46bd mov sp, r7 + 800024a: f85d 7b04 ldr.w r7, [sp], #4 + 800024e: 4770 bx lr + 8000250: cafecafe .word 0xcafecafe + +08000254 <LL_RCC_SetClkAfterWakeFromStop>: + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock) +{ + 8000254: b480 push {r7} + 8000256: b083 sub sp, #12 + 8000258: af00 add r7, sp, #0 + 800025a: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock); + 800025c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000260: 689b ldr r3, [r3, #8] + 8000262: f423 4200 bic.w r2, r3, #32768 @ 0x8000 + 8000266: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800026a: 687b ldr r3, [r7, #4] + 800026c: 4313 orrs r3, r2 + 800026e: 608b str r3, [r1, #8] +} + 8000270: bf00 nop + 8000272: 370c adds r7, #12 + 8000274: 46bd mov sp, r7 + 8000276: f85d 7b04 ldr.w r7, [sp], #4 + 800027a: 4770 bx lr + +0800027c <LL_DBGMCU_GetDeviceID>: + * @note For STM32WBxxxx devices, the device ID is 0x495 + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFF (ex: device ID is 0x495) + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + 800027c: b480 push {r7} + 800027e: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); + 8000280: 4b04 ldr r3, [pc, #16] @ (8000294 <LL_DBGMCU_GetDeviceID+0x18>) + 8000282: 681b ldr r3, [r3, #0] + 8000284: f3c3 030b ubfx r3, r3, #0, #12 +} + 8000288: 4618 mov r0, r3 + 800028a: 46bd mov sp, r7 + 800028c: f85d 7b04 ldr.w r7, [sp], #4 + 8000290: 4770 bx lr + 8000292: bf00 nop + 8000294: e0042000 .word 0xe0042000 + +08000298 <LL_DBGMCU_GetRevisionID>: + * @note This field indicates the revision of the device. + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + 8000298: b480 push {r7} + 800029a: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); + 800029c: 4b04 ldr r3, [pc, #16] @ (80002b0 <LL_DBGMCU_GetRevisionID+0x18>) + 800029e: 681b ldr r3, [r3, #0] + 80002a0: 0c1b lsrs r3, r3, #16 + 80002a2: b29b uxth r3, r3 +} + 80002a4: 4618 mov r0, r3 + 80002a6: 46bd mov sp, r7 + 80002a8: f85d 7b04 ldr.w r7, [sp], #4 + 80002ac: 4770 bx lr + 80002ae: bf00 nop + 80002b0: e0042000 .word 0xe0042000 + +080002b4 <LL_LPM_EnableSleep>: + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + 80002b4: b480 push {r7} + 80002b6: af00 add r7, sp, #0 + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 80002b8: 4b05 ldr r3, [pc, #20] @ (80002d0 <LL_LPM_EnableSleep+0x1c>) + 80002ba: 691b ldr r3, [r3, #16] + 80002bc: 4a04 ldr r2, [pc, #16] @ (80002d0 <LL_LPM_EnableSleep+0x1c>) + 80002be: f023 0304 bic.w r3, r3, #4 + 80002c2: 6113 str r3, [r2, #16] +} + 80002c4: bf00 nop + 80002c6: 46bd mov sp, r7 + 80002c8: f85d 7b04 ldr.w r7, [sp], #4 + 80002cc: 4770 bx lr + 80002ce: bf00 nop + 80002d0: e000ed00 .word 0xe000ed00 + +080002d4 <LL_RTC_EnableWriteProtection>: + * @rmtoll WPR KEY LL_RTC_EnableWriteProtection + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx) +{ + 80002d4: b480 push {r7} + 80002d6: b083 sub sp, #12 + 80002d8: af00 add r7, sp, #0 + 80002da: 6078 str r0, [r7, #4] + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE); + 80002dc: 687b ldr r3, [r7, #4] + 80002de: 22ff movs r2, #255 @ 0xff + 80002e0: 625a str r2, [r3, #36] @ 0x24 +} + 80002e2: bf00 nop + 80002e4: 370c adds r7, #12 + 80002e6: 46bd mov sp, r7 + 80002e8: f85d 7b04 ldr.w r7, [sp], #4 + 80002ec: 4770 bx lr + +080002ee <LL_RTC_DisableWriteProtection>: + * @rmtoll WPR KEY LL_RTC_DisableWriteProtection + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx) +{ + 80002ee: b480 push {r7} + 80002f0: b083 sub sp, #12 + 80002f2: af00 add r7, sp, #0 + 80002f4: 6078 str r0, [r7, #4] + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1); + 80002f6: 687b ldr r3, [r7, #4] + 80002f8: 22ca movs r2, #202 @ 0xca + 80002fa: 625a str r2, [r3, #36] @ 0x24 + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2); + 80002fc: 687b ldr r3, [r7, #4] + 80002fe: 2253 movs r2, #83 @ 0x53 + 8000300: 625a str r2, [r3, #36] @ 0x24 +} + 8000302: bf00 nop + 8000304: 370c adds r7, #12 + 8000306: 46bd mov sp, r7 + 8000308: f85d 7b04 ldr.w r7, [sp], #4 + 800030c: 4770 bx lr + +0800030e <LL_RTC_WAKEUP_SetClock>: + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock) +{ + 800030e: b480 push {r7} + 8000310: b083 sub sp, #12 + 8000312: af00 add r7, sp, #0 + 8000314: 6078 str r0, [r7, #4] + 8000316: 6039 str r1, [r7, #0] + MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock); + 8000318: 687b ldr r3, [r7, #4] + 800031a: 689b ldr r3, [r3, #8] + 800031c: f023 0207 bic.w r2, r3, #7 + 8000320: 683b ldr r3, [r7, #0] + 8000322: 431a orrs r2, r3 + 8000324: 687b ldr r3, [r7, #4] + 8000326: 609a str r2, [r3, #8] +} + 8000328: bf00 nop + 800032a: 370c adds r7, #12 + 800032c: 46bd mov sp, r7 + 800032e: f85d 7b04 ldr.w r7, [sp], #4 + 8000332: 4770 bx lr + +08000334 <MX_APPE_Config>: + +/* USER CODE END PFP */ + +/* Functions Definition ------------------------------------------------------*/ +void MX_APPE_Config(void) +{ + 8000334: b580 push {r7, lr} + 8000336: af00 add r7, sp, #0 + /** + * The OPTVERR flag is wrongly set at power on + * It shall be cleared before using any HAL_FLASH_xxx() api + */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); + 8000338: 4b04 ldr r3, [pc, #16] @ (800034c <MX_APPE_Config+0x18>) + 800033a: f44f 4200 mov.w r2, #32768 @ 0x8000 + 800033e: 611a str r2, [r3, #16] + + /** + * Reset some configurations so that the system behave in the same way + * when either out of nReset or Power On + */ + Reset_Device(); + 8000340: f000 f824 bl 800038c <Reset_Device> + + /* Configure HSE Tuning */ + Config_HSE(); + 8000344: f000 f829 bl 800039a <Config_HSE> + + return; + 8000348: bf00 nop +} + 800034a: bd80 pop {r7, pc} + 800034c: 58004000 .word 0x58004000 + +08000350 <MX_APPE_Init>: + +void MX_APPE_Init(void) +{ + 8000350: b580 push {r7, lr} + 8000352: af00 add r7, sp, #0 + System_Init(); /**< System initialization */ + 8000354: f000 f835 bl 80003c2 <System_Init> + + SystemPower_Config(); /**< Configure the system Power Mode */ + 8000358: f000 f84e bl 80003f8 <SystemPower_Config> + + HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */ + 800035c: 4903 ldr r1, [pc, #12] @ (800036c <MX_APPE_Init+0x1c>) + 800035e: 2000 movs r0, #0 + 8000360: f000 fcc6 bl 8000cf0 <HW_TS_Init> + +/* USER CODE BEGIN APPE_Init_1 */ + +/* USER CODE END APPE_Init_1 */ + appe_Tl_Init(); /* Initialize all transport layers */ + 8000364: f000 f856 bl 8000414 <appe_Tl_Init> + */ +/* USER CODE BEGIN APPE_Init_2 */ + +/* USER CODE END APPE_Init_2 */ + + return; + 8000368: bf00 nop +} + 800036a: bd80 pop {r7, pc} + 800036c: 200001cc .word 0x200001cc + +08000370 <Init_Smps>: + +void Init_Smps(void) +{ + 8000370: b480 push {r7} + 8000372: af00 add r7, sp, #0 + LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA); + LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40); + LL_PWR_SMPS_Enable(); +#endif /* CFG_USE_SMPS != 0 */ + + return; + 8000374: bf00 nop +} + 8000376: 46bd mov sp, r7 + 8000378: f85d 7b04 ldr.w r7, [sp], #4 + 800037c: 4770 bx lr + +0800037e <Init_Exti>: + +void Init_Exti(void) +{ + 800037e: b580 push {r7, lr} + 8000380: af00 add r7, sp, #0 + /* Enable IPCC(36), HSEM(38) wakeup interrupts on CPU1 */ + LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_36 | LL_EXTI_LINE_38); + 8000382: 2050 movs r0, #80 @ 0x50 + 8000384: f7ff ff34 bl 80001f0 <LL_EXTI_EnableIT_32_63> + + return; + 8000388: bf00 nop +} + 800038a: bd80 pop {r7, pc} + +0800038c <Reset_Device>: + * + * LOCAL FUNCTIONS + * + *************************************************************/ +static void Reset_Device(void) +{ + 800038c: b480 push {r7} + 800038e: af00 add r7, sp, #0 + Reset_BackupDomain(); + + Reset_IPCC(); +#endif /* CFG_HW_RESET_BY_FW == 1 */ + + return; + 8000390: bf00 nop +} + 8000392: 46bd mov sp, r7 + 8000394: f85d 7b04 ldr.w r7, [sp], #4 + 8000398: 4770 bx lr + +0800039a <Config_HSE>: + return; +} +#endif /* CFG_HW_RESET_BY_FW == 1 */ + +static void Config_HSE(void) +{ + 800039a: b580 push {r7, lr} + 800039c: b082 sub sp, #8 + 800039e: af00 add r7, sp, #0 + OTP_ID0_t * p_otp; + + /** + * Read HSE_Tuning from OTP + */ + p_otp = (OTP_ID0_t *) OTP_Read(0); + 80003a0: 2000 movs r0, #0 + 80003a2: f006 f95d bl 8006660 <OTP_Read> + 80003a6: 6078 str r0, [r7, #4] + if (p_otp) + 80003a8: 687b ldr r3, [r7, #4] + 80003aa: 2b00 cmp r3, #0 + 80003ac: d005 beq.n 80003ba <Config_HSE+0x20> + { + LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning); + 80003ae: 687b ldr r3, [r7, #4] + 80003b0: 799b ldrb r3, [r3, #6] + 80003b2: 4618 mov r0, r3 + 80003b4: f7ff ff30 bl 8000218 <LL_RCC_HSE_SetCapacitorTuning> + } + + return; + 80003b8: bf00 nop + 80003ba: bf00 nop +} + 80003bc: 3708 adds r7, #8 + 80003be: 46bd mov sp, r7 + 80003c0: bd80 pop {r7, pc} + +080003c2 <System_Init>: + +static void System_Init(void) +{ + 80003c2: b580 push {r7, lr} + 80003c4: af00 add r7, sp, #0 + Init_Smps(); + 80003c6: f7ff ffd3 bl 8000370 <Init_Smps> + + Init_Exti(); + 80003ca: f7ff ffd8 bl 800037e <Init_Exti> + + Init_Rtc(); + 80003ce: f000 f803 bl 80003d8 <Init_Rtc> + + return; + 80003d2: bf00 nop +} + 80003d4: bd80 pop {r7, pc} + ... + +080003d8 <Init_Rtc>: + +static void Init_Rtc(void) +{ + 80003d8: b580 push {r7, lr} + 80003da: af00 add r7, sp, #0 + /* Disable RTC registers write protection */ + LL_RTC_DisableWriteProtection(RTC); + 80003dc: 4805 ldr r0, [pc, #20] @ (80003f4 <Init_Rtc+0x1c>) + 80003de: f7ff ff86 bl 80002ee <LL_RTC_DisableWriteProtection> + + LL_RTC_WAKEUP_SetClock(RTC, CFG_RTC_WUCKSEL_DIVIDER); + 80003e2: 2100 movs r1, #0 + 80003e4: 4803 ldr r0, [pc, #12] @ (80003f4 <Init_Rtc+0x1c>) + 80003e6: f7ff ff92 bl 800030e <LL_RTC_WAKEUP_SetClock> + + /* Enable RTC registers write protection */ + LL_RTC_EnableWriteProtection(RTC); + 80003ea: 4802 ldr r0, [pc, #8] @ (80003f4 <Init_Rtc+0x1c>) + 80003ec: f7ff ff72 bl 80002d4 <LL_RTC_EnableWriteProtection> + + return; + 80003f0: bf00 nop +} + 80003f2: bd80 pop {r7, pc} + 80003f4: 40002800 .word 0x40002800 + +080003f8 <SystemPower_Config>: + * + * @param None + * @retval None + */ +static void SystemPower_Config(void) +{ + 80003f8: b580 push {r7, lr} + 80003fa: af00 add r7, sp, #0 + /** + * Select HSI as system clock source after Wake Up from Stop mode + */ + LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI); + 80003fc: f44f 4000 mov.w r0, #32768 @ 0x8000 + 8000400: f7ff ff28 bl 8000254 <LL_RCC_SetClkAfterWakeFromStop> + + /* Initialize low power manager */ + UTIL_LPM_Init(); + 8000404: f007 f880 bl 8007508 <UTIL_LPM_Init> + /* Initialize the CPU2 reset value before starting CPU2 with C2BOOT */ + LL_C2_PWR_SetPowerMode(LL_PWR_MODE_SHUTDOWN); + 8000408: 2004 movs r0, #4 + 800040a: f7ff fedb bl 80001c4 <LL_C2_PWR_SetPowerMode> + * Enable USB power + */ + HAL_PWREx_EnableVddUSB(); +#endif /* CFG_USB_INTERFACE_ENABLE != 0 */ + + return; + 800040e: bf00 nop +} + 8000410: bd80 pop {r7, pc} + ... + +08000414 <appe_Tl_Init>: + +static void appe_Tl_Init(void) +{ + 8000414: b580 push {r7, lr} + 8000416: b088 sub sp, #32 + 8000418: af00 add r7, sp, #0 + TL_MM_Config_t tl_mm_config; + SHCI_TL_HciInitConf_t SHci_Tl_Init_Conf; + /**< Reference table initialization */ + TL_Init(); + 800041a: f005 fed3 bl 80061c4 <TL_Init> + + /**< System channel initialization */ + UTIL_SEQ_RegTask(1<< CFG_TASK_SYSTEM_HCI_ASYNCH_EVT_ID, UTIL_SEQ_RFU, shci_user_evt_proc); + 800041e: 4a11 ldr r2, [pc, #68] @ (8000464 <appe_Tl_Init+0x50>) + 8000420: 2100 movs r1, #0 + 8000422: 2004 movs r0, #4 + 8000424: f007 fa34 bl 8007890 <UTIL_SEQ_RegTask> + SHci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&SystemCmdBuffer; + 8000428: 4b0f ldr r3, [pc, #60] @ (8000468 <appe_Tl_Init+0x54>) + 800042a: 603b str r3, [r7, #0] + SHci_Tl_Init_Conf.StatusNotCallBack = APPE_SysStatusNot; + 800042c: 4b0f ldr r3, [pc, #60] @ (800046c <appe_Tl_Init+0x58>) + 800042e: 607b str r3, [r7, #4] + shci_init(APPE_SysUserEvtRx, (void*) &SHci_Tl_Init_Conf); + 8000430: 463b mov r3, r7 + 8000432: 4619 mov r1, r3 + 8000434: 480e ldr r0, [pc, #56] @ (8000470 <appe_Tl_Init+0x5c>) + 8000436: f005 fd87 bl 8005f48 <shci_init> + + /**< Memory Manager channel initialization */ + tl_mm_config.p_BleSpareEvtBuffer = BleSpareEvtBuffer; + 800043a: 4b0e ldr r3, [pc, #56] @ (8000474 <appe_Tl_Init+0x60>) + 800043c: 60bb str r3, [r7, #8] + tl_mm_config.p_SystemSpareEvtBuffer = SystemSpareEvtBuffer; + 800043e: 4b0e ldr r3, [pc, #56] @ (8000478 <appe_Tl_Init+0x64>) + 8000440: 60fb str r3, [r7, #12] + tl_mm_config.p_AsynchEvtPool = EvtPool; + 8000442: 4b0e ldr r3, [pc, #56] @ (800047c <appe_Tl_Init+0x68>) + 8000444: 613b str r3, [r7, #16] + tl_mm_config.AsynchEvtPoolSize = POOL_SIZE; + 8000446: f240 533c movw r3, #1340 @ 0x53c + 800044a: 617b str r3, [r7, #20] + TL_MM_Init(&tl_mm_config); + 800044c: f107 0308 add.w r3, r7, #8 + 8000450: 4618 mov r0, r3 + 8000452: f005 fffd bl 8006450 <TL_MM_Init> + + TL_Enable(); + 8000456: f005 feaf bl 80061b8 <TL_Enable> + + return; + 800045a: bf00 nop +} + 800045c: 3720 adds r7, #32 + 800045e: 46bd mov sp, r7 + 8000460: bd80 pop {r7, pc} + 8000462: bf00 nop + 8000464: 08005f81 .word 0x08005f81 + 8000468: 20030734 .word 0x20030734 + 800046c: 08000481 .word 0x08000481 + 8000470: 08000499 .word 0x08000499 + 8000474: 2003094c .word 0x2003094c + 8000478: 20030840 .word 0x20030840 + 800047c: 200301f8 .word 0x200301f8 + +08000480 <APPE_SysStatusNot>: + +static void APPE_SysStatusNot(SHCI_TL_CmdStatus_t status) +{ + 8000480: b480 push {r7} + 8000482: b083 sub sp, #12 + 8000484: af00 add r7, sp, #0 + 8000486: 4603 mov r3, r0 + 8000488: 71fb strb r3, [r7, #7] + UNUSED(status); + return; + 800048a: bf00 nop +} + 800048c: 370c adds r7, #12 + 800048e: 46bd mov sp, r7 + 8000490: f85d 7b04 ldr.w r7, [sp], #4 + 8000494: 4770 bx lr + ... + +08000498 <APPE_SysUserEvtRx>: + * The buffer shall not be released + * (eg ((tSHCI_UserEvtRxParam*)pPayload)->status shall be set to SHCI_TL_UserEventFlow_Disable) + * When the status is not filled, the buffer is released by default + */ +static void APPE_SysUserEvtRx(void * pPayload) +{ + 8000498: b580 push {r7, lr} + 800049a: b088 sub sp, #32 + 800049c: af00 add r7, sp, #0 + 800049e: 6078 str r0, [r7, #4] + TL_AsynchEvt_t *p_sys_event; + WirelessFwInfo_t WirelessInfo; + + p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload); + 80004a0: 687b ldr r3, [r7, #4] + 80004a2: 685b ldr r3, [r3, #4] + 80004a4: 330b adds r3, #11 + 80004a6: 61fb str r3, [r7, #28] + + switch(p_sys_event->subevtcode) + 80004a8: 69fb ldr r3, [r7, #28] + 80004aa: 881b ldrh r3, [r3, #0] + 80004ac: b29b uxth r3, r3 + 80004ae: f5a3 4312 sub.w r3, r3, #37376 @ 0x9200 + 80004b2: 2b07 cmp r3, #7 + 80004b4: d81f bhi.n 80004f6 <APPE_SysUserEvtRx+0x5e> + 80004b6: a201 add r2, pc, #4 @ (adr r2, 80004bc <APPE_SysUserEvtRx+0x24>) + 80004b8: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80004bc: 080004dd .word 0x080004dd + 80004c0: 080004ef .word 0x080004ef + 80004c4: 080004f7 .word 0x080004f7 + 80004c8: 080004f7 .word 0x080004f7 + 80004cc: 080004f7 .word 0x080004f7 + 80004d0: 080004f7 .word 0x080004f7 + 80004d4: 080004f7 .word 0x080004f7 + 80004d8: 080004f7 .word 0x080004f7 + { + case SHCI_SUB_EVT_CODE_READY: + /* Read the firmware version of both the wireless firmware and the FUS */ + SHCI_GetWirelessFwInfo(&WirelessInfo); + 80004dc: f107 030c add.w r3, r7, #12 + 80004e0: 4618 mov r0, r3 + 80004e2: f005 fae7 bl 8005ab4 <SHCI_GetWirelessFwInfo> + APP_DBG_MSG("Wireless Firmware version %d.%d.%d\n", WirelessInfo.VersionMajor, WirelessInfo.VersionMinor, WirelessInfo.VersionSub); + APP_DBG_MSG("Wireless Firmware build %d\n", WirelessInfo.VersionReleaseType); + APP_DBG_MSG("FUS version %d.%d.%d\n", WirelessInfo.FusVersionMajor, WirelessInfo.FusVersionMinor, WirelessInfo.FusVersionSub); + + APP_DBG_MSG(">>== SHCI_SUB_EVT_CODE_READY\n\r"); + APPE_SysEvtReadyProcessing(pPayload); + 80004e6: 6878 ldr r0, [r7, #4] + 80004e8: f000 f81b bl 8000522 <APPE_SysEvtReadyProcessing> + break; + 80004ec: e004 b.n 80004f8 <APPE_SysUserEvtRx+0x60> + + case SHCI_SUB_EVT_ERROR_NOTIF: + APP_DBG_MSG(">>== SHCI_SUB_EVT_ERROR_NOTIF \n\r"); + APPE_SysEvtError(pPayload); + 80004ee: 6878 ldr r0, [r7, #4] + 80004f0: f000 f806 bl 8000500 <APPE_SysEvtError> + break; + 80004f4: e000 b.n 80004f8 <APPE_SysUserEvtRx+0x60> + case SHCI_SUB_EVT_NVM_END_ERASE: + APP_DBG_MSG(">>== SHCI_SUB_EVT_NVM_END_ERASE\n\r"); + break; + + default: + break; + 80004f6: bf00 nop + } + + return; + 80004f8: bf00 nop +} + 80004fa: 3720 adds r7, #32 + 80004fc: 46bd mov sp, r7 + 80004fe: bd80 pop {r7, pc} + +08000500 <APPE_SysEvtError>: + * @param ErrorCode : errorCode detected by the M0 firmware + * + * @retval None + */ +static void APPE_SysEvtError(void * pPayload) +{ + 8000500: b480 push {r7} + 8000502: b085 sub sp, #20 + 8000504: af00 add r7, sp, #0 + 8000506: 6078 str r0, [r7, #4] + TL_AsynchEvt_t *p_sys_event; + SCHI_SystemErrCode_t *p_sys_error_code; + + p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload); + 8000508: 687b ldr r3, [r7, #4] + 800050a: 685b ldr r3, [r3, #4] + 800050c: 330b adds r3, #11 + 800050e: 60fb str r3, [r7, #12] + p_sys_error_code = (SCHI_SystemErrCode_t*) p_sys_event->payload; + 8000510: 68fb ldr r3, [r7, #12] + 8000512: 3302 adds r3, #2 + 8000514: 60bb str r3, [r7, #8] + } + else + { + APP_DBG_MSG(">>== SHCI_SUB_EVT_ERROR_NOTIF WITH REASON - BLE ERROR \n"); + } + return; + 8000516: bf00 nop +} + 8000518: 3714 adds r7, #20 + 800051a: 46bd mov sp, r7 + 800051c: f85d 7b04 ldr.w r7, [sp], #4 + 8000520: 4770 bx lr + +08000522 <APPE_SysEvtReadyProcessing>: + +static void APPE_SysEvtReadyProcessing(void * pPayload) +{ + 8000522: b580 push {r7, lr} + 8000524: b08a sub sp, #40 @ 0x28 + 8000526: af00 add r7, sp, #0 + 8000528: 6078 str r0, [r7, #4] + TL_AsynchEvt_t *p_sys_event; + SHCI_C2_Ready_Evt_t *p_sys_ready_event; + + SHCI_C2_CONFIG_Cmd_Param_t config_param = {0}; + 800052a: f107 0308 add.w r3, r7, #8 + 800052e: 2200 movs r2, #0 + 8000530: 601a str r2, [r3, #0] + 8000532: 605a str r2, [r3, #4] + 8000534: 609a str r2, [r3, #8] + 8000536: 60da str r2, [r3, #12] + uint32_t RevisionID=0; + 8000538: 2300 movs r3, #0 + 800053a: 627b str r3, [r7, #36] @ 0x24 + uint32_t DeviceID=0; + 800053c: 2300 movs r3, #0 + 800053e: 623b str r3, [r7, #32] + + p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload); + 8000540: 687b ldr r3, [r7, #4] + 8000542: 685b ldr r3, [r3, #4] + 8000544: 330b adds r3, #11 + 8000546: 61fb str r3, [r7, #28] + p_sys_ready_event = (SHCI_C2_Ready_Evt_t*) p_sys_event->payload; + 8000548: 69fb ldr r3, [r7, #28] + 800054a: 3302 adds r3, #2 + 800054c: 61bb str r3, [r7, #24] + + if (p_sys_ready_event->sysevt_ready_rsp == WIRELESS_FW_RUNNING) + 800054e: 69bb ldr r3, [r7, #24] + 8000550: 781b ldrb r3, [r3, #0] + 8000552: 2b00 cmp r3, #0 + 8000554: d11d bne.n 8000592 <APPE_SysEvtReadyProcessing+0x70> + * The wireless firmware is running on the CPU2 + */ + APP_DBG_MSG(">>== WIRELESS_FW_RUNNING \n"); + + /* Traces channel initialization */ + APPD_EnableCPU2(); + 8000556: f7ff fe19 bl 800018c <APPD_EnableCPU2> + + /* Enable all events Notification */ + config_param.PayloadCmdSize = SHCI_C2_CONFIG_PAYLOAD_CMD_SIZE; + 800055a: 230f movs r3, #15 + 800055c: 723b strb r3, [r7, #8] + config_param.EvtMask1 = SHCI_C2_CONFIG_EVTMASK1_BIT0_ERROR_NOTIF_ENABLE + 800055e: 237f movs r3, #127 @ 0x7f + 8000560: 72bb strb r3, [r7, #10] + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ + RevisionID = LL_DBGMCU_GetRevisionID(); + 8000562: f7ff fe99 bl 8000298 <LL_DBGMCU_GetRevisionID> + 8000566: 6278 str r0, [r7, #36] @ 0x24 + + APP_DBG_MSG(">>== DBGMCU_GetRevisionID= %lx \n\r", RevisionID); + + config_param.RevisionID = (uint16_t)RevisionID; + 8000568: 6a7b ldr r3, [r7, #36] @ 0x24 + 800056a: b29b uxth r3, r3 + 800056c: 82bb strh r3, [r7, #20] + + DeviceID = LL_DBGMCU_GetDeviceID(); + 800056e: f7ff fe85 bl 800027c <LL_DBGMCU_GetDeviceID> + 8000572: 6238 str r0, [r7, #32] + APP_DBG_MSG(">>== DBGMCU_GetDeviceID= %lx \n\r", DeviceID); + config_param.DeviceID = (uint16_t)DeviceID; + 8000574: 6a3b ldr r3, [r7, #32] + 8000576: b29b uxth r3, r3 + 8000578: 82fb strh r3, [r7, #22] + (void)SHCI_C2_Config(&config_param); + 800057a: f107 0308 add.w r3, r7, #8 + 800057e: 4618 mov r0, r3 + 8000580: f005 fa82 bl 8005a88 <SHCI_C2_Config> + + APP_BLE_Init(); + 8000584: f006 f976 bl 8006874 <APP_BLE_Init> + UTIL_LPM_SetOffMode(1U << CFG_LPM_APP, UTIL_LPM_ENABLE); + 8000588: 2100 movs r1, #0 + 800058a: 2001 movs r0, #1 + 800058c: f006 ffce bl 800752c <UTIL_LPM_SetOffMode> + else + { + APP_DBG_MSG(">>== SHCI_SUB_EVT_CODE_READY - UNEXPECTED CASE \n\r"); + } + + return; + 8000590: e007 b.n 80005a2 <APPE_SysEvtReadyProcessing+0x80> + else if (p_sys_ready_event->sysevt_ready_rsp == FUS_FW_RUNNING) + 8000592: 69bb ldr r3, [r7, #24] + 8000594: 781b ldrb r3, [r3, #0] + 8000596: 2b01 cmp r3, #1 + 8000598: d103 bne.n 80005a2 <APPE_SysEvtReadyProcessing+0x80> + ((tSHCI_UserEvtRxParam*)pPayload)->status = SHCI_TL_UserEventFlow_Disable; + 800059a: 687b ldr r3, [r7, #4] + 800059c: 2200 movs r2, #0 + 800059e: 701a strb r2, [r3, #0] + return; + 80005a0: bf00 nop + 80005a2: bf00 nop +} + 80005a4: 3728 adds r7, #40 @ 0x28 + 80005a6: 46bd mov sp, r7 + 80005a8: bd80 pop {r7, pc} + +080005aa <HAL_Delay>: + * + * WRAP FUNCTIONS + * + *************************************************************/ +void HAL_Delay(uint32_t Delay) +{ + 80005aa: b580 push {r7, lr} + 80005ac: b084 sub sp, #16 + 80005ae: af00 add r7, sp, #0 + 80005b0: 6078 str r0, [r7, #4] + uint32_t tickstart = HAL_GetTick(); + 80005b2: f001 f9f7 bl 80019a4 <HAL_GetTick> + 80005b6: 60b8 str r0, [r7, #8] + uint32_t wait = Delay; + 80005b8: 687b ldr r3, [r7, #4] + 80005ba: 60fb str r3, [r7, #12] + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + 80005bc: 68fb ldr r3, [r7, #12] + 80005be: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80005c2: d00a beq.n 80005da <HAL_Delay+0x30> + { + wait += HAL_GetTickFreq(); + 80005c4: f001 fa06 bl 80019d4 <HAL_GetTickFreq> + 80005c8: 4603 mov r3, r0 + 80005ca: 461a mov r2, r3 + 80005cc: 68fb ldr r3, [r7, #12] + 80005ce: 4413 add r3, r2 + 80005d0: 60fb str r3, [r7, #12] + } + + while ((HAL_GetTick() - tickstart) < wait) + 80005d2: e002 b.n 80005da <HAL_Delay+0x30> + { + /************************************************************************************ + * ENTER SLEEP MODE + ***********************************************************************************/ + LL_LPM_EnableSleep(); /**< Clear SLEEPDEEP bit of Cortex System Control Register */ + 80005d4: f7ff fe6e bl 80002b4 <LL_LPM_EnableSleep> + */ + #if defined (__CC_ARM) || defined (__ARMCC_VERSION) + __force_stores(); + #endif /* __ARMCC_VERSION */ + + __WFI(); + 80005d8: bf30 wfi + while ((HAL_GetTick() - tickstart) < wait) + 80005da: f001 f9e3 bl 80019a4 <HAL_GetTick> + 80005de: 4602 mov r2, r0 + 80005e0: 68bb ldr r3, [r7, #8] + 80005e2: 1ad3 subs r3, r2, r3 + 80005e4: 68fa ldr r2, [r7, #12] + 80005e6: 429a cmp r2, r3 + 80005e8: d8f4 bhi.n 80005d4 <HAL_Delay+0x2a> + } +} + 80005ea: bf00 nop + 80005ec: bf00 nop + 80005ee: 3710 adds r7, #16 + 80005f0: 46bd mov sp, r7 + 80005f2: bd80 pop {r7, pc} + +080005f4 <MX_APPE_Process>: + +void MX_APPE_Process(void) +{ + 80005f4: b580 push {r7, lr} + 80005f6: af00 add r7, sp, #0 + /* USER CODE BEGIN MX_APPE_Process_1 */ + + /* USER CODE END MX_APPE_Process_1 */ + UTIL_SEQ_Run(UTIL_SEQ_DEFAULT); + 80005f8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 80005fc: f006 ffc6 bl 800758c <UTIL_SEQ_Run> + /* USER CODE BEGIN MX_APPE_Process_2 */ + + /* USER CODE END MX_APPE_Process_2 */ +} + 8000600: bf00 nop + 8000602: bd80 pop {r7, pc} + +08000604 <UTIL_SEQ_Idle>: + +void UTIL_SEQ_Idle(void) +{ + 8000604: b480 push {r7} + 8000606: af00 add r7, sp, #0 +#if (CFG_LPM_SUPPORTED == 1) + UTIL_LPM_EnterLowPower(); +#endif /* CFG_LPM_SUPPORTED == 1 */ + return; + 8000608: bf00 nop +} + 800060a: 46bd mov sp, r7 + 800060c: f85d 7b04 ldr.w r7, [sp], #4 + 8000610: 4770 bx lr + +08000612 <shci_notify_asynch_evt>: + +void shci_notify_asynch_evt(void* pdata) +{ + 8000612: b580 push {r7, lr} + 8000614: b082 sub sp, #8 + 8000616: af00 add r7, sp, #0 + 8000618: 6078 str r0, [r7, #4] + UTIL_SEQ_SetTask(1<<CFG_TASK_SYSTEM_HCI_ASYNCH_EVT_ID, CFG_SCH_PRIO_0); + 800061a: 2100 movs r1, #0 + 800061c: 2004 movs r0, #4 + 800061e: f007 f959 bl 80078d4 <UTIL_SEQ_SetTask> + return; + 8000622: bf00 nop +} + 8000624: 3708 adds r7, #8 + 8000626: 46bd mov sp, r7 + 8000628: bd80 pop {r7, pc} + +0800062a <shci_cmd_resp_release>: + +void shci_cmd_resp_release(uint32_t flag) +{ + 800062a: b580 push {r7, lr} + 800062c: b082 sub sp, #8 + 800062e: af00 add r7, sp, #0 + 8000630: 6078 str r0, [r7, #4] + UTIL_SEQ_SetEvt(1<< CFG_IDLEEVT_SYSTEM_HCI_CMD_EVT_RSP_ID); + 8000632: 2002 movs r0, #2 + 8000634: f007 f9ba bl 80079ac <UTIL_SEQ_SetEvt> + return; + 8000638: bf00 nop +} + 800063a: 3708 adds r7, #8 + 800063c: 46bd mov sp, r7 + 800063e: bd80 pop {r7, pc} + +08000640 <shci_cmd_resp_wait>: + +void shci_cmd_resp_wait(uint32_t timeout) +{ + 8000640: b580 push {r7, lr} + 8000642: b082 sub sp, #8 + 8000644: af00 add r7, sp, #0 + 8000646: 6078 str r0, [r7, #4] + UTIL_SEQ_WaitEvt(1<< CFG_IDLEEVT_SYSTEM_HCI_CMD_EVT_RSP_ID); + 8000648: 2002 movs r0, #2 + 800064a: f007 f9cf bl 80079ec <UTIL_SEQ_WaitEvt> + return; + 800064e: bf00 nop +} + 8000650: 3708 adds r7, #8 + 8000652: 46bd mov sp, r7 + 8000654: bd80 pop {r7, pc} + ... + +08000658 <LL_EXTI_EnableIT_0_31>: +{ + 8000658: b480 push {r7} + 800065a: b083 sub sp, #12 + 800065c: af00 add r7, sp, #0 + 800065e: 6078 str r0, [r7, #4] + SET_BIT(EXTI->IMR1, ExtiLine); + 8000660: 4b06 ldr r3, [pc, #24] @ (800067c <LL_EXTI_EnableIT_0_31+0x24>) + 8000662: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 + 8000666: 4905 ldr r1, [pc, #20] @ (800067c <LL_EXTI_EnableIT_0_31+0x24>) + 8000668: 687b ldr r3, [r7, #4] + 800066a: 4313 orrs r3, r2 + 800066c: f8c1 3080 str.w r3, [r1, #128] @ 0x80 +} + 8000670: bf00 nop + 8000672: 370c adds r7, #12 + 8000674: 46bd mov sp, r7 + 8000676: f85d 7b04 ldr.w r7, [sp], #4 + 800067a: 4770 bx lr + 800067c: 58000800 .word 0x58000800 + +08000680 <LL_EXTI_EnableRisingTrig_0_31>: + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + 8000680: b480 push {r7} + 8000682: b083 sub sp, #12 + 8000684: af00 add r7, sp, #0 + 8000686: 6078 str r0, [r7, #4] + SET_BIT(EXTI->RTSR1, ExtiLine); + 8000688: 4b05 ldr r3, [pc, #20] @ (80006a0 <LL_EXTI_EnableRisingTrig_0_31+0x20>) + 800068a: 681a ldr r2, [r3, #0] + 800068c: 4904 ldr r1, [pc, #16] @ (80006a0 <LL_EXTI_EnableRisingTrig_0_31+0x20>) + 800068e: 687b ldr r3, [r7, #4] + 8000690: 4313 orrs r3, r2 + 8000692: 600b str r3, [r1, #0] + +} + 8000694: bf00 nop + 8000696: 370c adds r7, #12 + 8000698: 46bd mov sp, r7 + 800069a: f85d 7b04 ldr.w r7, [sp], #4 + 800069e: 4770 bx lr + 80006a0: 58000800 .word 0x58000800 + +080006a4 <ReadRtcSsrValue>: + * reliability of the value + * @param None + * @retval SSR value read + */ +static uint32_t ReadRtcSsrValue(void) +{ + 80006a4: b480 push {r7} + 80006a6: b083 sub sp, #12 + 80006a8: af00 add r7, sp, #0 + uint32_t first_read; + uint32_t second_read; + + first_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS)); + 80006aa: 4b0d ldr r3, [pc, #52] @ (80006e0 <ReadRtcSsrValue+0x3c>) + 80006ac: 6a9b ldr r3, [r3, #40] @ 0x28 + 80006ae: b29b uxth r3, r3 + 80006b0: 607b str r3, [r7, #4] + + second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS)); + 80006b2: 4b0b ldr r3, [pc, #44] @ (80006e0 <ReadRtcSsrValue+0x3c>) + 80006b4: 6a9b ldr r3, [r3, #40] @ 0x28 + 80006b6: b29b uxth r3, r3 + 80006b8: 603b str r3, [r7, #0] + + while(first_read != second_read) + 80006ba: e005 b.n 80006c8 <ReadRtcSsrValue+0x24> + { + first_read = second_read; + 80006bc: 683b ldr r3, [r7, #0] + 80006be: 607b str r3, [r7, #4] + + second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS)); + 80006c0: 4b07 ldr r3, [pc, #28] @ (80006e0 <ReadRtcSsrValue+0x3c>) + 80006c2: 6a9b ldr r3, [r3, #40] @ 0x28 + 80006c4: b29b uxth r3, r3 + 80006c6: 603b str r3, [r7, #0] + while(first_read != second_read) + 80006c8: 687a ldr r2, [r7, #4] + 80006ca: 683b ldr r3, [r7, #0] + 80006cc: 429a cmp r2, r3 + 80006ce: d1f5 bne.n 80006bc <ReadRtcSsrValue+0x18> + } + + return second_read; + 80006d0: 683b ldr r3, [r7, #0] +} + 80006d2: 4618 mov r0, r3 + 80006d4: 370c adds r7, #12 + 80006d6: 46bd mov sp, r7 + 80006d8: f85d 7b04 ldr.w r7, [sp], #4 + 80006dc: 4770 bx lr + 80006de: bf00 nop + 80006e0: 40002800 .word 0x40002800 + +080006e4 <LinkTimerAfter>: + * @param TimerID: The ID of the Timer + * @param RefTimerID: The ID of the Timer to be linked after + * @retval None + */ +static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID) +{ + 80006e4: b480 push {r7} + 80006e6: b085 sub sp, #20 + 80006e8: af00 add r7, sp, #0 + 80006ea: 4603 mov r3, r0 + 80006ec: 460a mov r2, r1 + 80006ee: 71fb strb r3, [r7, #7] + 80006f0: 4613 mov r3, r2 + 80006f2: 71bb strb r3, [r7, #6] + uint8_t next_id; + + next_id = aTimerContext[RefTimerID].NextID; + 80006f4: 79ba ldrb r2, [r7, #6] + 80006f6: 491d ldr r1, [pc, #116] @ (800076c <LinkTimerAfter+0x88>) + 80006f8: 4613 mov r3, r2 + 80006fa: 005b lsls r3, r3, #1 + 80006fc: 4413 add r3, r2 + 80006fe: 00db lsls r3, r3, #3 + 8000700: 440b add r3, r1 + 8000702: 3315 adds r3, #21 + 8000704: 781b ldrb r3, [r3, #0] + 8000706: 73fb strb r3, [r7, #15] + + if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) + 8000708: 7bfb ldrb r3, [r7, #15] + 800070a: 2b06 cmp r3, #6 + 800070c: d009 beq.n 8000722 <LinkTimerAfter+0x3e> + { + aTimerContext[next_id].PreviousID = TimerID; + 800070e: 7bfa ldrb r2, [r7, #15] + 8000710: 4916 ldr r1, [pc, #88] @ (800076c <LinkTimerAfter+0x88>) + 8000712: 4613 mov r3, r2 + 8000714: 005b lsls r3, r3, #1 + 8000716: 4413 add r3, r2 + 8000718: 00db lsls r3, r3, #3 + 800071a: 440b add r3, r1 + 800071c: 3314 adds r3, #20 + 800071e: 79fa ldrb r2, [r7, #7] + 8000720: 701a strb r2, [r3, #0] + } + aTimerContext[TimerID].NextID = next_id; + 8000722: 79fa ldrb r2, [r7, #7] + 8000724: 4911 ldr r1, [pc, #68] @ (800076c <LinkTimerAfter+0x88>) + 8000726: 4613 mov r3, r2 + 8000728: 005b lsls r3, r3, #1 + 800072a: 4413 add r3, r2 + 800072c: 00db lsls r3, r3, #3 + 800072e: 440b add r3, r1 + 8000730: 3315 adds r3, #21 + 8000732: 7bfa ldrb r2, [r7, #15] + 8000734: 701a strb r2, [r3, #0] + aTimerContext[TimerID].PreviousID = RefTimerID ; + 8000736: 79fa ldrb r2, [r7, #7] + 8000738: 490c ldr r1, [pc, #48] @ (800076c <LinkTimerAfter+0x88>) + 800073a: 4613 mov r3, r2 + 800073c: 005b lsls r3, r3, #1 + 800073e: 4413 add r3, r2 + 8000740: 00db lsls r3, r3, #3 + 8000742: 440b add r3, r1 + 8000744: 3314 adds r3, #20 + 8000746: 79ba ldrb r2, [r7, #6] + 8000748: 701a strb r2, [r3, #0] + aTimerContext[RefTimerID].NextID = TimerID; + 800074a: 79ba ldrb r2, [r7, #6] + 800074c: 4907 ldr r1, [pc, #28] @ (800076c <LinkTimerAfter+0x88>) + 800074e: 4613 mov r3, r2 + 8000750: 005b lsls r3, r3, #1 + 8000752: 4413 add r3, r2 + 8000754: 00db lsls r3, r3, #3 + 8000756: 440b add r3, r1 + 8000758: 3315 adds r3, #21 + 800075a: 79fa ldrb r2, [r7, #7] + 800075c: 701a strb r2, [r3, #0] + + return; + 800075e: bf00 nop +} + 8000760: 3714 adds r7, #20 + 8000762: 46bd mov sp, r7 + 8000764: f85d 7b04 ldr.w r7, [sp], #4 + 8000768: 4770 bx lr + 800076a: bf00 nop + 800076c: 2000009c .word 0x2000009c + +08000770 <LinkTimerBefore>: + * @param TimerID: The ID of the Timer + * @param RefTimerID: The ID of the Timer to be linked before + * @retval None + */ +static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID) +{ + 8000770: b480 push {r7} + 8000772: b085 sub sp, #20 + 8000774: af00 add r7, sp, #0 + 8000776: 4603 mov r3, r0 + 8000778: 460a mov r2, r1 + 800077a: 71fb strb r3, [r7, #7] + 800077c: 4613 mov r3, r2 + 800077e: 71bb strb r3, [r7, #6] + uint8_t previous_id; + + if(RefTimerID != CurrentRunningTimerID) + 8000780: 4b29 ldr r3, [pc, #164] @ (8000828 <LinkTimerBefore+0xb8>) + 8000782: 781b ldrb r3, [r3, #0] + 8000784: b2db uxtb r3, r3 + 8000786: 79ba ldrb r2, [r7, #6] + 8000788: 429a cmp r2, r3 + 800078a: d032 beq.n 80007f2 <LinkTimerBefore+0x82> + { + previous_id = aTimerContext[RefTimerID].PreviousID; + 800078c: 79ba ldrb r2, [r7, #6] + 800078e: 4927 ldr r1, [pc, #156] @ (800082c <LinkTimerBefore+0xbc>) + 8000790: 4613 mov r3, r2 + 8000792: 005b lsls r3, r3, #1 + 8000794: 4413 add r3, r2 + 8000796: 00db lsls r3, r3, #3 + 8000798: 440b add r3, r1 + 800079a: 3314 adds r3, #20 + 800079c: 781b ldrb r3, [r3, #0] + 800079e: 73fb strb r3, [r7, #15] + + aTimerContext[previous_id].NextID = TimerID; + 80007a0: 7bfa ldrb r2, [r7, #15] + 80007a2: 4922 ldr r1, [pc, #136] @ (800082c <LinkTimerBefore+0xbc>) + 80007a4: 4613 mov r3, r2 + 80007a6: 005b lsls r3, r3, #1 + 80007a8: 4413 add r3, r2 + 80007aa: 00db lsls r3, r3, #3 + 80007ac: 440b add r3, r1 + 80007ae: 3315 adds r3, #21 + 80007b0: 79fa ldrb r2, [r7, #7] + 80007b2: 701a strb r2, [r3, #0] + aTimerContext[TimerID].NextID = RefTimerID; + 80007b4: 79fa ldrb r2, [r7, #7] + 80007b6: 491d ldr r1, [pc, #116] @ (800082c <LinkTimerBefore+0xbc>) + 80007b8: 4613 mov r3, r2 + 80007ba: 005b lsls r3, r3, #1 + 80007bc: 4413 add r3, r2 + 80007be: 00db lsls r3, r3, #3 + 80007c0: 440b add r3, r1 + 80007c2: 3315 adds r3, #21 + 80007c4: 79ba ldrb r2, [r7, #6] + 80007c6: 701a strb r2, [r3, #0] + aTimerContext[TimerID].PreviousID = previous_id ; + 80007c8: 79fa ldrb r2, [r7, #7] + 80007ca: 4918 ldr r1, [pc, #96] @ (800082c <LinkTimerBefore+0xbc>) + 80007cc: 4613 mov r3, r2 + 80007ce: 005b lsls r3, r3, #1 + 80007d0: 4413 add r3, r2 + 80007d2: 00db lsls r3, r3, #3 + 80007d4: 440b add r3, r1 + 80007d6: 3314 adds r3, #20 + 80007d8: 7bfa ldrb r2, [r7, #15] + 80007da: 701a strb r2, [r3, #0] + aTimerContext[RefTimerID].PreviousID = TimerID; + 80007dc: 79ba ldrb r2, [r7, #6] + 80007de: 4913 ldr r1, [pc, #76] @ (800082c <LinkTimerBefore+0xbc>) + 80007e0: 4613 mov r3, r2 + 80007e2: 005b lsls r3, r3, #1 + 80007e4: 4413 add r3, r2 + 80007e6: 00db lsls r3, r3, #3 + 80007e8: 440b add r3, r1 + 80007ea: 3314 adds r3, #20 + 80007ec: 79fa ldrb r2, [r7, #7] + 80007ee: 701a strb r2, [r3, #0] + { + aTimerContext[TimerID].NextID = RefTimerID; + aTimerContext[RefTimerID].PreviousID = TimerID; + } + + return; + 80007f0: e014 b.n 800081c <LinkTimerBefore+0xac> + aTimerContext[TimerID].NextID = RefTimerID; + 80007f2: 79fa ldrb r2, [r7, #7] + 80007f4: 490d ldr r1, [pc, #52] @ (800082c <LinkTimerBefore+0xbc>) + 80007f6: 4613 mov r3, r2 + 80007f8: 005b lsls r3, r3, #1 + 80007fa: 4413 add r3, r2 + 80007fc: 00db lsls r3, r3, #3 + 80007fe: 440b add r3, r1 + 8000800: 3315 adds r3, #21 + 8000802: 79ba ldrb r2, [r7, #6] + 8000804: 701a strb r2, [r3, #0] + aTimerContext[RefTimerID].PreviousID = TimerID; + 8000806: 79ba ldrb r2, [r7, #6] + 8000808: 4908 ldr r1, [pc, #32] @ (800082c <LinkTimerBefore+0xbc>) + 800080a: 4613 mov r3, r2 + 800080c: 005b lsls r3, r3, #1 + 800080e: 4413 add r3, r2 + 8000810: 00db lsls r3, r3, #3 + 8000812: 440b add r3, r1 + 8000814: 3314 adds r3, #20 + 8000816: 79fa ldrb r2, [r7, #7] + 8000818: 701a strb r2, [r3, #0] + return; + 800081a: bf00 nop +} + 800081c: 3714 adds r7, #20 + 800081e: 46bd mov sp, r7 + 8000820: f85d 7b04 ldr.w r7, [sp], #4 + 8000824: 4770 bx lr + 8000826: bf00 nop + 8000828: 2000012c .word 0x2000012c + 800082c: 2000009c .word 0x2000009c + +08000830 <linkTimer>: + * @brief Insert a Timer in the list + * @param TimerID: The ID of the Timer + * @retval None + */ +static uint16_t linkTimer(uint8_t TimerID) +{ + 8000830: b580 push {r7, lr} + 8000832: b084 sub sp, #16 + 8000834: af00 add r7, sp, #0 + 8000836: 4603 mov r3, r0 + 8000838: 71fb strb r3, [r7, #7] + uint32_t time_left; + uint16_t time_elapsed; + uint8_t timer_id_lookup; + uint8_t next_id; + + if(CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) + 800083a: 4b4e ldr r3, [pc, #312] @ (8000974 <linkTimer+0x144>) + 800083c: 781b ldrb r3, [r3, #0] + 800083e: b2db uxtb r3, r3 + 8000840: 2b06 cmp r3, #6 + 8000842: d118 bne.n 8000876 <linkTimer+0x46> + { + /** + * No timer in the list + */ + PreviousRunningTimerID = CurrentRunningTimerID; + 8000844: 4b4b ldr r3, [pc, #300] @ (8000974 <linkTimer+0x144>) + 8000846: 781b ldrb r3, [r3, #0] + 8000848: b2da uxtb r2, r3 + 800084a: 4b4b ldr r3, [pc, #300] @ (8000978 <linkTimer+0x148>) + 800084c: 701a strb r2, [r3, #0] + CurrentRunningTimerID = TimerID; + 800084e: 4a49 ldr r2, [pc, #292] @ (8000974 <linkTimer+0x144>) + 8000850: 79fb ldrb r3, [r7, #7] + 8000852: 7013 strb r3, [r2, #0] + aTimerContext[TimerID].NextID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; + 8000854: 79fa ldrb r2, [r7, #7] + 8000856: 4949 ldr r1, [pc, #292] @ (800097c <linkTimer+0x14c>) + 8000858: 4613 mov r3, r2 + 800085a: 005b lsls r3, r3, #1 + 800085c: 4413 add r3, r2 + 800085e: 00db lsls r3, r3, #3 + 8000860: 440b add r3, r1 + 8000862: 3315 adds r3, #21 + 8000864: 2206 movs r2, #6 + 8000866: 701a strb r2, [r3, #0] + + SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE; + 8000868: 4b45 ldr r3, [pc, #276] @ (8000980 <linkTimer+0x150>) + 800086a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 800086e: 601a str r2, [r3, #0] + time_elapsed = 0; + 8000870: 2300 movs r3, #0 + 8000872: 81fb strh r3, [r7, #14] + 8000874: e078 b.n 8000968 <linkTimer+0x138> + } + else + { + time_elapsed = ReturnTimeElapsed(); + 8000876: f000 f909 bl 8000a8c <ReturnTimeElapsed> + 800087a: 4603 mov r3, r0 + 800087c: 81fb strh r3, [r7, #14] + + /** + * update count of the timer to be linked + */ + aTimerContext[TimerID].CountLeft += time_elapsed; + 800087e: 79fa ldrb r2, [r7, #7] + 8000880: 493e ldr r1, [pc, #248] @ (800097c <linkTimer+0x14c>) + 8000882: 4613 mov r3, r2 + 8000884: 005b lsls r3, r3, #1 + 8000886: 4413 add r3, r2 + 8000888: 00db lsls r3, r3, #3 + 800088a: 440b add r3, r1 + 800088c: 3308 adds r3, #8 + 800088e: 6819 ldr r1, [r3, #0] + 8000890: 89fb ldrh r3, [r7, #14] + 8000892: 79fa ldrb r2, [r7, #7] + 8000894: 4419 add r1, r3 + 8000896: 4839 ldr r0, [pc, #228] @ (800097c <linkTimer+0x14c>) + 8000898: 4613 mov r3, r2 + 800089a: 005b lsls r3, r3, #1 + 800089c: 4413 add r3, r2 + 800089e: 00db lsls r3, r3, #3 + 80008a0: 4403 add r3, r0 + 80008a2: 3308 adds r3, #8 + 80008a4: 6019 str r1, [r3, #0] + time_left = aTimerContext[TimerID].CountLeft; + 80008a6: 79fa ldrb r2, [r7, #7] + 80008a8: 4934 ldr r1, [pc, #208] @ (800097c <linkTimer+0x14c>) + 80008aa: 4613 mov r3, r2 + 80008ac: 005b lsls r3, r3, #1 + 80008ae: 4413 add r3, r2 + 80008b0: 00db lsls r3, r3, #3 + 80008b2: 440b add r3, r1 + 80008b4: 3308 adds r3, #8 + 80008b6: 681b ldr r3, [r3, #0] + 80008b8: 60bb str r3, [r7, #8] + + /** + * Search for index where the new timer shall be linked + */ + if(aTimerContext[CurrentRunningTimerID].CountLeft <= time_left) + 80008ba: 4b2e ldr r3, [pc, #184] @ (8000974 <linkTimer+0x144>) + 80008bc: 781b ldrb r3, [r3, #0] + 80008be: b2db uxtb r3, r3 + 80008c0: 4619 mov r1, r3 + 80008c2: 4a2e ldr r2, [pc, #184] @ (800097c <linkTimer+0x14c>) + 80008c4: 460b mov r3, r1 + 80008c6: 005b lsls r3, r3, #1 + 80008c8: 440b add r3, r1 + 80008ca: 00db lsls r3, r3, #3 + 80008cc: 4413 add r3, r2 + 80008ce: 3308 adds r3, #8 + 80008d0: 681b ldr r3, [r3, #0] + 80008d2: 68ba ldr r2, [r7, #8] + 80008d4: 429a cmp r2, r3 + 80008d6: d337 bcc.n 8000948 <linkTimer+0x118> + { + /** + * Search for the ID after the first one + */ + timer_id_lookup = CurrentRunningTimerID; + 80008d8: 4b26 ldr r3, [pc, #152] @ (8000974 <linkTimer+0x144>) + 80008da: 781b ldrb r3, [r3, #0] + 80008dc: 737b strb r3, [r7, #13] + next_id = aTimerContext[timer_id_lookup].NextID; + 80008de: 7b7a ldrb r2, [r7, #13] + 80008e0: 4926 ldr r1, [pc, #152] @ (800097c <linkTimer+0x14c>) + 80008e2: 4613 mov r3, r2 + 80008e4: 005b lsls r3, r3, #1 + 80008e6: 4413 add r3, r2 + 80008e8: 00db lsls r3, r3, #3 + 80008ea: 440b add r3, r1 + 80008ec: 3315 adds r3, #21 + 80008ee: 781b ldrb r3, [r3, #0] + 80008f0: 733b strb r3, [r7, #12] + while((next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[next_id].CountLeft <= time_left)) + 80008f2: e013 b.n 800091c <linkTimer+0xec> + { + timer_id_lookup = aTimerContext[timer_id_lookup].NextID; + 80008f4: 7b7a ldrb r2, [r7, #13] + 80008f6: 4921 ldr r1, [pc, #132] @ (800097c <linkTimer+0x14c>) + 80008f8: 4613 mov r3, r2 + 80008fa: 005b lsls r3, r3, #1 + 80008fc: 4413 add r3, r2 + 80008fe: 00db lsls r3, r3, #3 + 8000900: 440b add r3, r1 + 8000902: 3315 adds r3, #21 + 8000904: 781b ldrb r3, [r3, #0] + 8000906: 737b strb r3, [r7, #13] + next_id = aTimerContext[timer_id_lookup].NextID; + 8000908: 7b7a ldrb r2, [r7, #13] + 800090a: 491c ldr r1, [pc, #112] @ (800097c <linkTimer+0x14c>) + 800090c: 4613 mov r3, r2 + 800090e: 005b lsls r3, r3, #1 + 8000910: 4413 add r3, r2 + 8000912: 00db lsls r3, r3, #3 + 8000914: 440b add r3, r1 + 8000916: 3315 adds r3, #21 + 8000918: 781b ldrb r3, [r3, #0] + 800091a: 733b strb r3, [r7, #12] + while((next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[next_id].CountLeft <= time_left)) + 800091c: 7b3b ldrb r3, [r7, #12] + 800091e: 2b06 cmp r3, #6 + 8000920: d00b beq.n 800093a <linkTimer+0x10a> + 8000922: 7b3a ldrb r2, [r7, #12] + 8000924: 4915 ldr r1, [pc, #84] @ (800097c <linkTimer+0x14c>) + 8000926: 4613 mov r3, r2 + 8000928: 005b lsls r3, r3, #1 + 800092a: 4413 add r3, r2 + 800092c: 00db lsls r3, r3, #3 + 800092e: 440b add r3, r1 + 8000930: 3308 adds r3, #8 + 8000932: 681b ldr r3, [r3, #0] + 8000934: 68ba ldr r2, [r7, #8] + 8000936: 429a cmp r2, r3 + 8000938: d2dc bcs.n 80008f4 <linkTimer+0xc4> + } + + /** + * Link after the ID + */ + LinkTimerAfter(TimerID, timer_id_lookup); + 800093a: 7b7a ldrb r2, [r7, #13] + 800093c: 79fb ldrb r3, [r7, #7] + 800093e: 4611 mov r1, r2 + 8000940: 4618 mov r0, r3 + 8000942: f7ff fecf bl 80006e4 <LinkTimerAfter> + 8000946: e00f b.n 8000968 <linkTimer+0x138> + else + { + /** + * Link before the first ID + */ + LinkTimerBefore(TimerID, CurrentRunningTimerID); + 8000948: 4b0a ldr r3, [pc, #40] @ (8000974 <linkTimer+0x144>) + 800094a: 781b ldrb r3, [r3, #0] + 800094c: b2da uxtb r2, r3 + 800094e: 79fb ldrb r3, [r7, #7] + 8000950: 4611 mov r1, r2 + 8000952: 4618 mov r0, r3 + 8000954: f7ff ff0c bl 8000770 <LinkTimerBefore> + PreviousRunningTimerID = CurrentRunningTimerID; + 8000958: 4b06 ldr r3, [pc, #24] @ (8000974 <linkTimer+0x144>) + 800095a: 781b ldrb r3, [r3, #0] + 800095c: b2da uxtb r2, r3 + 800095e: 4b06 ldr r3, [pc, #24] @ (8000978 <linkTimer+0x148>) + 8000960: 701a strb r2, [r3, #0] + CurrentRunningTimerID = TimerID; + 8000962: 4a04 ldr r2, [pc, #16] @ (8000974 <linkTimer+0x144>) + 8000964: 79fb ldrb r3, [r7, #7] + 8000966: 7013 strb r3, [r2, #0] + } + } + + return time_elapsed; + 8000968: 89fb ldrh r3, [r7, #14] +} + 800096a: 4618 mov r0, r3 + 800096c: 3710 adds r7, #16 + 800096e: 46bd mov sp, r7 + 8000970: bd80 pop {r7, pc} + 8000972: bf00 nop + 8000974: 2000012c .word 0x2000012c + 8000978: 2000012d .word 0x2000012d + 800097c: 2000009c .word 0x2000009c + 8000980: 20000130 .word 0x20000130 + +08000984 <UnlinkTimer>: + * @param TimerID: The ID of the Timer + * @param RequestReadSSR: Request to read the SSR register or not + * @retval None + */ +static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR) +{ + 8000984: b480 push {r7} + 8000986: b085 sub sp, #20 + 8000988: af00 add r7, sp, #0 + 800098a: 4603 mov r3, r0 + 800098c: 460a mov r2, r1 + 800098e: 71fb strb r3, [r7, #7] + 8000990: 4613 mov r3, r2 + 8000992: 71bb strb r3, [r7, #6] + uint8_t previous_id; + uint8_t next_id; + + if(TimerID == CurrentRunningTimerID) + 8000994: 4b39 ldr r3, [pc, #228] @ (8000a7c <UnlinkTimer+0xf8>) + 8000996: 781b ldrb r3, [r3, #0] + 8000998: b2db uxtb r3, r3 + 800099a: 79fa ldrb r2, [r7, #7] + 800099c: 429a cmp r2, r3 + 800099e: d111 bne.n 80009c4 <UnlinkTimer+0x40> + { + PreviousRunningTimerID = CurrentRunningTimerID; + 80009a0: 4b36 ldr r3, [pc, #216] @ (8000a7c <UnlinkTimer+0xf8>) + 80009a2: 781b ldrb r3, [r3, #0] + 80009a4: b2da uxtb r2, r3 + 80009a6: 4b36 ldr r3, [pc, #216] @ (8000a80 <UnlinkTimer+0xfc>) + 80009a8: 701a strb r2, [r3, #0] + CurrentRunningTimerID = aTimerContext[TimerID].NextID; + 80009aa: 79fa ldrb r2, [r7, #7] + 80009ac: 4935 ldr r1, [pc, #212] @ (8000a84 <UnlinkTimer+0x100>) + 80009ae: 4613 mov r3, r2 + 80009b0: 005b lsls r3, r3, #1 + 80009b2: 4413 add r3, r2 + 80009b4: 00db lsls r3, r3, #3 + 80009b6: 440b add r3, r1 + 80009b8: 3315 adds r3, #21 + 80009ba: 781b ldrb r3, [r3, #0] + 80009bc: b2da uxtb r2, r3 + 80009be: 4b2f ldr r3, [pc, #188] @ (8000a7c <UnlinkTimer+0xf8>) + 80009c0: 701a strb r2, [r3, #0] + 80009c2: e03e b.n 8000a42 <UnlinkTimer+0xbe> + } + else + { + previous_id = aTimerContext[TimerID].PreviousID; + 80009c4: 79fa ldrb r2, [r7, #7] + 80009c6: 492f ldr r1, [pc, #188] @ (8000a84 <UnlinkTimer+0x100>) + 80009c8: 4613 mov r3, r2 + 80009ca: 005b lsls r3, r3, #1 + 80009cc: 4413 add r3, r2 + 80009ce: 00db lsls r3, r3, #3 + 80009d0: 440b add r3, r1 + 80009d2: 3314 adds r3, #20 + 80009d4: 781b ldrb r3, [r3, #0] + 80009d6: 73fb strb r3, [r7, #15] + next_id = aTimerContext[TimerID].NextID; + 80009d8: 79fa ldrb r2, [r7, #7] + 80009da: 492a ldr r1, [pc, #168] @ (8000a84 <UnlinkTimer+0x100>) + 80009dc: 4613 mov r3, r2 + 80009de: 005b lsls r3, r3, #1 + 80009e0: 4413 add r3, r2 + 80009e2: 00db lsls r3, r3, #3 + 80009e4: 440b add r3, r1 + 80009e6: 3315 adds r3, #21 + 80009e8: 781b ldrb r3, [r3, #0] + 80009ea: 73bb strb r3, [r7, #14] + + aTimerContext[previous_id].NextID = aTimerContext[TimerID].NextID; + 80009ec: 79f9 ldrb r1, [r7, #7] + 80009ee: 7bfa ldrb r2, [r7, #15] + 80009f0: 4824 ldr r0, [pc, #144] @ (8000a84 <UnlinkTimer+0x100>) + 80009f2: 460b mov r3, r1 + 80009f4: 005b lsls r3, r3, #1 + 80009f6: 440b add r3, r1 + 80009f8: 00db lsls r3, r3, #3 + 80009fa: 4403 add r3, r0 + 80009fc: 3315 adds r3, #21 + 80009fe: 781b ldrb r3, [r3, #0] + 8000a00: b2d8 uxtb r0, r3 + 8000a02: 4920 ldr r1, [pc, #128] @ (8000a84 <UnlinkTimer+0x100>) + 8000a04: 4613 mov r3, r2 + 8000a06: 005b lsls r3, r3, #1 + 8000a08: 4413 add r3, r2 + 8000a0a: 00db lsls r3, r3, #3 + 8000a0c: 440b add r3, r1 + 8000a0e: 3315 adds r3, #21 + 8000a10: 4602 mov r2, r0 + 8000a12: 701a strb r2, [r3, #0] + if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) + 8000a14: 7bbb ldrb r3, [r7, #14] + 8000a16: 2b06 cmp r3, #6 + 8000a18: d013 beq.n 8000a42 <UnlinkTimer+0xbe> + { + aTimerContext[next_id].PreviousID = aTimerContext[TimerID].PreviousID; + 8000a1a: 79f9 ldrb r1, [r7, #7] + 8000a1c: 7bba ldrb r2, [r7, #14] + 8000a1e: 4819 ldr r0, [pc, #100] @ (8000a84 <UnlinkTimer+0x100>) + 8000a20: 460b mov r3, r1 + 8000a22: 005b lsls r3, r3, #1 + 8000a24: 440b add r3, r1 + 8000a26: 00db lsls r3, r3, #3 + 8000a28: 4403 add r3, r0 + 8000a2a: 3314 adds r3, #20 + 8000a2c: 781b ldrb r3, [r3, #0] + 8000a2e: b2d8 uxtb r0, r3 + 8000a30: 4914 ldr r1, [pc, #80] @ (8000a84 <UnlinkTimer+0x100>) + 8000a32: 4613 mov r3, r2 + 8000a34: 005b lsls r3, r3, #1 + 8000a36: 4413 add r3, r2 + 8000a38: 00db lsls r3, r3, #3 + 8000a3a: 440b add r3, r1 + 8000a3c: 3314 adds r3, #20 + 8000a3e: 4602 mov r2, r0 + 8000a40: 701a strb r2, [r3, #0] + } + + /** + * Timer is out of the list + */ + aTimerContext[TimerID].TimerIDStatus = TimerID_Created; + 8000a42: 79fa ldrb r2, [r7, #7] + 8000a44: 490f ldr r1, [pc, #60] @ (8000a84 <UnlinkTimer+0x100>) + 8000a46: 4613 mov r3, r2 + 8000a48: 005b lsls r3, r3, #1 + 8000a4a: 4413 add r3, r2 + 8000a4c: 00db lsls r3, r3, #3 + 8000a4e: 440b add r3, r1 + 8000a50: 330c adds r3, #12 + 8000a52: 2201 movs r2, #1 + 8000a54: 701a strb r2, [r3, #0] + + if((CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (RequestReadSSR == SSR_Read_Requested)) + 8000a56: 4b09 ldr r3, [pc, #36] @ (8000a7c <UnlinkTimer+0xf8>) + 8000a58: 781b ldrb r3, [r3, #0] + 8000a5a: b2db uxtb r3, r3 + 8000a5c: 2b06 cmp r3, #6 + 8000a5e: d107 bne.n 8000a70 <UnlinkTimer+0xec> + 8000a60: 79bb ldrb r3, [r7, #6] + 8000a62: 2b00 cmp r3, #0 + 8000a64: d104 bne.n 8000a70 <UnlinkTimer+0xec> + { + SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE; + 8000a66: 4b08 ldr r3, [pc, #32] @ (8000a88 <UnlinkTimer+0x104>) + 8000a68: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8000a6c: 601a str r2, [r3, #0] + } + + return; + 8000a6e: bf00 nop + 8000a70: bf00 nop +} + 8000a72: 3714 adds r7, #20 + 8000a74: 46bd mov sp, r7 + 8000a76: f85d 7b04 ldr.w r7, [sp], #4 + 8000a7a: 4770 bx lr + 8000a7c: 2000012c .word 0x2000012c + 8000a80: 2000012d .word 0x2000012d + 8000a84: 2000009c .word 0x2000009c + 8000a88: 20000130 .word 0x20000130 + +08000a8c <ReturnTimeElapsed>: + * since the time the timer has been started + * @param None + * @retval Time expired in Ticks + */ +static uint16_t ReturnTimeElapsed(void) +{ + 8000a8c: b580 push {r7, lr} + 8000a8e: b082 sub sp, #8 + 8000a90: af00 add r7, sp, #0 + uint32_t return_value; + uint32_t wrap_counter; + + if(SSRValueOnLastSetup != SSR_FORBIDDEN_VALUE) + 8000a92: 4b1a ldr r3, [pc, #104] @ (8000afc <ReturnTimeElapsed+0x70>) + 8000a94: 681b ldr r3, [r3, #0] + 8000a96: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8000a9a: d026 beq.n 8000aea <ReturnTimeElapsed+0x5e> + { + return_value = ReadRtcSsrValue(); /**< Read SSR register first */ + 8000a9c: f7ff fe02 bl 80006a4 <ReadRtcSsrValue> + 8000aa0: 6078 str r0, [r7, #4] + + if (SSRValueOnLastSetup >= return_value) + 8000aa2: 4b16 ldr r3, [pc, #88] @ (8000afc <ReturnTimeElapsed+0x70>) + 8000aa4: 681b ldr r3, [r3, #0] + 8000aa6: 687a ldr r2, [r7, #4] + 8000aa8: 429a cmp r2, r3 + 8000aaa: d805 bhi.n 8000ab8 <ReturnTimeElapsed+0x2c> + { + return_value = SSRValueOnLastSetup - return_value; + 8000aac: 4b13 ldr r3, [pc, #76] @ (8000afc <ReturnTimeElapsed+0x70>) + 8000aae: 681a ldr r2, [r3, #0] + 8000ab0: 687b ldr r3, [r7, #4] + 8000ab2: 1ad3 subs r3, r2, r3 + 8000ab4: 607b str r3, [r7, #4] + 8000ab6: e00a b.n 8000ace <ReturnTimeElapsed+0x42> + } + else + { + wrap_counter = SynchPrescalerUserConfig - return_value; + 8000ab8: 4b11 ldr r3, [pc, #68] @ (8000b00 <ReturnTimeElapsed+0x74>) + 8000aba: 881b ldrh r3, [r3, #0] + 8000abc: 461a mov r2, r3 + 8000abe: 687b ldr r3, [r7, #4] + 8000ac0: 1ad3 subs r3, r2, r3 + 8000ac2: 603b str r3, [r7, #0] + return_value = SSRValueOnLastSetup + wrap_counter; + 8000ac4: 4b0d ldr r3, [pc, #52] @ (8000afc <ReturnTimeElapsed+0x70>) + 8000ac6: 681b ldr r3, [r3, #0] + 8000ac8: 683a ldr r2, [r7, #0] + 8000aca: 4413 add r3, r2 + 8000acc: 607b str r3, [r7, #4] + + /** + * At this stage, ReturnValue holds the number of ticks counted by SSR + * Need to translate in number of ticks counted by the Wakeuptimer + */ + return_value = return_value*AsynchPrescalerUserConfig; + 8000ace: 4b0d ldr r3, [pc, #52] @ (8000b04 <ReturnTimeElapsed+0x78>) + 8000ad0: 781b ldrb r3, [r3, #0] + 8000ad2: 461a mov r2, r3 + 8000ad4: 687b ldr r3, [r7, #4] + 8000ad6: fb02 f303 mul.w r3, r2, r3 + 8000ada: 607b str r3, [r7, #4] + return_value = return_value >> WakeupTimerDivider; + 8000adc: 4b0a ldr r3, [pc, #40] @ (8000b08 <ReturnTimeElapsed+0x7c>) + 8000ade: 781b ldrb r3, [r3, #0] + 8000ae0: 461a mov r2, r3 + 8000ae2: 687b ldr r3, [r7, #4] + 8000ae4: 40d3 lsrs r3, r2 + 8000ae6: 607b str r3, [r7, #4] + 8000ae8: e001 b.n 8000aee <ReturnTimeElapsed+0x62> + } + else + { + return_value = 0; + 8000aea: 2300 movs r3, #0 + 8000aec: 607b str r3, [r7, #4] + } + + return (uint16_t)return_value; + 8000aee: 687b ldr r3, [r7, #4] + 8000af0: b29b uxth r3, r3 +} + 8000af2: 4618 mov r0, r3 + 8000af4: 3708 adds r7, #8 + 8000af6: 46bd mov sp, r7 + 8000af8: bd80 pop {r7, pc} + 8000afa: bf00 nop + 8000afc: 20000130 .word 0x20000130 + 8000b00: 20000138 .word 0x20000138 + 8000b04: 20000136 .word 0x20000136 + 8000b08: 20000135 .word 0x20000135 + +08000b0c <RestartWakeupCounter>: + * It assumes all condition are met to be allowed to write the wakeup counter + * @param Value: Value to be written in the counter + * @retval None + */ +static void RestartWakeupCounter(uint16_t Value) +{ + 8000b0c: b580 push {r7, lr} + 8000b0e: b082 sub sp, #8 + 8000b10: af00 add r7, sp, #0 + 8000b12: 4603 mov r3, r0 + 8000b14: 80fb strh r3, [r7, #6] + * The wakeuptimer has been disabled in the calling function to reduce the time to poll the WUTWF + * FLAG when the new value will have to be written + * __HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); + */ + + if(Value == 0) + 8000b16: 88fb ldrh r3, [r7, #6] + 8000b18: 2b00 cmp r3, #0 + 8000b1a: d108 bne.n 8000b2e <RestartWakeupCounter+0x22> + { + SSRValueOnLastSetup = ReadRtcSsrValue(); + 8000b1c: f7ff fdc2 bl 80006a4 <ReadRtcSsrValue> + 8000b20: 4603 mov r3, r0 + 8000b22: 4a21 ldr r2, [pc, #132] @ (8000ba8 <RestartWakeupCounter+0x9c>) + 8000b24: 6013 str r3, [r2, #0] + + /** + * Simulate that the Timer expired + */ + HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); + 8000b26: 2003 movs r0, #3 + 8000b28: f001 f8dd bl 8001ce6 <HAL_NVIC_SetPendingIRQ> + __HAL_RTC_WAKEUPTIMER_ENABLE(&hrtc); /**< Enable the Wakeup Timer */ + + HW_TS_RTC_CountUpdated_AppNot(); + } + + return ; + 8000b2c: e039 b.n 8000ba2 <RestartWakeupCounter+0x96> + if((Value > 1) ||(WakeupTimerDivider != 1)) + 8000b2e: 88fb ldrh r3, [r7, #6] + 8000b30: 2b01 cmp r3, #1 + 8000b32: d803 bhi.n 8000b3c <RestartWakeupCounter+0x30> + 8000b34: 4b1d ldr r3, [pc, #116] @ (8000bac <RestartWakeupCounter+0xa0>) + 8000b36: 781b ldrb r3, [r3, #0] + 8000b38: 2b01 cmp r3, #1 + 8000b3a: d002 beq.n 8000b42 <RestartWakeupCounter+0x36> + Value -= 1; + 8000b3c: 88fb ldrh r3, [r7, #6] + 8000b3e: 3b01 subs r3, #1 + 8000b40: 80fb strh r3, [r7, #6] + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == RESET); + 8000b42: bf00 nop + 8000b44: 4b1a ldr r3, [pc, #104] @ (8000bb0 <RestartWakeupCounter+0xa4>) + 8000b46: 681b ldr r3, [r3, #0] + 8000b48: 68db ldr r3, [r3, #12] + 8000b4a: f003 0304 and.w r3, r3, #4 + 8000b4e: 2b00 cmp r3, #0 + 8000b50: d0f8 beq.n 8000b44 <RestartWakeupCounter+0x38> + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */ + 8000b52: 4b17 ldr r3, [pc, #92] @ (8000bb0 <RestartWakeupCounter+0xa4>) + 8000b54: 681b ldr r3, [r3, #0] + 8000b56: 68db ldr r3, [r3, #12] + 8000b58: b2da uxtb r2, r3 + 8000b5a: 4b15 ldr r3, [pc, #84] @ (8000bb0 <RestartWakeupCounter+0xa4>) + 8000b5c: 681b ldr r3, [r3, #0] + 8000b5e: f462 6290 orn r2, r2, #1152 @ 0x480 + 8000b62: 60da str r2, [r3, #12] + __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */ + 8000b64: 4b13 ldr r3, [pc, #76] @ (8000bb4 <RestartWakeupCounter+0xa8>) + 8000b66: f44f 2200 mov.w r2, #524288 @ 0x80000 + 8000b6a: 60da str r2, [r3, #12] + HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Clear pending bit in NVIC */ + 8000b6c: 2003 movs r0, #3 + 8000b6e: f001 f8c8 bl 8001d02 <HAL_NVIC_ClearPendingIRQ> + MODIFY_REG(RTC->WUTR, RTC_WUTR_WUT, Value); + 8000b72: 4b11 ldr r3, [pc, #68] @ (8000bb8 <RestartWakeupCounter+0xac>) + 8000b74: 695b ldr r3, [r3, #20] + 8000b76: 0c1b lsrs r3, r3, #16 + 8000b78: 041b lsls r3, r3, #16 + 8000b7a: 88fa ldrh r2, [r7, #6] + 8000b7c: 490e ldr r1, [pc, #56] @ (8000bb8 <RestartWakeupCounter+0xac>) + 8000b7e: 4313 orrs r3, r2 + 8000b80: 614b str r3, [r1, #20] + SSRValueOnLastSetup = ReadRtcSsrValue(); + 8000b82: f7ff fd8f bl 80006a4 <ReadRtcSsrValue> + 8000b86: 4603 mov r3, r0 + 8000b88: 4a07 ldr r2, [pc, #28] @ (8000ba8 <RestartWakeupCounter+0x9c>) + 8000b8a: 6013 str r3, [r2, #0] + __HAL_RTC_WAKEUPTIMER_ENABLE(&hrtc); /**< Enable the Wakeup Timer */ + 8000b8c: 4b08 ldr r3, [pc, #32] @ (8000bb0 <RestartWakeupCounter+0xa4>) + 8000b8e: 681b ldr r3, [r3, #0] + 8000b90: 689a ldr r2, [r3, #8] + 8000b92: 4b07 ldr r3, [pc, #28] @ (8000bb0 <RestartWakeupCounter+0xa4>) + 8000b94: 681b ldr r3, [r3, #0] + 8000b96: f442 6280 orr.w r2, r2, #1024 @ 0x400 + 8000b9a: 609a str r2, [r3, #8] + HW_TS_RTC_CountUpdated_AppNot(); + 8000b9c: f3af 8000 nop.w + return ; + 8000ba0: bf00 nop +} + 8000ba2: 3708 adds r7, #8 + 8000ba4: 46bd mov sp, r7 + 8000ba6: bd80 pop {r7, pc} + 8000ba8: 20000130 .word 0x20000130 + 8000bac: 20000135 .word 0x20000135 + 8000bb0: 200001cc .word 0x200001cc + 8000bb4: 58000800 .word 0x58000800 + 8000bb8: 40002800 .word 0x40002800 + +08000bbc <RescheduleTimerList>: + * 2) Setup the wakeuptimer + * @param None + * @retval None + */ +static void RescheduleTimerList(void) +{ + 8000bbc: b580 push {r7, lr} + 8000bbe: b084 sub sp, #16 + 8000bc0: af00 add r7, sp, #0 + + /** + * The wakeuptimer is disabled now to reduce the time to poll the WUTWF + * FLAG when the new value will have to be written + */ + if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET) + 8000bc2: 4b45 ldr r3, [pc, #276] @ (8000cd8 <RescheduleTimerList+0x11c>) + 8000bc4: 689b ldr r3, [r3, #8] + 8000bc6: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8000bca: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8000bce: d107 bne.n 8000be0 <RescheduleTimerList+0x24> + { + /** + * Wait for the flag to be back to 0 when the wakeup timer is enabled + */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == SET); + 8000bd0: bf00 nop + 8000bd2: 4b42 ldr r3, [pc, #264] @ (8000cdc <RescheduleTimerList+0x120>) + 8000bd4: 681b ldr r3, [r3, #0] + 8000bd6: 68db ldr r3, [r3, #12] + 8000bd8: f003 0304 and.w r3, r3, #4 + 8000bdc: 2b00 cmp r3, #0 + 8000bde: d1f8 bne.n 8000bd2 <RescheduleTimerList+0x16> + } + __HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); /**< Disable the Wakeup Timer */ + 8000be0: 4b3e ldr r3, [pc, #248] @ (8000cdc <RescheduleTimerList+0x120>) + 8000be2: 681b ldr r3, [r3, #0] + 8000be4: 689a ldr r2, [r3, #8] + 8000be6: 4b3d ldr r3, [pc, #244] @ (8000cdc <RescheduleTimerList+0x120>) + 8000be8: 681b ldr r3, [r3, #0] + 8000bea: f422 6280 bic.w r2, r2, #1024 @ 0x400 + 8000bee: 609a str r2, [r3, #8] + + localTimerID = CurrentRunningTimerID; + 8000bf0: 4b3b ldr r3, [pc, #236] @ (8000ce0 <RescheduleTimerList+0x124>) + 8000bf2: 781b ldrb r3, [r3, #0] + 8000bf4: 73fb strb r3, [r7, #15] + + /** + * Calculate what will be the value to write in the wakeuptimer + */ + timecountleft = aTimerContext[localTimerID].CountLeft; + 8000bf6: 7bfa ldrb r2, [r7, #15] + 8000bf8: 493a ldr r1, [pc, #232] @ (8000ce4 <RescheduleTimerList+0x128>) + 8000bfa: 4613 mov r3, r2 + 8000bfc: 005b lsls r3, r3, #1 + 8000bfe: 4413 add r3, r2 + 8000c00: 00db lsls r3, r3, #3 + 8000c02: 440b add r3, r1 + 8000c04: 3308 adds r3, #8 + 8000c06: 681b ldr r3, [r3, #0] + 8000c08: 60bb str r3, [r7, #8] + + /** + * Read how much has been counted + */ + time_elapsed = ReturnTimeElapsed(); + 8000c0a: f7ff ff3f bl 8000a8c <ReturnTimeElapsed> + 8000c0e: 4603 mov r3, r0 + 8000c10: 80fb strh r3, [r7, #6] + + if(timecountleft < time_elapsed ) + 8000c12: 88fb ldrh r3, [r7, #6] + 8000c14: 68ba ldr r2, [r7, #8] + 8000c16: 429a cmp r2, r3 + 8000c18: d205 bcs.n 8000c26 <RescheduleTimerList+0x6a> + { + /** + * There is no tick left to count + */ + wakeup_timer_value = 0; + 8000c1a: 2300 movs r3, #0 + 8000c1c: 81bb strh r3, [r7, #12] + WakeupTimerLimitation = WakeupTimerValue_LargeEnough; + 8000c1e: 4b32 ldr r3, [pc, #200] @ (8000ce8 <RescheduleTimerList+0x12c>) + 8000c20: 2201 movs r2, #1 + 8000c22: 701a strb r2, [r3, #0] + 8000c24: e04d b.n 8000cc2 <RescheduleTimerList+0x106> + } + else + { + if(timecountleft > (time_elapsed + MaxWakeupTimerSetup)) + 8000c26: 88fb ldrh r3, [r7, #6] + 8000c28: 4a30 ldr r2, [pc, #192] @ (8000cec <RescheduleTimerList+0x130>) + 8000c2a: 8812 ldrh r2, [r2, #0] + 8000c2c: b292 uxth r2, r2 + 8000c2e: 4413 add r3, r2 + 8000c30: 461a mov r2, r3 + 8000c32: 68bb ldr r3, [r7, #8] + 8000c34: 4293 cmp r3, r2 + 8000c36: d906 bls.n 8000c46 <RescheduleTimerList+0x8a> + { + /** + * The number of tick left is greater than the Wakeuptimer maximum value + */ + wakeup_timer_value = MaxWakeupTimerSetup; + 8000c38: 4b2c ldr r3, [pc, #176] @ (8000cec <RescheduleTimerList+0x130>) + 8000c3a: 881b ldrh r3, [r3, #0] + 8000c3c: 81bb strh r3, [r7, #12] + + WakeupTimerLimitation = WakeupTimerValue_Overpassed; + 8000c3e: 4b2a ldr r3, [pc, #168] @ (8000ce8 <RescheduleTimerList+0x12c>) + 8000c40: 2200 movs r2, #0 + 8000c42: 701a strb r2, [r3, #0] + 8000c44: e03d b.n 8000cc2 <RescheduleTimerList+0x106> + } + else + { + wakeup_timer_value = timecountleft - time_elapsed; + 8000c46: 68bb ldr r3, [r7, #8] + 8000c48: b29a uxth r2, r3 + 8000c4a: 88fb ldrh r3, [r7, #6] + 8000c4c: 1ad3 subs r3, r2, r3 + 8000c4e: 81bb strh r3, [r7, #12] + WakeupTimerLimitation = WakeupTimerValue_LargeEnough; + 8000c50: 4b25 ldr r3, [pc, #148] @ (8000ce8 <RescheduleTimerList+0x12c>) + 8000c52: 2201 movs r2, #1 + 8000c54: 701a strb r2, [r3, #0] + } + + /** + * update ticks left to be counted for each timer + */ + while(localTimerID != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) + 8000c56: e034 b.n 8000cc2 <RescheduleTimerList+0x106> + { + if (aTimerContext[localTimerID].CountLeft < time_elapsed) + 8000c58: 7bfa ldrb r2, [r7, #15] + 8000c5a: 4922 ldr r1, [pc, #136] @ (8000ce4 <RescheduleTimerList+0x128>) + 8000c5c: 4613 mov r3, r2 + 8000c5e: 005b lsls r3, r3, #1 + 8000c60: 4413 add r3, r2 + 8000c62: 00db lsls r3, r3, #3 + 8000c64: 440b add r3, r1 + 8000c66: 3308 adds r3, #8 + 8000c68: 681a ldr r2, [r3, #0] + 8000c6a: 88fb ldrh r3, [r7, #6] + 8000c6c: 429a cmp r2, r3 + 8000c6e: d20a bcs.n 8000c86 <RescheduleTimerList+0xca> + { + aTimerContext[localTimerID].CountLeft = 0; + 8000c70: 7bfa ldrb r2, [r7, #15] + 8000c72: 491c ldr r1, [pc, #112] @ (8000ce4 <RescheduleTimerList+0x128>) + 8000c74: 4613 mov r3, r2 + 8000c76: 005b lsls r3, r3, #1 + 8000c78: 4413 add r3, r2 + 8000c7a: 00db lsls r3, r3, #3 + 8000c7c: 440b add r3, r1 + 8000c7e: 3308 adds r3, #8 + 8000c80: 2200 movs r2, #0 + 8000c82: 601a str r2, [r3, #0] + 8000c84: e013 b.n 8000cae <RescheduleTimerList+0xf2> + } + else + { + aTimerContext[localTimerID].CountLeft -= time_elapsed; + 8000c86: 7bfa ldrb r2, [r7, #15] + 8000c88: 4916 ldr r1, [pc, #88] @ (8000ce4 <RescheduleTimerList+0x128>) + 8000c8a: 4613 mov r3, r2 + 8000c8c: 005b lsls r3, r3, #1 + 8000c8e: 4413 add r3, r2 + 8000c90: 00db lsls r3, r3, #3 + 8000c92: 440b add r3, r1 + 8000c94: 3308 adds r3, #8 + 8000c96: 6819 ldr r1, [r3, #0] + 8000c98: 88fb ldrh r3, [r7, #6] + 8000c9a: 7bfa ldrb r2, [r7, #15] + 8000c9c: 1ac9 subs r1, r1, r3 + 8000c9e: 4811 ldr r0, [pc, #68] @ (8000ce4 <RescheduleTimerList+0x128>) + 8000ca0: 4613 mov r3, r2 + 8000ca2: 005b lsls r3, r3, #1 + 8000ca4: 4413 add r3, r2 + 8000ca6: 00db lsls r3, r3, #3 + 8000ca8: 4403 add r3, r0 + 8000caa: 3308 adds r3, #8 + 8000cac: 6019 str r1, [r3, #0] + } + localTimerID = aTimerContext[localTimerID].NextID; + 8000cae: 7bfa ldrb r2, [r7, #15] + 8000cb0: 490c ldr r1, [pc, #48] @ (8000ce4 <RescheduleTimerList+0x128>) + 8000cb2: 4613 mov r3, r2 + 8000cb4: 005b lsls r3, r3, #1 + 8000cb6: 4413 add r3, r2 + 8000cb8: 00db lsls r3, r3, #3 + 8000cba: 440b add r3, r1 + 8000cbc: 3315 adds r3, #21 + 8000cbe: 781b ldrb r3, [r3, #0] + 8000cc0: 73fb strb r3, [r7, #15] + while(localTimerID != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) + 8000cc2: 7bfb ldrb r3, [r7, #15] + 8000cc4: 2b06 cmp r3, #6 + 8000cc6: d1c7 bne.n 8000c58 <RescheduleTimerList+0x9c> + } + + /** + * Write next count + */ + RestartWakeupCounter(wakeup_timer_value); + 8000cc8: 89bb ldrh r3, [r7, #12] + 8000cca: 4618 mov r0, r3 + 8000ccc: f7ff ff1e bl 8000b0c <RestartWakeupCounter> + + return ; + 8000cd0: bf00 nop +} + 8000cd2: 3710 adds r7, #16 + 8000cd4: 46bd mov sp, r7 + 8000cd6: bd80 pop {r7, pc} + 8000cd8: 40002800 .word 0x40002800 + 8000cdc: 200001cc .word 0x200001cc + 8000ce0: 2000012c .word 0x2000012c + 8000ce4: 2000009c .word 0x2000009c + 8000ce8: 20000134 .word 0x20000134 + 8000cec: 2000013a .word 0x2000013a + +08000cf0 <HW_TS_Init>: + + return; +} + +void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *phrtc) +{ + 8000cf0: b580 push {r7, lr} + 8000cf2: b088 sub sp, #32 + 8000cf4: af00 add r7, sp, #0 + 8000cf6: 4603 mov r3, r0 + 8000cf8: 6039 str r1, [r7, #0] + 8000cfa: 71fb strb r3, [r7, #7] + uint8_t loop; + uint32_t localmaxwakeuptimersetup; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc ); + 8000cfc: 4b5e ldr r3, [pc, #376] @ (8000e78 <HW_TS_Init+0x188>) + 8000cfe: 681b ldr r3, [r3, #0] + 8000d00: 22ca movs r2, #202 @ 0xca + 8000d02: 625a str r2, [r3, #36] @ 0x24 + 8000d04: 4b5c ldr r3, [pc, #368] @ (8000e78 <HW_TS_Init+0x188>) + 8000d06: 681b ldr r3, [r3, #0] + 8000d08: 2253 movs r2, #83 @ 0x53 + 8000d0a: 625a str r2, [r3, #36] @ 0x24 + + SET_BIT(RTC->CR, RTC_CR_BYPSHAD); + 8000d0c: 4b5b ldr r3, [pc, #364] @ (8000e7c <HW_TS_Init+0x18c>) + 8000d0e: 689b ldr r3, [r3, #8] + 8000d10: 4a5a ldr r2, [pc, #360] @ (8000e7c <HW_TS_Init+0x18c>) + 8000d12: f043 0320 orr.w r3, r3, #32 + 8000d16: 6093 str r3, [r2, #8] + + /** + * Readout the user config + */ + WakeupTimerDivider = (4 - ((uint32_t)(READ_BIT(RTC->CR, RTC_CR_WUCKSEL)))); + 8000d18: 4b58 ldr r3, [pc, #352] @ (8000e7c <HW_TS_Init+0x18c>) + 8000d1a: 689b ldr r3, [r3, #8] + 8000d1c: b2db uxtb r3, r3 + 8000d1e: f003 0307 and.w r3, r3, #7 + 8000d22: b2db uxtb r3, r3 + 8000d24: f1c3 0304 rsb r3, r3, #4 + 8000d28: b2da uxtb r2, r3 + 8000d2a: 4b55 ldr r3, [pc, #340] @ (8000e80 <HW_TS_Init+0x190>) + 8000d2c: 701a strb r2, [r3, #0] + + AsynchPrescalerUserConfig = (uint8_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_A) >> (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)) + 1; + 8000d2e: 4b53 ldr r3, [pc, #332] @ (8000e7c <HW_TS_Init+0x18c>) + 8000d30: 691b ldr r3, [r3, #16] + 8000d32: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 + 8000d36: f44f 02fe mov.w r2, #8323072 @ 0x7f0000 + 8000d3a: 613a str r2, [r7, #16] + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8000d3c: 693a ldr r2, [r7, #16] + 8000d3e: fa92 f2a2 rbit r2, r2 + 8000d42: 60fa str r2, [r7, #12] + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; + 8000d44: 68fa ldr r2, [r7, #12] + 8000d46: 617a str r2, [r7, #20] + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + 8000d48: 697a ldr r2, [r7, #20] + 8000d4a: 2a00 cmp r2, #0 + 8000d4c: d101 bne.n 8000d52 <HW_TS_Init+0x62> + { + return 32U; + 8000d4e: 2220 movs r2, #32 + 8000d50: e003 b.n 8000d5a <HW_TS_Init+0x6a> + } + return __builtin_clz(value); + 8000d52: 697a ldr r2, [r7, #20] + 8000d54: fab2 f282 clz r2, r2 + 8000d58: b2d2 uxtb r2, r2 + 8000d5a: 40d3 lsrs r3, r2 + 8000d5c: b2db uxtb r3, r3 + 8000d5e: 3301 adds r3, #1 + 8000d60: b2da uxtb r2, r3 + 8000d62: 4b48 ldr r3, [pc, #288] @ (8000e84 <HW_TS_Init+0x194>) + 8000d64: 701a strb r2, [r3, #0] + + SynchPrescalerUserConfig = (uint16_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_S)) + 1; + 8000d66: 4b45 ldr r3, [pc, #276] @ (8000e7c <HW_TS_Init+0x18c>) + 8000d68: 691b ldr r3, [r3, #16] + 8000d6a: b29b uxth r3, r3 + 8000d6c: f3c3 030e ubfx r3, r3, #0, #15 + 8000d70: b29b uxth r3, r3 + 8000d72: 3301 adds r3, #1 + 8000d74: b29a uxth r2, r3 + 8000d76: 4b44 ldr r3, [pc, #272] @ (8000e88 <HW_TS_Init+0x198>) + 8000d78: 801a strh r2, [r3, #0] + + /** + * Margin is taken to avoid wrong calculation when the wrap around is there and some + * application interrupts may have delayed the reading + */ + localmaxwakeuptimersetup = ((((SynchPrescalerUserConfig - 1)*AsynchPrescalerUserConfig) - CFG_HW_TS_RTC_HANDLER_MAX_DELAY) >> WakeupTimerDivider); + 8000d7a: 4b43 ldr r3, [pc, #268] @ (8000e88 <HW_TS_Init+0x198>) + 8000d7c: 881b ldrh r3, [r3, #0] + 8000d7e: 3b01 subs r3, #1 + 8000d80: 4a40 ldr r2, [pc, #256] @ (8000e84 <HW_TS_Init+0x194>) + 8000d82: 7812 ldrb r2, [r2, #0] + 8000d84: fb02 f303 mul.w r3, r2, r3 + 8000d88: f5a3 73a0 sub.w r3, r3, #320 @ 0x140 + 8000d8c: 4a3c ldr r2, [pc, #240] @ (8000e80 <HW_TS_Init+0x190>) + 8000d8e: 7812 ldrb r2, [r2, #0] + 8000d90: 40d3 lsrs r3, r2 + 8000d92: 61bb str r3, [r7, #24] + + if(localmaxwakeuptimersetup >= 0xFFFF) + 8000d94: 69bb ldr r3, [r7, #24] + 8000d96: f64f 72fe movw r2, #65534 @ 0xfffe + 8000d9a: 4293 cmp r3, r2 + 8000d9c: d904 bls.n 8000da8 <HW_TS_Init+0xb8> + { + MaxWakeupTimerSetup = 0xFFFF; + 8000d9e: 4b3b ldr r3, [pc, #236] @ (8000e8c <HW_TS_Init+0x19c>) + 8000da0: f64f 72ff movw r2, #65535 @ 0xffff + 8000da4: 801a strh r2, [r3, #0] + 8000da6: e003 b.n 8000db0 <HW_TS_Init+0xc0> + } + else + { + MaxWakeupTimerSetup = (uint16_t)localmaxwakeuptimersetup; + 8000da8: 69bb ldr r3, [r7, #24] + 8000daa: b29a uxth r2, r3 + 8000dac: 4b37 ldr r3, [pc, #220] @ (8000e8c <HW_TS_Init+0x19c>) + 8000dae: 801a strh r2, [r3, #0] + } + + /** + * Configure EXTI module + */ + LL_EXTI_EnableRisingTrig_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); + 8000db0: f44f 2000 mov.w r0, #524288 @ 0x80000 + 8000db4: f7ff fc64 bl 8000680 <LL_EXTI_EnableRisingTrig_0_31> + LL_EXTI_EnableIT_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); + 8000db8: f44f 2000 mov.w r0, #524288 @ 0x80000 + 8000dbc: f7ff fc4c bl 8000658 <LL_EXTI_EnableIT_0_31> + + if(TimerInitMode == hw_ts_InitMode_Full) + 8000dc0: 79fb ldrb r3, [r7, #7] + 8000dc2: 2b00 cmp r3, #0 + 8000dc4: d13d bne.n 8000e42 <HW_TS_Init+0x152> + { + WakeupTimerLimitation = WakeupTimerValue_LargeEnough; + 8000dc6: 4b32 ldr r3, [pc, #200] @ (8000e90 <HW_TS_Init+0x1a0>) + 8000dc8: 2201 movs r2, #1 + 8000dca: 701a strb r2, [r3, #0] + SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE; + 8000dcc: 4b31 ldr r3, [pc, #196] @ (8000e94 <HW_TS_Init+0x1a4>) + 8000dce: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8000dd2: 601a str r2, [r3, #0] + + /** + * Initialize the timer server + */ + for(loop = 0; loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; loop++) + 8000dd4: 2300 movs r3, #0 + 8000dd6: 77fb strb r3, [r7, #31] + 8000dd8: e00c b.n 8000df4 <HW_TS_Init+0x104> + { + aTimerContext[loop].TimerIDStatus = TimerID_Free; + 8000dda: 7ffa ldrb r2, [r7, #31] + 8000ddc: 492e ldr r1, [pc, #184] @ (8000e98 <HW_TS_Init+0x1a8>) + 8000dde: 4613 mov r3, r2 + 8000de0: 005b lsls r3, r3, #1 + 8000de2: 4413 add r3, r2 + 8000de4: 00db lsls r3, r3, #3 + 8000de6: 440b add r3, r1 + 8000de8: 330c adds r3, #12 + 8000dea: 2200 movs r2, #0 + 8000dec: 701a strb r2, [r3, #0] + for(loop = 0; loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; loop++) + 8000dee: 7ffb ldrb r3, [r7, #31] + 8000df0: 3301 adds r3, #1 + 8000df2: 77fb strb r3, [r7, #31] + 8000df4: 7ffb ldrb r3, [r7, #31] + 8000df6: 2b05 cmp r3, #5 + 8000df8: d9ef bls.n 8000dda <HW_TS_Init+0xea> + } + + CurrentRunningTimerID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; /**< Set ID to non valid value */ + 8000dfa: 4b28 ldr r3, [pc, #160] @ (8000e9c <HW_TS_Init+0x1ac>) + 8000dfc: 2206 movs r2, #6 + 8000dfe: 701a strb r2, [r3, #0] + + __HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); /**< Disable the Wakeup Timer */ + 8000e00: 4b1d ldr r3, [pc, #116] @ (8000e78 <HW_TS_Init+0x188>) + 8000e02: 681b ldr r3, [r3, #0] + 8000e04: 689a ldr r2, [r3, #8] + 8000e06: 4b1c ldr r3, [pc, #112] @ (8000e78 <HW_TS_Init+0x188>) + 8000e08: 681b ldr r3, [r3, #0] + 8000e0a: f422 6280 bic.w r2, r2, #1024 @ 0x400 + 8000e0e: 609a str r2, [r3, #8] + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */ + 8000e10: 4b19 ldr r3, [pc, #100] @ (8000e78 <HW_TS_Init+0x188>) + 8000e12: 681b ldr r3, [r3, #0] + 8000e14: 68db ldr r3, [r3, #12] + 8000e16: b2da uxtb r2, r3 + 8000e18: 4b17 ldr r3, [pc, #92] @ (8000e78 <HW_TS_Init+0x188>) + 8000e1a: 681b ldr r3, [r3, #0] + 8000e1c: f462 6290 orn r2, r2, #1152 @ 0x480 + 8000e20: 60da str r2, [r3, #12] + __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */ + 8000e22: 4b1f ldr r3, [pc, #124] @ (8000ea0 <HW_TS_Init+0x1b0>) + 8000e24: f44f 2200 mov.w r2, #524288 @ 0x80000 + 8000e28: 60da str r2, [r3, #12] + HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Clear pending bit in NVIC */ + 8000e2a: 2003 movs r0, #3 + 8000e2c: f000 ff69 bl 8001d02 <HAL_NVIC_ClearPendingIRQ> + __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hrtc, RTC_IT_WUT); /**< Enable interrupt in RTC module */ + 8000e30: 4b11 ldr r3, [pc, #68] @ (8000e78 <HW_TS_Init+0x188>) + 8000e32: 681b ldr r3, [r3, #0] + 8000e34: 689a ldr r2, [r3, #8] + 8000e36: 4b10 ldr r3, [pc, #64] @ (8000e78 <HW_TS_Init+0x188>) + 8000e38: 681b ldr r3, [r3, #0] + 8000e3a: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 8000e3e: 609a str r2, [r3, #8] + 8000e40: e009 b.n 8000e56 <HW_TS_Init+0x166> + } + else + { + if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTF) != RESET) + 8000e42: 4b0d ldr r3, [pc, #52] @ (8000e78 <HW_TS_Init+0x188>) + 8000e44: 681b ldr r3, [r3, #0] + 8000e46: 68db ldr r3, [r3, #12] + 8000e48: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8000e4c: 2b00 cmp r3, #0 + 8000e4e: d002 beq.n 8000e56 <HW_TS_Init+0x166> + { + /** + * Simulate that the Timer expired + */ + HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); + 8000e50: 2003 movs r0, #3 + 8000e52: f000 ff48 bl 8001ce6 <HAL_NVIC_SetPendingIRQ> + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc ); + 8000e56: 4b08 ldr r3, [pc, #32] @ (8000e78 <HW_TS_Init+0x188>) + 8000e58: 681b ldr r3, [r3, #0] + 8000e5a: 22ff movs r2, #255 @ 0xff + 8000e5c: 625a str r2, [r3, #36] @ 0x24 + + HAL_NVIC_SetPriority(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO); /**< Set NVIC priority */ + 8000e5e: 2200 movs r2, #0 + 8000e60: 2103 movs r1, #3 + 8000e62: 2003 movs r0, #3 + 8000e64: f000 fefd bl 8001c62 <HAL_NVIC_SetPriority> + HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Enable NVIC */ + 8000e68: 2003 movs r0, #3 + 8000e6a: f000 ff14 bl 8001c96 <HAL_NVIC_EnableIRQ> + + return; + 8000e6e: bf00 nop +} + 8000e70: 3720 adds r7, #32 + 8000e72: 46bd mov sp, r7 + 8000e74: bd80 pop {r7, pc} + 8000e76: bf00 nop + 8000e78: 200001cc .word 0x200001cc + 8000e7c: 40002800 .word 0x40002800 + 8000e80: 20000135 .word 0x20000135 + 8000e84: 20000136 .word 0x20000136 + 8000e88: 20000138 .word 0x20000138 + 8000e8c: 2000013a .word 0x2000013a + 8000e90: 20000134 .word 0x20000134 + 8000e94: 20000130 .word 0x20000130 + 8000e98: 2000009c .word 0x2000009c + 8000e9c: 2000012c .word 0x2000012c + 8000ea0: 58000800 .word 0x58000800 + +08000ea4 <HW_TS_Create>: + +HW_TS_ReturnStatus_t HW_TS_Create(uint32_t TimerProcessID, uint8_t *pTimerId, HW_TS_Mode_t TimerMode, HW_TS_pTimerCb_t pftimeout_handler) +{ + 8000ea4: b480 push {r7} + 8000ea6: b08b sub sp, #44 @ 0x2c + 8000ea8: af00 add r7, sp, #0 + 8000eaa: 60f8 str r0, [r7, #12] + 8000eac: 60b9 str r1, [r7, #8] + 8000eae: 603b str r3, [r7, #0] + 8000eb0: 4613 mov r3, r2 + 8000eb2: 71fb strb r3, [r7, #7] + HW_TS_ReturnStatus_t localreturnstatus; + uint8_t loop = 0; + 8000eb4: 2300 movs r3, #0 + 8000eb6: f887 3026 strb.w r3, [r7, #38] @ 0x26 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8000eba: f3ef 8310 mrs r3, PRIMASK + 8000ebe: 61fb str r3, [r7, #28] + return(result); + 8000ec0: 69fb ldr r3, [r7, #28] +#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) + uint32_t primask_bit; +#endif + +#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) + primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ + 8000ec2: 623b str r3, [r7, #32] + __ASM volatile ("cpsid i" : : : "memory"); + 8000ec4: b672 cpsid i +} + 8000ec6: bf00 nop + __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ +#endif + + while((loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[loop].TimerIDStatus != TimerID_Free)) + 8000ec8: e004 b.n 8000ed4 <HW_TS_Create+0x30> + { + loop++; + 8000eca: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 + 8000ece: 3301 adds r3, #1 + 8000ed0: f887 3026 strb.w r3, [r7, #38] @ 0x26 + while((loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[loop].TimerIDStatus != TimerID_Free)) + 8000ed4: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 + 8000ed8: 2b05 cmp r3, #5 + 8000eda: d80c bhi.n 8000ef6 <HW_TS_Create+0x52> + 8000edc: f897 2026 ldrb.w r2, [r7, #38] @ 0x26 + 8000ee0: 492c ldr r1, [pc, #176] @ (8000f94 <HW_TS_Create+0xf0>) + 8000ee2: 4613 mov r3, r2 + 8000ee4: 005b lsls r3, r3, #1 + 8000ee6: 4413 add r3, r2 + 8000ee8: 00db lsls r3, r3, #3 + 8000eea: 440b add r3, r1 + 8000eec: 330c adds r3, #12 + 8000eee: 781b ldrb r3, [r3, #0] + 8000ef0: b2db uxtb r3, r3 + 8000ef2: 2b00 cmp r3, #0 + 8000ef4: d1e9 bne.n 8000eca <HW_TS_Create+0x26> + } + + if(loop != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) + 8000ef6: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 + 8000efa: 2b06 cmp r3, #6 + 8000efc: d038 beq.n 8000f70 <HW_TS_Create+0xcc> + { + aTimerContext[loop].TimerIDStatus = TimerID_Created; + 8000efe: f897 2026 ldrb.w r2, [r7, #38] @ 0x26 + 8000f02: 4924 ldr r1, [pc, #144] @ (8000f94 <HW_TS_Create+0xf0>) + 8000f04: 4613 mov r3, r2 + 8000f06: 005b lsls r3, r3, #1 + 8000f08: 4413 add r3, r2 + 8000f0a: 00db lsls r3, r3, #3 + 8000f0c: 440b add r3, r1 + 8000f0e: 330c adds r3, #12 + 8000f10: 2201 movs r2, #1 + 8000f12: 701a strb r2, [r3, #0] + 8000f14: 6a3b ldr r3, [r7, #32] + 8000f16: 61bb str r3, [r7, #24] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8000f18: 69bb ldr r3, [r7, #24] + 8000f1a: f383 8810 msr PRIMASK, r3 +} + 8000f1e: bf00 nop + +#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) + __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ +#endif + + aTimerContext[loop].TimerProcessID = TimerProcessID; + 8000f20: f897 2026 ldrb.w r2, [r7, #38] @ 0x26 + 8000f24: 491b ldr r1, [pc, #108] @ (8000f94 <HW_TS_Create+0xf0>) + 8000f26: 4613 mov r3, r2 + 8000f28: 005b lsls r3, r3, #1 + 8000f2a: 4413 add r3, r2 + 8000f2c: 00db lsls r3, r3, #3 + 8000f2e: 440b add r3, r1 + 8000f30: 3310 adds r3, #16 + 8000f32: 68fa ldr r2, [r7, #12] + 8000f34: 601a str r2, [r3, #0] + aTimerContext[loop].TimerMode = TimerMode; + 8000f36: f897 2026 ldrb.w r2, [r7, #38] @ 0x26 + 8000f3a: 4916 ldr r1, [pc, #88] @ (8000f94 <HW_TS_Create+0xf0>) + 8000f3c: 4613 mov r3, r2 + 8000f3e: 005b lsls r3, r3, #1 + 8000f40: 4413 add r3, r2 + 8000f42: 00db lsls r3, r3, #3 + 8000f44: 440b add r3, r1 + 8000f46: 330d adds r3, #13 + 8000f48: 79fa ldrb r2, [r7, #7] + 8000f4a: 701a strb r2, [r3, #0] + aTimerContext[loop].pTimerCallBack = pftimeout_handler; + 8000f4c: f897 2026 ldrb.w r2, [r7, #38] @ 0x26 + 8000f50: 4910 ldr r1, [pc, #64] @ (8000f94 <HW_TS_Create+0xf0>) + 8000f52: 4613 mov r3, r2 + 8000f54: 005b lsls r3, r3, #1 + 8000f56: 4413 add r3, r2 + 8000f58: 00db lsls r3, r3, #3 + 8000f5a: 440b add r3, r1 + 8000f5c: 683a ldr r2, [r7, #0] + 8000f5e: 601a str r2, [r3, #0] + *pTimerId = loop; + 8000f60: 68bb ldr r3, [r7, #8] + 8000f62: f897 2026 ldrb.w r2, [r7, #38] @ 0x26 + 8000f66: 701a strb r2, [r3, #0] + + localreturnstatus = hw_ts_Successful; + 8000f68: 2300 movs r3, #0 + 8000f6a: f887 3027 strb.w r3, [r7, #39] @ 0x27 + 8000f6e: e008 b.n 8000f82 <HW_TS_Create+0xde> + 8000f70: 6a3b ldr r3, [r7, #32] + 8000f72: 617b str r3, [r7, #20] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8000f74: 697b ldr r3, [r7, #20] + 8000f76: f383 8810 msr PRIMASK, r3 +} + 8000f7a: bf00 nop + { +#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) + __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ +#endif + + localreturnstatus = hw_ts_Failed; + 8000f7c: 2301 movs r3, #1 + 8000f7e: f887 3027 strb.w r3, [r7, #39] @ 0x27 + } + + return(localreturnstatus); + 8000f82: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 +} + 8000f86: 4618 mov r0, r3 + 8000f88: 372c adds r7, #44 @ 0x2c + 8000f8a: 46bd mov sp, r7 + 8000f8c: f85d 7b04 ldr.w r7, [sp], #4 + 8000f90: 4770 bx lr + 8000f92: bf00 nop + 8000f94: 2000009c .word 0x2000009c + +08000f98 <HW_TS_Stop>: + + return; +} + +void HW_TS_Stop(uint8_t timer_id) +{ + 8000f98: b580 push {r7, lr} + 8000f9a: b086 sub sp, #24 + 8000f9c: af00 add r7, sp, #0 + 8000f9e: 4603 mov r3, r0 + 8000fa0: 71fb strb r3, [r7, #7] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8000fa2: f3ef 8310 mrs r3, PRIMASK + 8000fa6: 60fb str r3, [r7, #12] + return(result); + 8000fa8: 68fb ldr r3, [r7, #12] +#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) + uint32_t primask_bit; +#endif + +#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) + primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ + 8000faa: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 8000fac: b672 cpsid i +} + 8000fae: bf00 nop + __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ +#endif + + HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Disable NVIC */ + 8000fb0: 2003 movs r0, #3 + 8000fb2: f000 fe7e bl 8001cb2 <HAL_NVIC_DisableIRQ> + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc ); + 8000fb6: 4b34 ldr r3, [pc, #208] @ (8001088 <HW_TS_Stop+0xf0>) + 8000fb8: 681b ldr r3, [r3, #0] + 8000fba: 22ca movs r2, #202 @ 0xca + 8000fbc: 625a str r2, [r3, #36] @ 0x24 + 8000fbe: 4b32 ldr r3, [pc, #200] @ (8001088 <HW_TS_Stop+0xf0>) + 8000fc0: 681b ldr r3, [r3, #0] + 8000fc2: 2253 movs r2, #83 @ 0x53 + 8000fc4: 625a str r2, [r3, #36] @ 0x24 + + if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running) + 8000fc6: 79fa ldrb r2, [r7, #7] + 8000fc8: 4930 ldr r1, [pc, #192] @ (800108c <HW_TS_Stop+0xf4>) + 8000fca: 4613 mov r3, r2 + 8000fcc: 005b lsls r3, r3, #1 + 8000fce: 4413 add r3, r2 + 8000fd0: 00db lsls r3, r3, #3 + 8000fd2: 440b add r3, r1 + 8000fd4: 330c adds r3, #12 + 8000fd6: 781b ldrb r3, [r3, #0] + 8000fd8: b2db uxtb r3, r3 + 8000fda: 2b02 cmp r3, #2 + 8000fdc: d142 bne.n 8001064 <HW_TS_Stop+0xcc> + { + UnlinkTimer(timer_id, SSR_Read_Requested); + 8000fde: 79fb ldrb r3, [r7, #7] + 8000fe0: 2100 movs r1, #0 + 8000fe2: 4618 mov r0, r3 + 8000fe4: f7ff fcce bl 8000984 <UnlinkTimer> + localcurrentrunningtimerid = CurrentRunningTimerID; + 8000fe8: 4b29 ldr r3, [pc, #164] @ (8001090 <HW_TS_Stop+0xf8>) + 8000fea: 781b ldrb r3, [r3, #0] + 8000fec: 74fb strb r3, [r7, #19] + + if(localcurrentrunningtimerid == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) + 8000fee: 7cfb ldrb r3, [r7, #19] + 8000ff0: 2b06 cmp r3, #6 + 8000ff2: d12f bne.n 8001054 <HW_TS_Stop+0xbc> + */ + + /** + * Disable the timer + */ + if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET) + 8000ff4: 4b27 ldr r3, [pc, #156] @ (8001094 <HW_TS_Stop+0xfc>) + 8000ff6: 689b ldr r3, [r3, #8] + 8000ff8: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8000ffc: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8001000: d107 bne.n 8001012 <HW_TS_Stop+0x7a> + { + /** + * Wait for the flag to be back to 0 when the wakeup timer is enabled + */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == SET); + 8001002: bf00 nop + 8001004: 4b20 ldr r3, [pc, #128] @ (8001088 <HW_TS_Stop+0xf0>) + 8001006: 681b ldr r3, [r3, #0] + 8001008: 68db ldr r3, [r3, #12] + 800100a: f003 0304 and.w r3, r3, #4 + 800100e: 2b00 cmp r3, #0 + 8001010: d1f8 bne.n 8001004 <HW_TS_Stop+0x6c> + } + __HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); /**< Disable the Wakeup Timer */ + 8001012: 4b1d ldr r3, [pc, #116] @ (8001088 <HW_TS_Stop+0xf0>) + 8001014: 681b ldr r3, [r3, #0] + 8001016: 689a ldr r2, [r3, #8] + 8001018: 4b1b ldr r3, [pc, #108] @ (8001088 <HW_TS_Stop+0xf0>) + 800101a: 681b ldr r3, [r3, #0] + 800101c: f422 6280 bic.w r2, r2, #1024 @ 0x400 + 8001020: 609a str r2, [r3, #8] + + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == RESET); + 8001022: bf00 nop + 8001024: 4b18 ldr r3, [pc, #96] @ (8001088 <HW_TS_Stop+0xf0>) + 8001026: 681b ldr r3, [r3, #0] + 8001028: 68db ldr r3, [r3, #12] + 800102a: f003 0304 and.w r3, r3, #4 + 800102e: 2b00 cmp r3, #0 + 8001030: d0f8 beq.n 8001024 <HW_TS_Stop+0x8c> + * It takes 2 RTCCLK between the time the WUTE bit is disabled and the + * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable + * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between + * due to the autoreload feature + */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */ + 8001032: 4b15 ldr r3, [pc, #84] @ (8001088 <HW_TS_Stop+0xf0>) + 8001034: 681b ldr r3, [r3, #0] + 8001036: 68db ldr r3, [r3, #12] + 8001038: b2da uxtb r2, r3 + 800103a: 4b13 ldr r3, [pc, #76] @ (8001088 <HW_TS_Stop+0xf0>) + 800103c: 681b ldr r3, [r3, #0] + 800103e: f462 6290 orn r2, r2, #1152 @ 0x480 + 8001042: 60da str r2, [r3, #12] + __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */ + 8001044: 4b14 ldr r3, [pc, #80] @ (8001098 <HW_TS_Stop+0x100>) + 8001046: f44f 2200 mov.w r2, #524288 @ 0x80000 + 800104a: 60da str r2, [r3, #12] + HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Clear pending bit in NVIC */ + 800104c: 2003 movs r0, #3 + 800104e: f000 fe58 bl 8001d02 <HAL_NVIC_ClearPendingIRQ> + 8001052: e007 b.n 8001064 <HW_TS_Stop+0xcc> + } + else if(PreviousRunningTimerID != localcurrentrunningtimerid) + 8001054: 4b11 ldr r3, [pc, #68] @ (800109c <HW_TS_Stop+0x104>) + 8001056: 781b ldrb r3, [r3, #0] + 8001058: b2db uxtb r3, r3 + 800105a: 7cfa ldrb r2, [r7, #19] + 800105c: 429a cmp r2, r3 + 800105e: d001 beq.n 8001064 <HW_TS_Stop+0xcc> + { + RescheduleTimerList(); + 8001060: f7ff fdac bl 8000bbc <RescheduleTimerList> + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc ); + 8001064: 4b08 ldr r3, [pc, #32] @ (8001088 <HW_TS_Stop+0xf0>) + 8001066: 681b ldr r3, [r3, #0] + 8001068: 22ff movs r2, #255 @ 0xff + 800106a: 625a str r2, [r3, #36] @ 0x24 + + HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Enable NVIC */ + 800106c: 2003 movs r0, #3 + 800106e: f000 fe12 bl 8001c96 <HAL_NVIC_EnableIRQ> + 8001072: 697b ldr r3, [r7, #20] + 8001074: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8001076: 68bb ldr r3, [r7, #8] + 8001078: f383 8810 msr PRIMASK, r3 +} + 800107c: bf00 nop + +#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) + __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ +#endif + + return; + 800107e: bf00 nop +} + 8001080: 3718 adds r7, #24 + 8001082: 46bd mov sp, r7 + 8001084: bd80 pop {r7, pc} + 8001086: bf00 nop + 8001088: 200001cc .word 0x200001cc + 800108c: 2000009c .word 0x2000009c + 8001090: 2000012c .word 0x2000012c + 8001094: 40002800 .word 0x40002800 + 8001098: 58000800 .word 0x58000800 + 800109c: 2000012d .word 0x2000012d + +080010a0 <HW_TS_Start>: + +void HW_TS_Start(uint8_t timer_id, uint32_t timeout_ticks) +{ + 80010a0: b580 push {r7, lr} + 80010a2: b086 sub sp, #24 + 80010a4: af00 add r7, sp, #0 + 80010a6: 4603 mov r3, r0 + 80010a8: 6039 str r1, [r7, #0] + 80010aa: 71fb strb r3, [r7, #7] + +#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) + uint32_t primask_bit; +#endif + + if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running) + 80010ac: 79fa ldrb r2, [r7, #7] + 80010ae: 493b ldr r1, [pc, #236] @ (800119c <HW_TS_Start+0xfc>) + 80010b0: 4613 mov r3, r2 + 80010b2: 005b lsls r3, r3, #1 + 80010b4: 4413 add r3, r2 + 80010b6: 00db lsls r3, r3, #3 + 80010b8: 440b add r3, r1 + 80010ba: 330c adds r3, #12 + 80010bc: 781b ldrb r3, [r3, #0] + 80010be: b2db uxtb r3, r3 + 80010c0: 2b02 cmp r3, #2 + 80010c2: d103 bne.n 80010cc <HW_TS_Start+0x2c> + { + HW_TS_Stop( timer_id ); + 80010c4: 79fb ldrb r3, [r7, #7] + 80010c6: 4618 mov r0, r3 + 80010c8: f7ff ff66 bl 8000f98 <HW_TS_Stop> + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 80010cc: f3ef 8310 mrs r3, PRIMASK + 80010d0: 60fb str r3, [r7, #12] + return(result); + 80010d2: 68fb ldr r3, [r7, #12] + } + +#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) + primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ + 80010d4: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 80010d6: b672 cpsid i +} + 80010d8: bf00 nop + __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ +#endif + + HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Disable NVIC */ + 80010da: 2003 movs r0, #3 + 80010dc: f000 fde9 bl 8001cb2 <HAL_NVIC_DisableIRQ> + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc ); + 80010e0: 4b2f ldr r3, [pc, #188] @ (80011a0 <HW_TS_Start+0x100>) + 80010e2: 681b ldr r3, [r3, #0] + 80010e4: 22ca movs r2, #202 @ 0xca + 80010e6: 625a str r2, [r3, #36] @ 0x24 + 80010e8: 4b2d ldr r3, [pc, #180] @ (80011a0 <HW_TS_Start+0x100>) + 80010ea: 681b ldr r3, [r3, #0] + 80010ec: 2253 movs r2, #83 @ 0x53 + 80010ee: 625a str r2, [r3, #36] @ 0x24 + + aTimerContext[timer_id].TimerIDStatus = TimerID_Running; + 80010f0: 79fa ldrb r2, [r7, #7] + 80010f2: 492a ldr r1, [pc, #168] @ (800119c <HW_TS_Start+0xfc>) + 80010f4: 4613 mov r3, r2 + 80010f6: 005b lsls r3, r3, #1 + 80010f8: 4413 add r3, r2 + 80010fa: 00db lsls r3, r3, #3 + 80010fc: 440b add r3, r1 + 80010fe: 330c adds r3, #12 + 8001100: 2202 movs r2, #2 + 8001102: 701a strb r2, [r3, #0] + + aTimerContext[timer_id].CountLeft = timeout_ticks; + 8001104: 79fa ldrb r2, [r7, #7] + 8001106: 4925 ldr r1, [pc, #148] @ (800119c <HW_TS_Start+0xfc>) + 8001108: 4613 mov r3, r2 + 800110a: 005b lsls r3, r3, #1 + 800110c: 4413 add r3, r2 + 800110e: 00db lsls r3, r3, #3 + 8001110: 440b add r3, r1 + 8001112: 3308 adds r3, #8 + 8001114: 683a ldr r2, [r7, #0] + 8001116: 601a str r2, [r3, #0] + aTimerContext[timer_id].CounterInit = timeout_ticks; + 8001118: 79fa ldrb r2, [r7, #7] + 800111a: 4920 ldr r1, [pc, #128] @ (800119c <HW_TS_Start+0xfc>) + 800111c: 4613 mov r3, r2 + 800111e: 005b lsls r3, r3, #1 + 8001120: 4413 add r3, r2 + 8001122: 00db lsls r3, r3, #3 + 8001124: 440b add r3, r1 + 8001126: 3304 adds r3, #4 + 8001128: 683a ldr r2, [r7, #0] + 800112a: 601a str r2, [r3, #0] + + time_elapsed = linkTimer(timer_id); + 800112c: 79fb ldrb r3, [r7, #7] + 800112e: 4618 mov r0, r3 + 8001130: f7ff fb7e bl 8000830 <linkTimer> + 8001134: 4603 mov r3, r0 + 8001136: 827b strh r3, [r7, #18] + + localcurrentrunningtimerid = CurrentRunningTimerID; + 8001138: 4b1a ldr r3, [pc, #104] @ (80011a4 <HW_TS_Start+0x104>) + 800113a: 781b ldrb r3, [r3, #0] + 800113c: 747b strb r3, [r7, #17] + + if(PreviousRunningTimerID != localcurrentrunningtimerid) + 800113e: 4b1a ldr r3, [pc, #104] @ (80011a8 <HW_TS_Start+0x108>) + 8001140: 781b ldrb r3, [r3, #0] + 8001142: b2db uxtb r3, r3 + 8001144: 7c7a ldrb r2, [r7, #17] + 8001146: 429a cmp r2, r3 + 8001148: d002 beq.n 8001150 <HW_TS_Start+0xb0> + { + RescheduleTimerList(); + 800114a: f7ff fd37 bl 8000bbc <RescheduleTimerList> + 800114e: e013 b.n 8001178 <HW_TS_Start+0xd8> + } + else + { + aTimerContext[timer_id].CountLeft -= time_elapsed; + 8001150: 79fa ldrb r2, [r7, #7] + 8001152: 4912 ldr r1, [pc, #72] @ (800119c <HW_TS_Start+0xfc>) + 8001154: 4613 mov r3, r2 + 8001156: 005b lsls r3, r3, #1 + 8001158: 4413 add r3, r2 + 800115a: 00db lsls r3, r3, #3 + 800115c: 440b add r3, r1 + 800115e: 3308 adds r3, #8 + 8001160: 6819 ldr r1, [r3, #0] + 8001162: 8a7b ldrh r3, [r7, #18] + 8001164: 79fa ldrb r2, [r7, #7] + 8001166: 1ac9 subs r1, r1, r3 + 8001168: 480c ldr r0, [pc, #48] @ (800119c <HW_TS_Start+0xfc>) + 800116a: 4613 mov r3, r2 + 800116c: 005b lsls r3, r3, #1 + 800116e: 4413 add r3, r2 + 8001170: 00db lsls r3, r3, #3 + 8001172: 4403 add r3, r0 + 8001174: 3308 adds r3, #8 + 8001176: 6019 str r1, [r3, #0] + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc ); + 8001178: 4b09 ldr r3, [pc, #36] @ (80011a0 <HW_TS_Start+0x100>) + 800117a: 681b ldr r3, [r3, #0] + 800117c: 22ff movs r2, #255 @ 0xff + 800117e: 625a str r2, [r3, #36] @ 0x24 + + HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Enable NVIC */ + 8001180: 2003 movs r0, #3 + 8001182: f000 fd88 bl 8001c96 <HAL_NVIC_EnableIRQ> + 8001186: 697b ldr r3, [r7, #20] + 8001188: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800118a: 68bb ldr r3, [r7, #8] + 800118c: f383 8810 msr PRIMASK, r3 +} + 8001190: bf00 nop + +#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) + __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ +#endif + + return; + 8001192: bf00 nop +} + 8001194: 3718 adds r7, #24 + 8001196: 46bd mov sp, r7 + 8001198: bd80 pop {r7, pc} + 800119a: bf00 nop + 800119c: 2000009c .word 0x2000009c + 80011a0: 200001cc .word 0x200001cc + 80011a4: 2000012c .word 0x2000012c + 80011a8: 2000012d .word 0x2000012d + +080011ac <LL_RCC_LSE_SetDriveCapability>: +{ + 80011ac: b480 push {r7} + 80011ae: b083 sub sp, #12 + 80011b0: af00 add r7, sp, #0 + 80011b2: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); + 80011b4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80011b8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80011bc: f023 0218 bic.w r2, r3, #24 + 80011c0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80011c4: 687b ldr r3, [r7, #4] + 80011c6: 4313 orrs r3, r2 + 80011c8: f8c1 3090 str.w r3, [r1, #144] @ 0x90 +} + 80011cc: bf00 nop + 80011ce: 370c adds r7, #12 + 80011d0: 46bd mov sp, r7 + 80011d2: f85d 7b04 ldr.w r7, [sp], #4 + 80011d6: 4770 bx lr + +080011d8 <LL_AHB2_GRP1_EnableClock>: + * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*) + * @note (*) Not supported by all the devices + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + 80011d8: b480 push {r7} + 80011da: b085 sub sp, #20 + 80011dc: af00 add r7, sp, #0 + 80011de: 6078 str r0, [r7, #4] + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2ENR, Periphs); + 80011e0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80011e4: 6cda ldr r2, [r3, #76] @ 0x4c + 80011e6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80011ea: 687b ldr r3, [r7, #4] + 80011ec: 4313 orrs r3, r2 + 80011ee: 64cb str r3, [r1, #76] @ 0x4c + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + 80011f0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80011f4: 6cda ldr r2, [r3, #76] @ 0x4c + 80011f6: 687b ldr r3, [r7, #4] + 80011f8: 4013 ands r3, r2 + 80011fa: 60fb str r3, [r7, #12] + (void)tmpreg; + 80011fc: 68fb ldr r3, [r7, #12] +} + 80011fe: bf00 nop + 8001200: 3714 adds r7, #20 + 8001202: 46bd mov sp, r7 + 8001204: f85d 7b04 ldr.w r7, [sp], #4 + 8001208: 4770 bx lr + ... + +0800120c <main>: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 800120c: b580 push {r7, lr} + 800120e: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 8001210: f000 fb5a bl 80018c8 <HAL_Init> + /* Config code for STM32_WPAN (HSE Tuning must be done before system clock configuration) */ + MX_APPE_Config(); + 8001214: f7ff f88e bl 8000334 <MX_APPE_Config> + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 8001218: f000 f81e bl 8001258 <SystemClock_Config> + + /* Configure the peripherals common clocks */ + PeriphCommonClock_Config(); + 800121c: f000 f878 bl 8001310 <PeriphCommonClock_Config> + + /* IPCC initialisation */ + MX_IPCC_Init(); + 8001220: f000 f8d4 bl 80013cc <MX_IPCC_Init> + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 8001224: f000 f94e bl 80014c4 <MX_GPIO_Init> + MX_I2C1_Init(); + 8001228: f000 f892 bl 8001350 <MX_I2C1_Init> + MX_RTC_Init(); + 800122c: f000 f8ea bl 8001404 <MX_RTC_Init> + MX_RF_Init(); + 8001230: f000 f8e0 bl 80013f4 <MX_RF_Init> + + + /* USER CODE END 2 */ + + /* Init code for STM32_WPAN */ + MX_APPE_Init(); + 8001234: f7ff f88c bl 8000350 <MX_APPE_Init> + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + MX_APPE_Process(); + 8001238: f7ff f9dc bl 80005f4 <MX_APPE_Process> + + /* USER CODE BEGIN 3 */ + HAL_Delay(5000); + 800123c: f241 3088 movw r0, #5000 @ 0x1388 + 8001240: f7ff f9b3 bl 80005aa <HAL_Delay> + __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU); + 8001244: 4b03 ldr r3, [pc, #12] @ (8001254 <main+0x48>) + 8001246: 221f movs r2, #31 + 8001248: 619a str r2, [r3, #24] + HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI); + 800124a: 2001 movs r0, #1 + 800124c: f001 f8ea bl 8002424 <HAL_PWREx_EnterSTOP2Mode> + MX_APPE_Process(); + 8001250: bf00 nop + 8001252: e7f1 b.n 8001238 <main+0x2c> + 8001254: 58000400 .word 0x58000400 + +08001258 <SystemClock_Config>: +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 8001258: b580 push {r7, lr} + 800125a: b09a sub sp, #104 @ 0x68 + 800125c: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 800125e: f107 0320 add.w r3, r7, #32 + 8001262: 2248 movs r2, #72 @ 0x48 + 8001264: 2100 movs r1, #0 + 8001266: 4618 mov r0, r3 + 8001268: f006 fc5d bl 8007b26 <memset> + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 800126c: 1d3b adds r3, r7, #4 + 800126e: 2200 movs r2, #0 + 8001270: 601a str r2, [r3, #0] + 8001272: 605a str r2, [r3, #4] + 8001274: 609a str r2, [r3, #8] + 8001276: 60da str r2, [r3, #12] + 8001278: 611a str r2, [r3, #16] + 800127a: 615a str r2, [r3, #20] + 800127c: 619a str r2, [r3, #24] + + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + 800127e: f001 f8b3 bl 80023e8 <HAL_PWR_EnableBkUpAccess> + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH); + 8001282: 2010 movs r0, #16 + 8001284: f7ff ff92 bl 80011ac <LL_RCC_LSE_SetDriveCapability> + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 8001288: 4b20 ldr r3, [pc, #128] @ (800130c <SystemClock_Config+0xb4>) + 800128a: 681b ldr r3, [r3, #0] + 800128c: f423 63c0 bic.w r3, r3, #1536 @ 0x600 + 8001290: 4a1e ldr r2, [pc, #120] @ (800130c <SystemClock_Config+0xb4>) + 8001292: f443 7300 orr.w r3, r3, #512 @ 0x200 + 8001296: 6013 str r3, [r2, #0] + 8001298: 4b1c ldr r3, [pc, #112] @ (800130c <SystemClock_Config+0xb4>) + 800129a: 681b ldr r3, [r3, #0] + 800129c: f403 63c0 and.w r3, r3, #1536 @ 0x600 + 80012a0: 603b str r3, [r7, #0] + 80012a2: 683b ldr r3, [r7, #0] + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE + 80012a4: 2307 movs r3, #7 + 80012a6: 623b str r3, [r7, #32] + |RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 80012a8: f44f 3380 mov.w r3, #65536 @ 0x10000 + 80012ac: 627b str r3, [r7, #36] @ 0x24 + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + 80012ae: 2301 movs r3, #1 + 80012b0: 62bb str r3, [r7, #40] @ 0x28 + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 80012b2: f44f 7380 mov.w r3, #256 @ 0x100 + 80012b6: 62fb str r3, [r7, #44] @ 0x2c + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 80012b8: 2340 movs r3, #64 @ 0x40 + 80012ba: 633b str r3, [r7, #48] @ 0x30 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 80012bc: 2300 movs r3, #0 + 80012be: 64fb str r3, [r7, #76] @ 0x4c + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 80012c0: f107 0320 add.w r3, r7, #32 + 80012c4: 4618 mov r0, r3 + 80012c6: f001 fc37 bl 8002b38 <HAL_RCC_OscConfig> + 80012ca: 4603 mov r3, r0 + 80012cc: 2b00 cmp r3, #0 + 80012ce: d001 beq.n 80012d4 <SystemClock_Config+0x7c> + { + Error_Handler(); + 80012d0: f000 f924 bl 800151c <Error_Handler> + } + + /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2 + 80012d4: 236f movs r3, #111 @ 0x6f + 80012d6: 607b str r3, [r7, #4] + |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; + 80012d8: 2302 movs r3, #2 + 80012da: 60bb str r3, [r7, #8] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV16; + 80012dc: 23b0 movs r3, #176 @ 0xb0 + 80012de: 60fb str r3, [r7, #12] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 80012e0: 2300 movs r3, #0 + 80012e2: 613b str r3, [r7, #16] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 80012e4: 2300 movs r3, #0 + 80012e6: 617b str r3, [r7, #20] + RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1; + 80012e8: 2300 movs r3, #0 + 80012ea: 61bb str r3, [r7, #24] + RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1; + 80012ec: 2300 movs r3, #0 + 80012ee: 61fb str r3, [r7, #28] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + 80012f0: 1d3b adds r3, r7, #4 + 80012f2: 2101 movs r1, #1 + 80012f4: 4618 mov r0, r3 + 80012f6: f001 ff93 bl 8003220 <HAL_RCC_ClockConfig> + 80012fa: 4603 mov r3, r0 + 80012fc: 2b00 cmp r3, #0 + 80012fe: d001 beq.n 8001304 <SystemClock_Config+0xac> + { + Error_Handler(); + 8001300: f000 f90c bl 800151c <Error_Handler> + } +} + 8001304: bf00 nop + 8001306: 3768 adds r7, #104 @ 0x68 + 8001308: 46bd mov sp, r7 + 800130a: bd80 pop {r7, pc} + 800130c: 58000400 .word 0x58000400 + +08001310 <PeriphCommonClock_Config>: +/** + * @brief Peripherals Common Clock Configuration + * @retval None + */ +void PeriphCommonClock_Config(void) +{ + 8001310: b580 push {r7, lr} + 8001312: b094 sub sp, #80 @ 0x50 + 8001314: af00 add r7, sp, #0 + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 8001316: 463b mov r3, r7 + 8001318: 2250 movs r2, #80 @ 0x50 + 800131a: 2100 movs r1, #0 + 800131c: 4618 mov r0, r3 + 800131e: f006 fc02 bl 8007b26 <memset> + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_RFWAKEUP; + 8001322: f44f 5340 mov.w r3, #12288 @ 0x3000 + 8001326: 603b str r3, [r7, #0] + PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_HSE_DIV1024; + 8001328: f44f 4340 mov.w r3, #49152 @ 0xc000 + 800132c: 647b str r3, [r7, #68] @ 0x44 + PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE; + 800132e: 2302 movs r3, #2 + 8001330: 64bb str r3, [r7, #72] @ 0x48 + PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE0; + 8001332: 2300 movs r3, #0 + 8001334: 64fb str r3, [r7, #76] @ 0x4c + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 8001336: 463b mov r3, r7 + 8001338: 4618 mov r0, r3 + 800133a: f002 fb82 bl 8003a42 <HAL_RCCEx_PeriphCLKConfig> + 800133e: 4603 mov r3, r0 + 8001340: 2b00 cmp r3, #0 + 8001342: d001 beq.n 8001348 <PeriphCommonClock_Config+0x38> + { + Error_Handler(); + 8001344: f000 f8ea bl 800151c <Error_Handler> + } + /* USER CODE BEGIN Smps */ + + /* USER CODE END Smps */ +} + 8001348: bf00 nop + 800134a: 3750 adds r7, #80 @ 0x50 + 800134c: 46bd mov sp, r7 + 800134e: bd80 pop {r7, pc} + +08001350 <MX_I2C1_Init>: + * @brief I2C1 Initialization Function + * @param None + * @retval None + */ +static void MX_I2C1_Init(void) +{ + 8001350: b580 push {r7, lr} + 8001352: af00 add r7, sp, #0 + /* USER CODE END I2C1_Init 0 */ + + /* USER CODE BEGIN I2C1_Init 1 */ + + /* USER CODE END I2C1_Init 1 */ + hi2c1.Instance = I2C1; + 8001354: 4b1b ldr r3, [pc, #108] @ (80013c4 <MX_I2C1_Init+0x74>) + 8001356: 4a1c ldr r2, [pc, #112] @ (80013c8 <MX_I2C1_Init+0x78>) + 8001358: 601a str r2, [r3, #0] + hi2c1.Init.Timing = 0x00000508; + 800135a: 4b1a ldr r3, [pc, #104] @ (80013c4 <MX_I2C1_Init+0x74>) + 800135c: f44f 62a1 mov.w r2, #1288 @ 0x508 + 8001360: 605a str r2, [r3, #4] + hi2c1.Init.OwnAddress1 = 0; + 8001362: 4b18 ldr r3, [pc, #96] @ (80013c4 <MX_I2C1_Init+0x74>) + 8001364: 2200 movs r2, #0 + 8001366: 609a str r2, [r3, #8] + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 8001368: 4b16 ldr r3, [pc, #88] @ (80013c4 <MX_I2C1_Init+0x74>) + 800136a: 2201 movs r2, #1 + 800136c: 60da str r2, [r3, #12] + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 800136e: 4b15 ldr r3, [pc, #84] @ (80013c4 <MX_I2C1_Init+0x74>) + 8001370: 2200 movs r2, #0 + 8001372: 611a str r2, [r3, #16] + hi2c1.Init.OwnAddress2 = 0; + 8001374: 4b13 ldr r3, [pc, #76] @ (80013c4 <MX_I2C1_Init+0x74>) + 8001376: 2200 movs r2, #0 + 8001378: 615a str r2, [r3, #20] + hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 800137a: 4b12 ldr r3, [pc, #72] @ (80013c4 <MX_I2C1_Init+0x74>) + 800137c: 2200 movs r2, #0 + 800137e: 619a str r2, [r3, #24] + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 8001380: 4b10 ldr r3, [pc, #64] @ (80013c4 <MX_I2C1_Init+0x74>) + 8001382: 2200 movs r2, #0 + 8001384: 61da str r2, [r3, #28] + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 8001386: 4b0f ldr r3, [pc, #60] @ (80013c4 <MX_I2C1_Init+0x74>) + 8001388: 2200 movs r2, #0 + 800138a: 621a str r2, [r3, #32] + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + 800138c: 480d ldr r0, [pc, #52] @ (80013c4 <MX_I2C1_Init+0x74>) + 800138e: f000 fe73 bl 8002078 <HAL_I2C_Init> + 8001392: 4603 mov r3, r0 + 8001394: 2b00 cmp r3, #0 + 8001396: d001 beq.n 800139c <MX_I2C1_Init+0x4c> + { + Error_Handler(); + 8001398: f000 f8c0 bl 800151c <Error_Handler> + } + + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + 800139c: 2100 movs r1, #0 + 800139e: 4809 ldr r0, [pc, #36] @ (80013c4 <MX_I2C1_Init+0x74>) + 80013a0: f000 ff05 bl 80021ae <HAL_I2CEx_ConfigAnalogFilter> + 80013a4: 4603 mov r3, r0 + 80013a6: 2b00 cmp r3, #0 + 80013a8: d001 beq.n 80013ae <MX_I2C1_Init+0x5e> + { + Error_Handler(); + 80013aa: f000 f8b7 bl 800151c <Error_Handler> + } + + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) + 80013ae: 2100 movs r1, #0 + 80013b0: 4804 ldr r0, [pc, #16] @ (80013c4 <MX_I2C1_Init+0x74>) + 80013b2: f000 ff47 bl 8002244 <HAL_I2CEx_ConfigDigitalFilter> + 80013b6: 4603 mov r3, r0 + 80013b8: 2b00 cmp r3, #0 + 80013ba: d001 beq.n 80013c0 <MX_I2C1_Init+0x70> + { + Error_Handler(); + 80013bc: f000 f8ae bl 800151c <Error_Handler> + } + /* USER CODE BEGIN I2C1_Init 2 */ + + /* USER CODE END I2C1_Init 2 */ + +} + 80013c0: bf00 nop + 80013c2: bd80 pop {r7, pc} + 80013c4: 2000013c .word 0x2000013c + 80013c8: 40005400 .word 0x40005400 + +080013cc <MX_IPCC_Init>: + * @brief IPCC Initialization Function + * @param None + * @retval None + */ +static void MX_IPCC_Init(void) +{ + 80013cc: b580 push {r7, lr} + 80013ce: af00 add r7, sp, #0 + /* USER CODE END IPCC_Init 0 */ + + /* USER CODE BEGIN IPCC_Init 1 */ + + /* USER CODE END IPCC_Init 1 */ + hipcc.Instance = IPCC; + 80013d0: 4b06 ldr r3, [pc, #24] @ (80013ec <MX_IPCC_Init+0x20>) + 80013d2: 4a07 ldr r2, [pc, #28] @ (80013f0 <MX_IPCC_Init+0x24>) + 80013d4: 601a str r2, [r3, #0] + if (HAL_IPCC_Init(&hipcc) != HAL_OK) + 80013d6: 4805 ldr r0, [pc, #20] @ (80013ec <MX_IPCC_Init+0x20>) + 80013d8: f000 ff80 bl 80022dc <HAL_IPCC_Init> + 80013dc: 4603 mov r3, r0 + 80013de: 2b00 cmp r3, #0 + 80013e0: d001 beq.n 80013e6 <MX_IPCC_Init+0x1a> + { + Error_Handler(); + 80013e2: f000 f89b bl 800151c <Error_Handler> + } + /* USER CODE BEGIN IPCC_Init 2 */ + + /* USER CODE END IPCC_Init 2 */ + +} + 80013e6: bf00 nop + 80013e8: bd80 pop {r7, pc} + 80013ea: bf00 nop + 80013ec: 20000190 .word 0x20000190 + 80013f0: 58000c00 .word 0x58000c00 + +080013f4 <MX_RF_Init>: + * @brief RF Initialization Function + * @param None + * @retval None + */ +static void MX_RF_Init(void) +{ + 80013f4: b480 push {r7} + 80013f6: af00 add r7, sp, #0 + /* USER CODE END RF_Init 1 */ + /* USER CODE BEGIN RF_Init 2 */ + + /* USER CODE END RF_Init 2 */ + +} + 80013f8: bf00 nop + 80013fa: 46bd mov sp, r7 + 80013fc: f85d 7b04 ldr.w r7, [sp], #4 + 8001400: 4770 bx lr + ... + +08001404 <MX_RTC_Init>: + * @brief RTC Initialization Function + * @param None + * @retval None + */ +static void MX_RTC_Init(void) +{ + 8001404: b580 push {r7, lr} + 8001406: b086 sub sp, #24 + 8001408: af00 add r7, sp, #0 + + /* USER CODE BEGIN RTC_Init 0 */ + + /* USER CODE END RTC_Init 0 */ + + RTC_TimeTypeDef sTime = {0}; + 800140a: 1d3b adds r3, r7, #4 + 800140c: 2200 movs r2, #0 + 800140e: 601a str r2, [r3, #0] + 8001410: 605a str r2, [r3, #4] + 8001412: 609a str r2, [r3, #8] + 8001414: 60da str r2, [r3, #12] + 8001416: 611a str r2, [r3, #16] + RTC_DateTypeDef sDate = {0}; + 8001418: 2300 movs r3, #0 + 800141a: 603b str r3, [r7, #0] + + /* USER CODE END RTC_Init 1 */ + + /** Initialize RTC Only + */ + hrtc.Instance = RTC; + 800141c: 4b27 ldr r3, [pc, #156] @ (80014bc <MX_RTC_Init+0xb8>) + 800141e: 4a28 ldr r2, [pc, #160] @ (80014c0 <MX_RTC_Init+0xbc>) + 8001420: 601a str r2, [r3, #0] + hrtc.Init.HourFormat = RTC_HOURFORMAT_24; + 8001422: 4b26 ldr r3, [pc, #152] @ (80014bc <MX_RTC_Init+0xb8>) + 8001424: 2200 movs r2, #0 + 8001426: 605a str r2, [r3, #4] + hrtc.Init.AsynchPrediv = CFG_RTC_ASYNCH_PRESCALER; + 8001428: 4b24 ldr r3, [pc, #144] @ (80014bc <MX_RTC_Init+0xb8>) + 800142a: 220f movs r2, #15 + 800142c: 609a str r2, [r3, #8] + hrtc.Init.SynchPrediv = CFG_RTC_SYNCH_PRESCALER; + 800142e: 4b23 ldr r3, [pc, #140] @ (80014bc <MX_RTC_Init+0xb8>) + 8001430: f647 72ff movw r2, #32767 @ 0x7fff + 8001434: 60da str r2, [r3, #12] + hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; + 8001436: 4b21 ldr r3, [pc, #132] @ (80014bc <MX_RTC_Init+0xb8>) + 8001438: 2200 movs r2, #0 + 800143a: 611a str r2, [r3, #16] + hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + 800143c: 4b1f ldr r3, [pc, #124] @ (80014bc <MX_RTC_Init+0xb8>) + 800143e: 2200 movs r2, #0 + 8001440: 619a str r2, [r3, #24] + hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + 8001442: 4b1e ldr r3, [pc, #120] @ (80014bc <MX_RTC_Init+0xb8>) + 8001444: 2200 movs r2, #0 + 8001446: 61da str r2, [r3, #28] + hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE; + 8001448: 4b1c ldr r3, [pc, #112] @ (80014bc <MX_RTC_Init+0xb8>) + 800144a: 2200 movs r2, #0 + 800144c: 615a str r2, [r3, #20] + if (HAL_RTC_Init(&hrtc) != HAL_OK) + 800144e: 481b ldr r0, [pc, #108] @ (80014bc <MX_RTC_Init+0xb8>) + 8001450: f002 fd7e bl 8003f50 <HAL_RTC_Init> + 8001454: 4603 mov r3, r0 + 8001456: 2b00 cmp r3, #0 + 8001458: d001 beq.n 800145e <MX_RTC_Init+0x5a> + { + Error_Handler(); + 800145a: f000 f85f bl 800151c <Error_Handler> + + /* USER CODE END Check_RTC_BKUP */ + + /** Initialize RTC and set the Time and Date + */ + sTime.Hours = 0x0; + 800145e: 2300 movs r3, #0 + 8001460: 713b strb r3, [r7, #4] + sTime.Minutes = 0x0; + 8001462: 2300 movs r3, #0 + 8001464: 717b strb r3, [r7, #5] + sTime.Seconds = 0x0; + 8001466: 2300 movs r3, #0 + 8001468: 71bb strb r3, [r7, #6] + sTime.SubSeconds = 0x0; + 800146a: 2300 movs r3, #0 + 800146c: 60bb str r3, [r7, #8] + sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; + 800146e: 2300 movs r3, #0 + 8001470: 613b str r3, [r7, #16] + sTime.StoreOperation = RTC_STOREOPERATION_RESET; + 8001472: 2300 movs r3, #0 + 8001474: 617b str r3, [r7, #20] + if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BCD) != HAL_OK) + 8001476: 1d3b adds r3, r7, #4 + 8001478: 2201 movs r2, #1 + 800147a: 4619 mov r1, r3 + 800147c: 480f ldr r0, [pc, #60] @ (80014bc <MX_RTC_Init+0xb8>) + 800147e: f002 fdef bl 8004060 <HAL_RTC_SetTime> + 8001482: 4603 mov r3, r0 + 8001484: 2b00 cmp r3, #0 + 8001486: d001 beq.n 800148c <MX_RTC_Init+0x88> + { + Error_Handler(); + 8001488: f000 f848 bl 800151c <Error_Handler> + } + sDate.WeekDay = RTC_WEEKDAY_MONDAY; + 800148c: 2301 movs r3, #1 + 800148e: 703b strb r3, [r7, #0] + sDate.Month = RTC_MONTH_JANUARY; + 8001490: 2301 movs r3, #1 + 8001492: 707b strb r3, [r7, #1] + sDate.Date = 0x1; + 8001494: 2301 movs r3, #1 + 8001496: 70bb strb r3, [r7, #2] + sDate.Year = 0x0; + 8001498: 2300 movs r3, #0 + 800149a: 70fb strb r3, [r7, #3] + + if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BCD) != HAL_OK) + 800149c: 463b mov r3, r7 + 800149e: 2201 movs r2, #1 + 80014a0: 4619 mov r1, r3 + 80014a2: 4806 ldr r0, [pc, #24] @ (80014bc <MX_RTC_Init+0xb8>) + 80014a4: f002 fe7b bl 800419e <HAL_RTC_SetDate> + 80014a8: 4603 mov r3, r0 + 80014aa: 2b00 cmp r3, #0 + 80014ac: d001 beq.n 80014b2 <MX_RTC_Init+0xae> + { + Error_Handler(); + 80014ae: f000 f835 bl 800151c <Error_Handler> + } + /* USER CODE BEGIN RTC_Init 2 */ + + /* USER CODE END RTC_Init 2 */ + +} + 80014b2: bf00 nop + 80014b4: 3718 adds r7, #24 + 80014b6: 46bd mov sp, r7 + 80014b8: bd80 pop {r7, pc} + 80014ba: bf00 nop + 80014bc: 200001cc .word 0x200001cc + 80014c0: 40002800 .word 0x40002800 + +080014c4 <MX_GPIO_Init>: + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 80014c4: b580 push {r7, lr} + 80014c6: b086 sub sp, #24 + 80014c8: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80014ca: 1d3b adds r3, r7, #4 + 80014cc: 2200 movs r2, #0 + 80014ce: 601a str r2, [r3, #0] + 80014d0: 605a str r2, [r3, #4] + 80014d2: 609a str r2, [r3, #8] + 80014d4: 60da str r2, [r3, #12] + 80014d6: 611a str r2, [r3, #16] + /* USER CODE BEGIN MX_GPIO_Init_1 */ + + /* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 80014d8: 2004 movs r0, #4 + 80014da: f7ff fe7d bl 80011d8 <LL_AHB2_GRP1_EnableClock> + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80014de: 2001 movs r0, #1 + 80014e0: f7ff fe7a bl 80011d8 <LL_AHB2_GRP1_EnableClock> + __HAL_RCC_GPIOB_CLK_ENABLE(); + 80014e4: 2002 movs r0, #2 + 80014e6: f7ff fe77 bl 80011d8 <LL_AHB2_GRP1_EnableClock> + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4|GPIO_PIN_5, GPIO_PIN_SET); + 80014ea: 2201 movs r2, #1 + 80014ec: 2130 movs r1, #48 @ 0x30 + 80014ee: 480a ldr r0, [pc, #40] @ (8001518 <MX_GPIO_Init+0x54>) + 80014f0: f000 fd86 bl 8002000 <HAL_GPIO_WritePin> + + /*Configure GPIO pins : PB4 PB5 */ + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; + 80014f4: 2330 movs r3, #48 @ 0x30 + 80014f6: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 80014f8: 2301 movs r3, #1 + 80014fa: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 80014fc: 2301 movs r3, #1 + 80014fe: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001500: 2300 movs r3, #0 + 8001502: 613b str r3, [r7, #16] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8001504: 1d3b adds r3, r7, #4 + 8001506: 4619 mov r1, r3 + 8001508: 4803 ldr r0, [pc, #12] @ (8001518 <MX_GPIO_Init+0x54>) + 800150a: f000 fc09 bl 8001d20 <HAL_GPIO_Init> + + /* USER CODE BEGIN MX_GPIO_Init_2 */ + + /* USER CODE END MX_GPIO_Init_2 */ +} + 800150e: bf00 nop + 8001510: 3718 adds r7, #24 + 8001512: 46bd mov sp, r7 + 8001514: bd80 pop {r7, pc} + 8001516: bf00 nop + 8001518: 48000400 .word 0x48000400 + +0800151c <Error_Handler>: +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 800151c: b480 push {r7} + 800151e: af00 add r7, sp, #0 + __ASM volatile ("cpsid i" : : : "memory"); + 8001520: b672 cpsid i +} + 8001522: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 8001524: bf00 nop + 8001526: e7fd b.n 8001524 <Error_Handler+0x8> + +08001528 <LL_RCC_EnableRTC>: + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + 8001528: b480 push {r7} + 800152a: af00 add r7, sp, #0 + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); + 800152c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001530: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8001534: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8001538: f443 4300 orr.w r3, r3, #32768 @ 0x8000 + 800153c: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 8001540: bf00 nop + 8001542: 46bd mov sp, r7 + 8001544: f85d 7b04 ldr.w r7, [sp], #4 + 8001548: 4770 bx lr + +0800154a <LL_AHB2_GRP1_EnableClock>: +{ + 800154a: b480 push {r7} + 800154c: b085 sub sp, #20 + 800154e: af00 add r7, sp, #0 + 8001550: 6078 str r0, [r7, #4] + SET_BIT(RCC->AHB2ENR, Periphs); + 8001552: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001556: 6cda ldr r2, [r3, #76] @ 0x4c + 8001558: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800155c: 687b ldr r3, [r7, #4] + 800155e: 4313 orrs r3, r2 + 8001560: 64cb str r3, [r1, #76] @ 0x4c + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + 8001562: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001566: 6cda ldr r2, [r3, #76] @ 0x4c + 8001568: 687b ldr r3, [r7, #4] + 800156a: 4013 ands r3, r2 + 800156c: 60fb str r3, [r7, #12] + (void)tmpreg; + 800156e: 68fb ldr r3, [r7, #12] +} + 8001570: bf00 nop + 8001572: 3714 adds r7, #20 + 8001574: 46bd mov sp, r7 + 8001576: f85d 7b04 ldr.w r7, [sp], #4 + 800157a: 4770 bx lr + +0800157c <LL_AHB3_GRP1_EnableClock>: + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @note (*) Not supported by all the devices + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + 800157c: b480 push {r7} + 800157e: b085 sub sp, #20 + 8001580: af00 add r7, sp, #0 + 8001582: 6078 str r0, [r7, #4] + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3ENR, Periphs); + 8001584: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001588: 6d1a ldr r2, [r3, #80] @ 0x50 + 800158a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800158e: 687b ldr r3, [r7, #4] + 8001590: 4313 orrs r3, r2 + 8001592: 650b str r3, [r1, #80] @ 0x50 + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); + 8001594: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001598: 6d1a ldr r2, [r3, #80] @ 0x50 + 800159a: 687b ldr r3, [r7, #4] + 800159c: 4013 ands r3, r2 + 800159e: 60fb str r3, [r7, #12] + (void)tmpreg; + 80015a0: 68fb ldr r3, [r7, #12] +} + 80015a2: bf00 nop + 80015a4: 3714 adds r7, #20 + 80015a6: 46bd mov sp, r7 + 80015a8: f85d 7b04 ldr.w r7, [sp], #4 + 80015ac: 4770 bx lr + +080015ae <LL_APB1_GRP1_EnableClock>: + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @note (*) Not supported by all the devices + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + 80015ae: b480 push {r7} + 80015b0: b085 sub sp, #20 + 80015b2: af00 add r7, sp, #0 + 80015b4: 6078 str r0, [r7, #4] + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR1, Periphs); + 80015b6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80015ba: 6d9a ldr r2, [r3, #88] @ 0x58 + 80015bc: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80015c0: 687b ldr r3, [r7, #4] + 80015c2: 4313 orrs r3, r2 + 80015c4: 658b str r3, [r1, #88] @ 0x58 + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); + 80015c6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80015ca: 6d9a ldr r2, [r3, #88] @ 0x58 + 80015cc: 687b ldr r3, [r7, #4] + 80015ce: 4013 ands r3, r2 + 80015d0: 60fb str r3, [r7, #12] + (void)tmpreg; + 80015d2: 68fb ldr r3, [r7, #12] +} + 80015d4: bf00 nop + 80015d6: 3714 adds r7, #20 + 80015d8: 46bd mov sp, r7 + 80015da: f85d 7b04 ldr.w r7, [sp], #4 + 80015de: 4770 bx lr + +080015e0 <HAL_MspInit>: +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 80015e0: b580 push {r7, lr} + 80015e2: af00 add r7, sp, #0 + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_HSEM_CLK_ENABLE(); + 80015e4: f44f 2000 mov.w r0, #524288 @ 0x80000 + 80015e8: f7ff ffc8 bl 800157c <LL_AHB3_GRP1_EnableClock> + + /* System interrupt init*/ + + /* Peripheral interrupt init */ + /* HSEM_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(HSEM_IRQn, 0, 0); + 80015ec: 2200 movs r2, #0 + 80015ee: 2100 movs r1, #0 + 80015f0: 202e movs r0, #46 @ 0x2e + 80015f2: f000 fb36 bl 8001c62 <HAL_NVIC_SetPriority> + HAL_NVIC_EnableIRQ(HSEM_IRQn); + 80015f6: 202e movs r0, #46 @ 0x2e + 80015f8: f000 fb4d bl 8001c96 <HAL_NVIC_EnableIRQ> + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 80015fc: bf00 nop + 80015fe: bd80 pop {r7, pc} + +08001600 <HAL_I2C_MspInit>: + * This function configures the hardware resources used in this example + * @param hi2c: I2C handle pointer + * @retval None + */ +void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) +{ + 8001600: b580 push {r7, lr} + 8001602: b09c sub sp, #112 @ 0x70 + 8001604: af00 add r7, sp, #0 + 8001606: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8001608: f107 035c add.w r3, r7, #92 @ 0x5c + 800160c: 2200 movs r2, #0 + 800160e: 601a str r2, [r3, #0] + 8001610: 605a str r2, [r3, #4] + 8001612: 609a str r2, [r3, #8] + 8001614: 60da str r2, [r3, #12] + 8001616: 611a str r2, [r3, #16] + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 8001618: f107 030c add.w r3, r7, #12 + 800161c: 2250 movs r2, #80 @ 0x50 + 800161e: 2100 movs r1, #0 + 8001620: 4618 mov r0, r3 + 8001622: f006 fa80 bl 8007b26 <memset> + if(hi2c->Instance==I2C1) + 8001626: 687b ldr r3, [r7, #4] + 8001628: 681b ldr r3, [r3, #0] + 800162a: 4a16 ldr r2, [pc, #88] @ (8001684 <HAL_I2C_MspInit+0x84>) + 800162c: 4293 cmp r3, r2 + 800162e: d125 bne.n 800167c <HAL_I2C_MspInit+0x7c> + + /* USER CODE END I2C1_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C1; + 8001630: 2304 movs r3, #4 + 8001632: 60fb str r3, [r7, #12] + PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1; + 8001634: f44f 3340 mov.w r3, #196608 @ 0x30000 + 8001638: 62fb str r3, [r7, #44] @ 0x2c + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 800163a: f107 030c add.w r3, r7, #12 + 800163e: 4618 mov r0, r3 + 8001640: f002 f9ff bl 8003a42 <HAL_RCCEx_PeriphCLKConfig> + 8001644: 4603 mov r3, r0 + 8001646: 2b00 cmp r3, #0 + 8001648: d001 beq.n 800164e <HAL_I2C_MspInit+0x4e> + { + Error_Handler(); + 800164a: f7ff ff67 bl 800151c <Error_Handler> + } + + __HAL_RCC_GPIOB_CLK_ENABLE(); + 800164e: 2002 movs r0, #2 + 8001650: f7ff ff7b bl 800154a <LL_AHB2_GRP1_EnableClock> + /**I2C1 GPIO Configuration + PB6 ------> I2C1_SCL + PB7 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + 8001654: 23c0 movs r3, #192 @ 0xc0 + 8001656: 65fb str r3, [r7, #92] @ 0x5c + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 8001658: 2312 movs r3, #18 + 800165a: 663b str r3, [r7, #96] @ 0x60 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800165c: 2300 movs r3, #0 + 800165e: 667b str r3, [r7, #100] @ 0x64 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001660: 2300 movs r3, #0 + 8001662: 66bb str r3, [r7, #104] @ 0x68 + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + 8001664: 2304 movs r3, #4 + 8001666: 66fb str r3, [r7, #108] @ 0x6c + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8001668: f107 035c add.w r3, r7, #92 @ 0x5c + 800166c: 4619 mov r1, r3 + 800166e: 4806 ldr r0, [pc, #24] @ (8001688 <HAL_I2C_MspInit+0x88>) + 8001670: f000 fb56 bl 8001d20 <HAL_GPIO_Init> + + /* Peripheral clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + 8001674: f44f 1000 mov.w r0, #2097152 @ 0x200000 + 8001678: f7ff ff99 bl 80015ae <LL_APB1_GRP1_EnableClock> + + /* USER CODE END I2C1_MspInit 1 */ + + } + +} + 800167c: bf00 nop + 800167e: 3770 adds r7, #112 @ 0x70 + 8001680: 46bd mov sp, r7 + 8001682: bd80 pop {r7, pc} + 8001684: 40005400 .word 0x40005400 + 8001688: 48000400 .word 0x48000400 + +0800168c <HAL_IPCC_MspInit>: + * This function configures the hardware resources used in this example + * @param hipcc: IPCC handle pointer + * @retval None + */ +void HAL_IPCC_MspInit(IPCC_HandleTypeDef* hipcc) +{ + 800168c: b580 push {r7, lr} + 800168e: b082 sub sp, #8 + 8001690: af00 add r7, sp, #0 + 8001692: 6078 str r0, [r7, #4] + if(hipcc->Instance==IPCC) + 8001694: 687b ldr r3, [r7, #4] + 8001696: 681b ldr r3, [r3, #0] + 8001698: 4a0d ldr r2, [pc, #52] @ (80016d0 <HAL_IPCC_MspInit+0x44>) + 800169a: 4293 cmp r3, r2 + 800169c: d113 bne.n 80016c6 <HAL_IPCC_MspInit+0x3a> + { + /* USER CODE BEGIN IPCC_MspInit 0 */ + + /* USER CODE END IPCC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_IPCC_CLK_ENABLE(); + 800169e: f44f 1080 mov.w r0, #1048576 @ 0x100000 + 80016a2: f7ff ff6b bl 800157c <LL_AHB3_GRP1_EnableClock> + /* IPCC interrupt Init */ + HAL_NVIC_SetPriority(IPCC_C1_RX_IRQn, 0, 0); + 80016a6: 2200 movs r2, #0 + 80016a8: 2100 movs r1, #0 + 80016aa: 202c movs r0, #44 @ 0x2c + 80016ac: f000 fad9 bl 8001c62 <HAL_NVIC_SetPriority> + HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn); + 80016b0: 202c movs r0, #44 @ 0x2c + 80016b2: f000 faf0 bl 8001c96 <HAL_NVIC_EnableIRQ> + HAL_NVIC_SetPriority(IPCC_C1_TX_IRQn, 0, 0); + 80016b6: 2200 movs r2, #0 + 80016b8: 2100 movs r1, #0 + 80016ba: 202d movs r0, #45 @ 0x2d + 80016bc: f000 fad1 bl 8001c62 <HAL_NVIC_SetPriority> + HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn); + 80016c0: 202d movs r0, #45 @ 0x2d + 80016c2: f000 fae8 bl 8001c96 <HAL_NVIC_EnableIRQ> + + /* USER CODE END IPCC_MspInit 1 */ + + } + +} + 80016c6: bf00 nop + 80016c8: 3708 adds r7, #8 + 80016ca: 46bd mov sp, r7 + 80016cc: bd80 pop {r7, pc} + 80016ce: bf00 nop + 80016d0: 58000c00 .word 0x58000c00 + +080016d4 <HAL_RTC_MspInit>: + * This function configures the hardware resources used in this example + * @param hrtc: RTC handle pointer + * @retval None + */ +void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) +{ + 80016d4: b580 push {r7, lr} + 80016d6: b096 sub sp, #88 @ 0x58 + 80016d8: af00 add r7, sp, #0 + 80016da: 6078 str r0, [r7, #4] + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 80016dc: f107 0308 add.w r3, r7, #8 + 80016e0: 2250 movs r2, #80 @ 0x50 + 80016e2: 2100 movs r1, #0 + 80016e4: 4618 mov r0, r3 + 80016e6: f006 fa1e bl 8007b26 <memset> + if(hrtc->Instance==RTC) + 80016ea: 687b ldr r3, [r7, #4] + 80016ec: 681b ldr r3, [r3, #0] + 80016ee: 4a0e ldr r2, [pc, #56] @ (8001728 <HAL_RTC_MspInit+0x54>) + 80016f0: 4293 cmp r3, r2 + 80016f2: d115 bne.n 8001720 <HAL_RTC_MspInit+0x4c> + + /* USER CODE END RTC_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + 80016f4: f44f 6300 mov.w r3, #2048 @ 0x800 + 80016f8: 60bb str r3, [r7, #8] + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + 80016fa: f44f 7380 mov.w r3, #256 @ 0x100 + 80016fe: 64bb str r3, [r7, #72] @ 0x48 + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 8001700: f107 0308 add.w r3, r7, #8 + 8001704: 4618 mov r0, r3 + 8001706: f002 f99c bl 8003a42 <HAL_RCCEx_PeriphCLKConfig> + 800170a: 4603 mov r3, r0 + 800170c: 2b00 cmp r3, #0 + 800170e: d001 beq.n 8001714 <HAL_RTC_MspInit+0x40> + { + Error_Handler(); + 8001710: f7ff ff04 bl 800151c <Error_Handler> + } + + /* Peripheral clock enable */ + __HAL_RCC_RTC_ENABLE(); + 8001714: f7ff ff08 bl 8001528 <LL_RCC_EnableRTC> + __HAL_RCC_RTCAPB_CLK_ENABLE(); + 8001718: f44f 6080 mov.w r0, #1024 @ 0x400 + 800171c: f7ff ff47 bl 80015ae <LL_APB1_GRP1_EnableClock> + + /* USER CODE END RTC_MspInit 1 */ + + } + +} + 8001720: bf00 nop + 8001722: 3758 adds r7, #88 @ 0x58 + 8001724: 46bd mov sp, r7 + 8001726: bd80 pop {r7, pc} + 8001728: 40002800 .word 0x40002800 + +0800172c <NMI_Handler>: +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 800172c: b480 push {r7} + 800172e: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 8001730: bf00 nop + 8001732: e7fd b.n 8001730 <NMI_Handler+0x4> + +08001734 <HardFault_Handler>: + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 8001734: b480 push {r7} + 8001736: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 8001738: bf00 nop + 800173a: e7fd b.n 8001738 <HardFault_Handler+0x4> + +0800173c <MemManage_Handler>: + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 800173c: b480 push {r7} + 800173e: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 8001740: bf00 nop + 8001742: e7fd b.n 8001740 <MemManage_Handler+0x4> + +08001744 <BusFault_Handler>: + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 8001744: b480 push {r7} + 8001746: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 8001748: bf00 nop + 800174a: e7fd b.n 8001748 <BusFault_Handler+0x4> + +0800174c <UsageFault_Handler>: + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 800174c: b480 push {r7} + 800174e: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 8001750: bf00 nop + 8001752: e7fd b.n 8001750 <UsageFault_Handler+0x4> + +08001754 <SVC_Handler>: + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 8001754: b480 push {r7} + 8001756: af00 add r7, sp, #0 + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + 8001758: bf00 nop + 800175a: 46bd mov sp, r7 + 800175c: f85d 7b04 ldr.w r7, [sp], #4 + 8001760: 4770 bx lr + +08001762 <DebugMon_Handler>: + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 8001762: b480 push {r7} + 8001764: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 8001766: bf00 nop + 8001768: 46bd mov sp, r7 + 800176a: f85d 7b04 ldr.w r7, [sp], #4 + 800176e: 4770 bx lr + +08001770 <PendSV_Handler>: + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 8001770: b480 push {r7} + 8001772: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8001774: bf00 nop + 8001776: 46bd mov sp, r7 + 8001778: f85d 7b04 ldr.w r7, [sp], #4 + 800177c: 4770 bx lr + +0800177e <SysTick_Handler>: + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 800177e: b580 push {r7, lr} + 8001780: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 8001782: f000 f8fb bl 800197c <HAL_IncTick> + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8001786: bf00 nop + 8001788: bd80 pop {r7, pc} + +0800178a <IPCC_C1_RX_IRQHandler>: + +/** + * @brief This function handles IPCC RX occupied interrupt. + */ +void IPCC_C1_RX_IRQHandler(void) +{ + 800178a: b580 push {r7, lr} + 800178c: af00 add r7, sp, #0 + /* USER CODE BEGIN IPCC_C1_RX_IRQn 0 */ + + /* USER CODE END IPCC_C1_RX_IRQn 0 */ + HAL_IPCC_RX_IRQHandler(&hipcc); + 800178e: f005 fd01 bl 8007194 <HW_IPCC_Rx_Handler> + /* USER CODE BEGIN IPCC_C1_RX_IRQn 1 */ + + /* USER CODE END IPCC_C1_RX_IRQn 1 */ +} + 8001792: bf00 nop + 8001794: bd80 pop {r7, pc} + +08001796 <IPCC_C1_TX_IRQHandler>: + +/** + * @brief This function handles IPCC TX free interrupt. + */ +void IPCC_C1_TX_IRQHandler(void) +{ + 8001796: b580 push {r7, lr} + 8001798: af00 add r7, sp, #0 + /* USER CODE BEGIN IPCC_C1_TX_IRQn 0 */ + + /* USER CODE END IPCC_C1_TX_IRQn 0 */ + HAL_IPCC_TX_IRQHandler(&hipcc); + 800179a: f005 fd31 bl 8007200 <HW_IPCC_Tx_Handler> + /* USER CODE BEGIN IPCC_C1_TX_IRQn 1 */ + + /* USER CODE END IPCC_C1_TX_IRQn 1 */ +} + 800179e: bf00 nop + 80017a0: bd80 pop {r7, pc} + +080017a2 <HSEM_IRQHandler>: + +/** + * @brief This function handles HSEM global interrupt. + */ +void HSEM_IRQHandler(void) +{ + 80017a2: b580 push {r7, lr} + 80017a4: af00 add r7, sp, #0 + /* USER CODE BEGIN HSEM_IRQn 0 */ + + /* USER CODE END HSEM_IRQn 0 */ + HAL_HSEM_IRQHandler(); + 80017a6: f000 fc43 bl 8002030 <HAL_HSEM_IRQHandler> + /* USER CODE BEGIN HSEM_IRQn 1 */ + + /* USER CODE END HSEM_IRQn 1 */ +} + 80017aa: bf00 nop + 80017ac: bd80 pop {r7, pc} + ... + +080017b0 <SystemInit>: + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit(void) +{ + 80017b0: b480 push {r7} + 80017b2: af00 add r7, sp, #0 + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; +#endif /* USER_VECT_TAB_ADDRESS */ + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10UL * 2UL)) | (3UL << (11UL * 2UL))); /* set CP10 and CP11 Full Access */ + 80017b4: 4b24 ldr r3, [pc, #144] @ (8001848 <SystemInit+0x98>) + 80017b6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 80017ba: 4a23 ldr r2, [pc, #140] @ (8001848 <SystemInit+0x98>) + 80017bc: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 + 80017c0: f8c2 3088 str.w r3, [r2, #136] @ 0x88 +#endif /* FPU */ + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC->CR |= RCC_CR_MSION; + 80017c4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80017c8: 681b ldr r3, [r3, #0] + 80017ca: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80017ce: f043 0301 orr.w r3, r3, #1 + 80017d2: 6013 str r3, [r2, #0] + + /* Reset CFGR register */ + RCC->CFGR = 0x00070000U; + 80017d4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80017d8: f44f 22e0 mov.w r2, #458752 @ 0x70000 + 80017dc: 609a str r2, [r3, #8] + + /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */ + RCC->CR &= (uint32_t)0xFAF6FEFBU; + 80017de: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80017e2: 681a ldr r2, [r3, #0] + 80017e4: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80017e8: 4b18 ldr r3, [pc, #96] @ (800184c <SystemInit+0x9c>) + 80017ea: 4013 ands r3, r2 + 80017ec: 600b str r3, [r1, #0] + + /*!< Reset LSI1 and LSI2 bits */ + RCC->CSR &= (uint32_t)0xFFFFFFFAU; + 80017ee: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80017f2: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 80017f6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80017fa: f023 0305 bic.w r3, r3, #5 + 80017fe: f8c2 3094 str.w r3, [r2, #148] @ 0x94 + + /*!< Reset HSI48ON bit */ + RCC->CRRCR &= (uint32_t)0xFFFFFFFEU; + 8001802: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001806: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 + 800180a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 800180e: f023 0301 bic.w r3, r3, #1 + 8001812: f8c2 3098 str.w r3, [r2, #152] @ 0x98 + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x22041000U; + 8001816: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800181a: 4a0d ldr r2, [pc, #52] @ (8001850 <SystemInit+0xa0>) + 800181c: 60da str r2, [r3, #12] + +#if defined(STM32WB55xx) || defined(STM32WB5Mxx) + /* Reset PLLSAI1CFGR register */ + RCC->PLLSAI1CFGR = 0x22041000U; + 800181e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001822: 4a0b ldr r2, [pc, #44] @ (8001850 <SystemInit+0xa0>) + 8001824: 611a str r2, [r3, #16] +#endif /* STM32WB55xx || STM32WB5Mxx */ + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + 8001826: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800182a: 681b ldr r3, [r3, #0] + 800182c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8001830: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8001834: 6013 str r3, [r2, #0] + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + 8001836: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800183a: 2200 movs r2, #0 + 800183c: 619a str r2, [r3, #24] +} + 800183e: bf00 nop + 8001840: 46bd mov sp, r7 + 8001842: f85d 7b04 ldr.w r7, [sp], #4 + 8001846: 4770 bx lr + 8001848: e000ed00 .word 0xe000ed00 + 800184c: faf6fefb .word 0xfaf6fefb + 8001850: 22041000 .word 0x22041000 + +08001854 <CopyDataInit>: + bl LoopCopyDataInit +.endm + +.section .text.data_initializers +CopyDataInit: + ldr r4, [r2, r3] + 8001854: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 8001856: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 8001858: 3304 adds r3, #4 + +0800185a <LoopCopyDataInit>: + +LoopCopyDataInit: + adds r4, r0, r3 + 800185a: 18c4 adds r4, r0, r3 + cmp r4, r1 + 800185c: 428c cmp r4, r1 + bcc CopyDataInit + 800185e: d3f9 bcc.n 8001854 <CopyDataInit> + bx lr + 8001860: 4770 bx lr + +08001862 <FillZerobss>: + +FillZerobss: + str r3, [r0] + 8001862: 6003 str r3, [r0, #0] + adds r0, r0, #4 + 8001864: 3004 adds r0, #4 + +08001866 <LoopFillZerobss>: + +LoopFillZerobss: + cmp r0, r1 + 8001866: 4288 cmp r0, r1 + bcc FillZerobss + 8001868: d3fb bcc.n 8001862 <FillZerobss> + bx lr + 800186a: 4770 bx lr + +0800186c <Reset_Handler>: + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + 800186c: 480c ldr r0, [pc, #48] @ (80018a0 <LoopForever+0x2>) + mov sp, r0 /* set stack pointer */ + 800186e: 4685 mov sp, r0 +/* Call the clock system initialization function.*/ + bl SystemInit + 8001870: f7ff ff9e bl 80017b0 <SystemInit> + +/* Copy the data segment initializers from flash to SRAM */ + INIT_DATA _sdata, _edata, _sidata + 8001874: 480b ldr r0, [pc, #44] @ (80018a4 <LoopForever+0x6>) + 8001876: 490c ldr r1, [pc, #48] @ (80018a8 <LoopForever+0xa>) + 8001878: 4a0c ldr r2, [pc, #48] @ (80018ac <LoopForever+0xe>) + 800187a: 2300 movs r3, #0 + 800187c: f7ff ffed bl 800185a <LoopCopyDataInit> + INIT_DATA _sMB_MEM2, _eMB_MEM2, _siMB_MEM2 + 8001880: 480b ldr r0, [pc, #44] @ (80018b0 <LoopForever+0x12>) + 8001882: 490c ldr r1, [pc, #48] @ (80018b4 <LoopForever+0x16>) + 8001884: 4a0c ldr r2, [pc, #48] @ (80018b8 <LoopForever+0x1a>) + 8001886: 2300 movs r3, #0 + 8001888: f7ff ffe7 bl 800185a <LoopCopyDataInit> + +/* Zero fill the bss segments. */ + INIT_BSS _sbss, _ebss + 800188c: 480b ldr r0, [pc, #44] @ (80018bc <LoopForever+0x1e>) + 800188e: 490c ldr r1, [pc, #48] @ (80018c0 <LoopForever+0x22>) + 8001890: 2300 movs r3, #0 + 8001892: f7ff ffe8 bl 8001866 <LoopFillZerobss> + +/* Call static constructors */ + bl __libc_init_array + 8001896: f006 f94f bl 8007b38 <__libc_init_array> +/* Call the application s entry point.*/ + bl main + 800189a: f7ff fcb7 bl 800120c <main> + +0800189e <LoopForever>: + +LoopForever: + b LoopForever + 800189e: e7fe b.n 800189e <LoopForever> + ldr r0, =_estack + 80018a0: 20030000 .word 0x20030000 + INIT_DATA _sdata, _edata, _sidata + 80018a4: 20000008 .word 0x20000008 + 80018a8: 2000002c .word 0x2000002c + 80018ac: 08007e30 .word 0x08007e30 + INIT_DATA _sMB_MEM2, _eMB_MEM2, _siMB_MEM2 + 80018b0: 200301e4 .word 0x200301e4 + 80018b4: 20030a67 .word 0x20030a67 + 80018b8: 08007ea2 .word 0x08007ea2 + INIT_BSS _sbss, _ebss + 80018bc: 20000080 .word 0x20000080 + 80018c0: 200003a4 .word 0x200003a4 + +080018c4 <ADC1_IRQHandler>: + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 80018c4: e7fe b.n 80018c4 <ADC1_IRQHandler> + ... + +080018c8 <HAL_Init>: + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 80018c8: b580 push {r7, lr} + 80018ca: b082 sub sp, #8 + 80018cc: af00 add r7, sp, #0 + HAL_StatusTypeDef status = HAL_OK; + 80018ce: 2300 movs r3, #0 + 80018d0: 71fb strb r3, [r7, #7] +#if (DATA_CACHE_ENABLE == 0U) + __HAL_FLASH_DATA_CACHE_DISABLE(); +#endif /* DATA_CACHE_ENABLE */ + +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); + 80018d2: 4b0c ldr r3, [pc, #48] @ (8001904 <HAL_Init+0x3c>) + 80018d4: 681b ldr r3, [r3, #0] + 80018d6: 4a0b ldr r2, [pc, #44] @ (8001904 <HAL_Init+0x3c>) + 80018d8: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80018dc: 6013 str r3, [r2, #0] +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 80018de: 2003 movs r0, #3 + 80018e0: f000 f9b4 bl 8001c4c <HAL_NVIC_SetPriorityGrouping> + + /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 80018e4: 200f movs r0, #15 + 80018e6: f000 f80f bl 8001908 <HAL_InitTick> + 80018ea: 4603 mov r3, r0 + 80018ec: 2b00 cmp r3, #0 + 80018ee: d002 beq.n 80018f6 <HAL_Init+0x2e> + { + status = HAL_ERROR; + 80018f0: 2301 movs r3, #1 + 80018f2: 71fb strb r3, [r7, #7] + 80018f4: e001 b.n 80018fa <HAL_Init+0x32> + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + 80018f6: f7ff fe73 bl 80015e0 <HAL_MspInit> + } + + /* Return function status */ + return status; + 80018fa: 79fb ldrb r3, [r7, #7] +} + 80018fc: 4618 mov r0, r3 + 80018fe: 3708 adds r7, #8 + 8001900: 46bd mov sp, r7 + 8001902: bd80 pop {r7, pc} + 8001904: 58004000 .word 0x58004000 + +08001908 <HAL_InitTick>: + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8001908: b580 push {r7, lr} + 800190a: b084 sub sp, #16 + 800190c: af00 add r7, sp, #0 + 800190e: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8001910: 2300 movs r3, #0 + 8001912: 73fb strb r3, [r7, #15] + + if ((uint32_t)uwTickFreq != 0U) + 8001914: 4b17 ldr r3, [pc, #92] @ (8001974 <HAL_InitTick+0x6c>) + 8001916: 781b ldrb r3, [r3, #0] + 8001918: 2b00 cmp r3, #0 + 800191a: d024 beq.n 8001966 <HAL_InitTick+0x5e> + { + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / (1000U / (uint32_t)uwTickFreq)) == 0U) + 800191c: f001 fe2c bl 8003578 <HAL_RCC_GetHCLKFreq> + 8001920: 4602 mov r2, r0 + 8001922: 4b14 ldr r3, [pc, #80] @ (8001974 <HAL_InitTick+0x6c>) + 8001924: 781b ldrb r3, [r3, #0] + 8001926: 4619 mov r1, r3 + 8001928: f44f 737a mov.w r3, #1000 @ 0x3e8 + 800192c: fbb3 f3f1 udiv r3, r3, r1 + 8001930: fbb2 f3f3 udiv r3, r2, r3 + 8001934: 4618 mov r0, r3 + 8001936: f000 f9ca bl 8001cce <HAL_SYSTICK_Config> + 800193a: 4603 mov r3, r0 + 800193c: 2b00 cmp r3, #0 + 800193e: d10f bne.n 8001960 <HAL_InitTick+0x58> + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 8001940: 687b ldr r3, [r7, #4] + 8001942: 2b0f cmp r3, #15 + 8001944: d809 bhi.n 800195a <HAL_InitTick+0x52> + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 8001946: 2200 movs r2, #0 + 8001948: 6879 ldr r1, [r7, #4] + 800194a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 800194e: f000 f988 bl 8001c62 <HAL_NVIC_SetPriority> + uwTickPrio = TickPriority; + 8001952: 4a09 ldr r2, [pc, #36] @ (8001978 <HAL_InitTick+0x70>) + 8001954: 687b ldr r3, [r7, #4] + 8001956: 6013 str r3, [r2, #0] + 8001958: e007 b.n 800196a <HAL_InitTick+0x62> + } + else + { + status = HAL_ERROR; + 800195a: 2301 movs r3, #1 + 800195c: 73fb strb r3, [r7, #15] + 800195e: e004 b.n 800196a <HAL_InitTick+0x62> + } + } + else + { + status = HAL_ERROR; + 8001960: 2301 movs r3, #1 + 8001962: 73fb strb r3, [r7, #15] + 8001964: e001 b.n 800196a <HAL_InitTick+0x62> + } + } + else + { + status = HAL_ERROR; + 8001966: 2301 movs r3, #1 + 8001968: 73fb strb r3, [r7, #15] + } + + /* Return function status */ + return status; + 800196a: 7bfb ldrb r3, [r7, #15] +} + 800196c: 4618 mov r0, r3 + 800196e: 3710 adds r7, #16 + 8001970: 46bd mov sp, r7 + 8001972: bd80 pop {r7, pc} + 8001974: 20000010 .word 0x20000010 + 8001978: 2000000c .word 0x2000000c + +0800197c <HAL_IncTick>: + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 800197c: b480 push {r7} + 800197e: af00 add r7, sp, #0 + uwTick += (uint32_t)uwTickFreq; + 8001980: 4b06 ldr r3, [pc, #24] @ (800199c <HAL_IncTick+0x20>) + 8001982: 781b ldrb r3, [r3, #0] + 8001984: 461a mov r2, r3 + 8001986: 4b06 ldr r3, [pc, #24] @ (80019a0 <HAL_IncTick+0x24>) + 8001988: 681b ldr r3, [r3, #0] + 800198a: 4413 add r3, r2 + 800198c: 4a04 ldr r2, [pc, #16] @ (80019a0 <HAL_IncTick+0x24>) + 800198e: 6013 str r3, [r2, #0] +} + 8001990: bf00 nop + 8001992: 46bd mov sp, r7 + 8001994: f85d 7b04 ldr.w r7, [sp], #4 + 8001998: 4770 bx lr + 800199a: bf00 nop + 800199c: 20000010 .word 0x20000010 + 80019a0: 200001f0 .word 0x200001f0 + +080019a4 <HAL_GetTick>: + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 80019a4: b480 push {r7} + 80019a6: af00 add r7, sp, #0 + return uwTick; + 80019a8: 4b03 ldr r3, [pc, #12] @ (80019b8 <HAL_GetTick+0x14>) + 80019aa: 681b ldr r3, [r3, #0] +} + 80019ac: 4618 mov r0, r3 + 80019ae: 46bd mov sp, r7 + 80019b0: f85d 7b04 ldr.w r7, [sp], #4 + 80019b4: 4770 bx lr + 80019b6: bf00 nop + 80019b8: 200001f0 .word 0x200001f0 + +080019bc <HAL_GetTickPrio>: +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + 80019bc: b480 push {r7} + 80019be: af00 add r7, sp, #0 + return uwTickPrio; + 80019c0: 4b03 ldr r3, [pc, #12] @ (80019d0 <HAL_GetTickPrio+0x14>) + 80019c2: 681b ldr r3, [r3, #0] +} + 80019c4: 4618 mov r0, r3 + 80019c6: 46bd mov sp, r7 + 80019c8: f85d 7b04 ldr.w r7, [sp], #4 + 80019cc: 4770 bx lr + 80019ce: bf00 nop + 80019d0: 2000000c .word 0x2000000c + +080019d4 <HAL_GetTickFreq>: + * @brief Return tick frequency. + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + 80019d4: b480 push {r7} + 80019d6: af00 add r7, sp, #0 + return uwTickFreq; + 80019d8: 4b03 ldr r3, [pc, #12] @ (80019e8 <HAL_GetTickFreq+0x14>) + 80019da: 781b ldrb r3, [r3, #0] +} + 80019dc: 4618 mov r0, r3 + 80019de: 46bd mov sp, r7 + 80019e0: f85d 7b04 ldr.w r7, [sp], #4 + 80019e4: 4770 bx lr + 80019e6: bf00 nop + 80019e8: 20000010 .word 0x20000010 + +080019ec <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 80019ec: b480 push {r7} + 80019ee: b085 sub sp, #20 + 80019f0: af00 add r7, sp, #0 + 80019f2: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 80019f4: 687b ldr r3, [r7, #4] + 80019f6: f003 0307 and.w r3, r3, #7 + 80019fa: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 80019fc: 4b0c ldr r3, [pc, #48] @ (8001a30 <__NVIC_SetPriorityGrouping+0x44>) + 80019fe: 68db ldr r3, [r3, #12] + 8001a00: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 8001a02: 68ba ldr r2, [r7, #8] + 8001a04: f64f 03ff movw r3, #63743 @ 0xf8ff + 8001a08: 4013 ands r3, r2 + 8001a0a: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 8001a0c: 68fb ldr r3, [r7, #12] + 8001a0e: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 8001a10: 68bb ldr r3, [r7, #8] + 8001a12: 4313 orrs r3, r2 + reg_value = (reg_value | + 8001a14: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 8001a18: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8001a1c: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 8001a1e: 4a04 ldr r2, [pc, #16] @ (8001a30 <__NVIC_SetPriorityGrouping+0x44>) + 8001a20: 68bb ldr r3, [r7, #8] + 8001a22: 60d3 str r3, [r2, #12] +} + 8001a24: bf00 nop + 8001a26: 3714 adds r7, #20 + 8001a28: 46bd mov sp, r7 + 8001a2a: f85d 7b04 ldr.w r7, [sp], #4 + 8001a2e: 4770 bx lr + 8001a30: e000ed00 .word 0xe000ed00 + +08001a34 <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 8001a34: b480 push {r7} + 8001a36: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8001a38: 4b04 ldr r3, [pc, #16] @ (8001a4c <__NVIC_GetPriorityGrouping+0x18>) + 8001a3a: 68db ldr r3, [r3, #12] + 8001a3c: 0a1b lsrs r3, r3, #8 + 8001a3e: f003 0307 and.w r3, r3, #7 +} + 8001a42: 4618 mov r0, r3 + 8001a44: 46bd mov sp, r7 + 8001a46: f85d 7b04 ldr.w r7, [sp], #4 + 8001a4a: 4770 bx lr + 8001a4c: e000ed00 .word 0xe000ed00 + +08001a50 <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8001a50: b480 push {r7} + 8001a52: b083 sub sp, #12 + 8001a54: af00 add r7, sp, #0 + 8001a56: 4603 mov r3, r0 + 8001a58: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8001a5a: f997 3007 ldrsb.w r3, [r7, #7] + 8001a5e: 2b00 cmp r3, #0 + 8001a60: db0b blt.n 8001a7a <__NVIC_EnableIRQ+0x2a> + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8001a62: 79fb ldrb r3, [r7, #7] + 8001a64: f003 021f and.w r2, r3, #31 + 8001a68: 4907 ldr r1, [pc, #28] @ (8001a88 <__NVIC_EnableIRQ+0x38>) + 8001a6a: f997 3007 ldrsb.w r3, [r7, #7] + 8001a6e: 095b lsrs r3, r3, #5 + 8001a70: 2001 movs r0, #1 + 8001a72: fa00 f202 lsl.w r2, r0, r2 + 8001a76: f841 2023 str.w r2, [r1, r3, lsl #2] + __COMPILER_BARRIER(); + } +} + 8001a7a: bf00 nop + 8001a7c: 370c adds r7, #12 + 8001a7e: 46bd mov sp, r7 + 8001a80: f85d 7b04 ldr.w r7, [sp], #4 + 8001a84: 4770 bx lr + 8001a86: bf00 nop + 8001a88: e000e100 .word 0xe000e100 + +08001a8c <__NVIC_DisableIRQ>: + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + 8001a8c: b480 push {r7} + 8001a8e: b083 sub sp, #12 + 8001a90: af00 add r7, sp, #0 + 8001a92: 4603 mov r3, r0 + 8001a94: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8001a96: f997 3007 ldrsb.w r3, [r7, #7] + 8001a9a: 2b00 cmp r3, #0 + 8001a9c: db12 blt.n 8001ac4 <__NVIC_DisableIRQ+0x38> + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8001a9e: 79fb ldrb r3, [r7, #7] + 8001aa0: f003 021f and.w r2, r3, #31 + 8001aa4: 490a ldr r1, [pc, #40] @ (8001ad0 <__NVIC_DisableIRQ+0x44>) + 8001aa6: f997 3007 ldrsb.w r3, [r7, #7] + 8001aaa: 095b lsrs r3, r3, #5 + 8001aac: 2001 movs r0, #1 + 8001aae: fa00 f202 lsl.w r2, r0, r2 + 8001ab2: 3320 adds r3, #32 + 8001ab4: f841 2023 str.w r2, [r1, r3, lsl #2] + __ASM volatile ("dsb 0xF":::"memory"); + 8001ab8: f3bf 8f4f dsb sy +} + 8001abc: bf00 nop + __ASM volatile ("isb 0xF":::"memory"); + 8001abe: f3bf 8f6f isb sy +} + 8001ac2: bf00 nop + __DSB(); + __ISB(); + } +} + 8001ac4: bf00 nop + 8001ac6: 370c adds r7, #12 + 8001ac8: 46bd mov sp, r7 + 8001aca: f85d 7b04 ldr.w r7, [sp], #4 + 8001ace: 4770 bx lr + 8001ad0: e000e100 .word 0xe000e100 + +08001ad4 <__NVIC_SetPendingIRQ>: + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + 8001ad4: b480 push {r7} + 8001ad6: b083 sub sp, #12 + 8001ad8: af00 add r7, sp, #0 + 8001ada: 4603 mov r3, r0 + 8001adc: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8001ade: f997 3007 ldrsb.w r3, [r7, #7] + 8001ae2: 2b00 cmp r3, #0 + 8001ae4: db0c blt.n 8001b00 <__NVIC_SetPendingIRQ+0x2c> + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8001ae6: 79fb ldrb r3, [r7, #7] + 8001ae8: f003 021f and.w r2, r3, #31 + 8001aec: 4907 ldr r1, [pc, #28] @ (8001b0c <__NVIC_SetPendingIRQ+0x38>) + 8001aee: f997 3007 ldrsb.w r3, [r7, #7] + 8001af2: 095b lsrs r3, r3, #5 + 8001af4: 2001 movs r0, #1 + 8001af6: fa00 f202 lsl.w r2, r0, r2 + 8001afa: 3340 adds r3, #64 @ 0x40 + 8001afc: f841 2023 str.w r2, [r1, r3, lsl #2] + } +} + 8001b00: bf00 nop + 8001b02: 370c adds r7, #12 + 8001b04: 46bd mov sp, r7 + 8001b06: f85d 7b04 ldr.w r7, [sp], #4 + 8001b0a: 4770 bx lr + 8001b0c: e000e100 .word 0xe000e100 + +08001b10 <__NVIC_ClearPendingIRQ>: + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + 8001b10: b480 push {r7} + 8001b12: b083 sub sp, #12 + 8001b14: af00 add r7, sp, #0 + 8001b16: 4603 mov r3, r0 + 8001b18: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8001b1a: f997 3007 ldrsb.w r3, [r7, #7] + 8001b1e: 2b00 cmp r3, #0 + 8001b20: db0c blt.n 8001b3c <__NVIC_ClearPendingIRQ+0x2c> + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8001b22: 79fb ldrb r3, [r7, #7] + 8001b24: f003 021f and.w r2, r3, #31 + 8001b28: 4907 ldr r1, [pc, #28] @ (8001b48 <__NVIC_ClearPendingIRQ+0x38>) + 8001b2a: f997 3007 ldrsb.w r3, [r7, #7] + 8001b2e: 095b lsrs r3, r3, #5 + 8001b30: 2001 movs r0, #1 + 8001b32: fa00 f202 lsl.w r2, r0, r2 + 8001b36: 3360 adds r3, #96 @ 0x60 + 8001b38: f841 2023 str.w r2, [r1, r3, lsl #2] + } +} + 8001b3c: bf00 nop + 8001b3e: 370c adds r7, #12 + 8001b40: 46bd mov sp, r7 + 8001b42: f85d 7b04 ldr.w r7, [sp], #4 + 8001b46: 4770 bx lr + 8001b48: e000e100 .word 0xe000e100 + +08001b4c <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8001b4c: b480 push {r7} + 8001b4e: b083 sub sp, #12 + 8001b50: af00 add r7, sp, #0 + 8001b52: 4603 mov r3, r0 + 8001b54: 6039 str r1, [r7, #0] + 8001b56: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8001b58: f997 3007 ldrsb.w r3, [r7, #7] + 8001b5c: 2b00 cmp r3, #0 + 8001b5e: db0a blt.n 8001b76 <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8001b60: 683b ldr r3, [r7, #0] + 8001b62: b2da uxtb r2, r3 + 8001b64: 490c ldr r1, [pc, #48] @ (8001b98 <__NVIC_SetPriority+0x4c>) + 8001b66: f997 3007 ldrsb.w r3, [r7, #7] + 8001b6a: 0112 lsls r2, r2, #4 + 8001b6c: b2d2 uxtb r2, r2 + 8001b6e: 440b add r3, r1 + 8001b70: f883 2300 strb.w r2, [r3, #768] @ 0x300 + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 8001b74: e00a b.n 8001b8c <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8001b76: 683b ldr r3, [r7, #0] + 8001b78: b2da uxtb r2, r3 + 8001b7a: 4908 ldr r1, [pc, #32] @ (8001b9c <__NVIC_SetPriority+0x50>) + 8001b7c: 79fb ldrb r3, [r7, #7] + 8001b7e: f003 030f and.w r3, r3, #15 + 8001b82: 3b04 subs r3, #4 + 8001b84: 0112 lsls r2, r2, #4 + 8001b86: b2d2 uxtb r2, r2 + 8001b88: 440b add r3, r1 + 8001b8a: 761a strb r2, [r3, #24] +} + 8001b8c: bf00 nop + 8001b8e: 370c adds r7, #12 + 8001b90: 46bd mov sp, r7 + 8001b92: f85d 7b04 ldr.w r7, [sp], #4 + 8001b96: 4770 bx lr + 8001b98: e000e100 .word 0xe000e100 + 8001b9c: e000ed00 .word 0xe000ed00 + +08001ba0 <NVIC_EncodePriority>: + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8001ba0: b480 push {r7} + 8001ba2: b089 sub sp, #36 @ 0x24 + 8001ba4: af00 add r7, sp, #0 + 8001ba6: 60f8 str r0, [r7, #12] + 8001ba8: 60b9 str r1, [r7, #8] + 8001baa: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8001bac: 68fb ldr r3, [r7, #12] + 8001bae: f003 0307 and.w r3, r3, #7 + 8001bb2: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 8001bb4: 69fb ldr r3, [r7, #28] + 8001bb6: f1c3 0307 rsb r3, r3, #7 + 8001bba: 2b04 cmp r3, #4 + 8001bbc: bf28 it cs + 8001bbe: 2304 movcs r3, #4 + 8001bc0: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 8001bc2: 69fb ldr r3, [r7, #28] + 8001bc4: 3304 adds r3, #4 + 8001bc6: 2b06 cmp r3, #6 + 8001bc8: d902 bls.n 8001bd0 <NVIC_EncodePriority+0x30> + 8001bca: 69fb ldr r3, [r7, #28] + 8001bcc: 3b03 subs r3, #3 + 8001bce: e000 b.n 8001bd2 <NVIC_EncodePriority+0x32> + 8001bd0: 2300 movs r3, #0 + 8001bd2: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8001bd4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8001bd8: 69bb ldr r3, [r7, #24] + 8001bda: fa02 f303 lsl.w r3, r2, r3 + 8001bde: 43da mvns r2, r3 + 8001be0: 68bb ldr r3, [r7, #8] + 8001be2: 401a ands r2, r3 + 8001be4: 697b ldr r3, [r7, #20] + 8001be6: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8001be8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 8001bec: 697b ldr r3, [r7, #20] + 8001bee: fa01 f303 lsl.w r3, r1, r3 + 8001bf2: 43d9 mvns r1, r3 + 8001bf4: 687b ldr r3, [r7, #4] + 8001bf6: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8001bf8: 4313 orrs r3, r2 + ); +} + 8001bfa: 4618 mov r0, r3 + 8001bfc: 3724 adds r7, #36 @ 0x24 + 8001bfe: 46bd mov sp, r7 + 8001c00: f85d 7b04 ldr.w r7, [sp], #4 + 8001c04: 4770 bx lr + ... + +08001c08 <SysTick_Config>: + \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the + function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 8001c08: b580 push {r7, lr} + 8001c0a: b082 sub sp, #8 + 8001c0c: af00 add r7, sp, #0 + 8001c0e: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8001c10: 687b ldr r3, [r7, #4] + 8001c12: 3b01 subs r3, #1 + 8001c14: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 8001c18: d301 bcc.n 8001c1e <SysTick_Config+0x16> + { + return (1UL); /* Reload value impossible */ + 8001c1a: 2301 movs r3, #1 + 8001c1c: e00f b.n 8001c3e <SysTick_Config+0x36> + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 8001c1e: 4a0a ldr r2, [pc, #40] @ (8001c48 <SysTick_Config+0x40>) + 8001c20: 687b ldr r3, [r7, #4] + 8001c22: 3b01 subs r3, #1 + 8001c24: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 8001c26: 210f movs r1, #15 + 8001c28: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8001c2c: f7ff ff8e bl 8001b4c <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8001c30: 4b05 ldr r3, [pc, #20] @ (8001c48 <SysTick_Config+0x40>) + 8001c32: 2200 movs r2, #0 + 8001c34: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8001c36: 4b04 ldr r3, [pc, #16] @ (8001c48 <SysTick_Config+0x40>) + 8001c38: 2207 movs r2, #7 + 8001c3a: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 8001c3c: 2300 movs r3, #0 +} + 8001c3e: 4618 mov r0, r3 + 8001c40: 3708 adds r7, #8 + 8001c42: 46bd mov sp, r7 + 8001c44: bd80 pop {r7, pc} + 8001c46: bf00 nop + 8001c48: e000e010 .word 0xe000e010 + +08001c4c <HAL_NVIC_SetPriorityGrouping>: + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8001c4c: b580 push {r7, lr} + 8001c4e: b082 sub sp, #8 + 8001c50: af00 add r7, sp, #0 + 8001c52: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 8001c54: 6878 ldr r0, [r7, #4] + 8001c56: f7ff fec9 bl 80019ec <__NVIC_SetPriorityGrouping> +} + 8001c5a: bf00 nop + 8001c5c: 3708 adds r7, #8 + 8001c5e: 46bd mov sp, r7 + 8001c60: bd80 pop {r7, pc} + +08001c62 <HAL_NVIC_SetPriority>: + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8001c62: b580 push {r7, lr} + 8001c64: b086 sub sp, #24 + 8001c66: af00 add r7, sp, #0 + 8001c68: 4603 mov r3, r0 + 8001c6a: 60b9 str r1, [r7, #8] + 8001c6c: 607a str r2, [r7, #4] + 8001c6e: 73fb strb r3, [r7, #15] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8001c70: f7ff fee0 bl 8001a34 <__NVIC_GetPriorityGrouping> + 8001c74: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 8001c76: 687a ldr r2, [r7, #4] + 8001c78: 68b9 ldr r1, [r7, #8] + 8001c7a: 6978 ldr r0, [r7, #20] + 8001c7c: f7ff ff90 bl 8001ba0 <NVIC_EncodePriority> + 8001c80: 4602 mov r2, r0 + 8001c82: f997 300f ldrsb.w r3, [r7, #15] + 8001c86: 4611 mov r1, r2 + 8001c88: 4618 mov r0, r3 + 8001c8a: f7ff ff5f bl 8001b4c <__NVIC_SetPriority> +} + 8001c8e: bf00 nop + 8001c90: 3718 adds r7, #24 + 8001c92: 46bd mov sp, r7 + 8001c94: bd80 pop {r7, pc} + +08001c96 <HAL_NVIC_EnableIRQ>: + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8001c96: b580 push {r7, lr} + 8001c98: b082 sub sp, #8 + 8001c9a: af00 add r7, sp, #0 + 8001c9c: 4603 mov r3, r0 + 8001c9e: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 8001ca0: f997 3007 ldrsb.w r3, [r7, #7] + 8001ca4: 4618 mov r0, r3 + 8001ca6: f7ff fed3 bl 8001a50 <__NVIC_EnableIRQ> +} + 8001caa: bf00 nop + 8001cac: 3708 adds r7, #8 + 8001cae: 46bd mov sp, r7 + 8001cb0: bd80 pop {r7, pc} + +08001cb2 <HAL_NVIC_DisableIRQ>: + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + 8001cb2: b580 push {r7, lr} + 8001cb4: b082 sub sp, #8 + 8001cb6: af00 add r7, sp, #0 + 8001cb8: 4603 mov r3, r0 + 8001cba: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); + 8001cbc: f997 3007 ldrsb.w r3, [r7, #7] + 8001cc0: 4618 mov r0, r3 + 8001cc2: f7ff fee3 bl 8001a8c <__NVIC_DisableIRQ> +} + 8001cc6: bf00 nop + 8001cc8: 3708 adds r7, #8 + 8001cca: 46bd mov sp, r7 + 8001ccc: bd80 pop {r7, pc} + +08001cce <HAL_SYSTICK_Config>: + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 8001cce: b580 push {r7, lr} + 8001cd0: b082 sub sp, #8 + 8001cd2: af00 add r7, sp, #0 + 8001cd4: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 8001cd6: 6878 ldr r0, [r7, #4] + 8001cd8: f7ff ff96 bl 8001c08 <SysTick_Config> + 8001cdc: 4603 mov r3, r0 +} + 8001cde: 4618 mov r0, r3 + 8001ce0: 3708 adds r7, #8 + 8001ce2: 46bd mov sp, r7 + 8001ce4: bd80 pop {r7, pc} + +08001ce6 <HAL_NVIC_SetPendingIRQ>: + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + 8001ce6: b580 push {r7, lr} + 8001ce8: b082 sub sp, #8 + 8001cea: af00 add r7, sp, #0 + 8001cec: 4603 mov r3, r0 + 8001cee: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); + 8001cf0: f997 3007 ldrsb.w r3, [r7, #7] + 8001cf4: 4618 mov r0, r3 + 8001cf6: f7ff feed bl 8001ad4 <__NVIC_SetPendingIRQ> +} + 8001cfa: bf00 nop + 8001cfc: 3708 adds r7, #8 + 8001cfe: 46bd mov sp, r7 + 8001d00: bd80 pop {r7, pc} + +08001d02 <HAL_NVIC_ClearPendingIRQ>: + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + 8001d02: b580 push {r7, lr} + 8001d04: b082 sub sp, #8 + 8001d06: af00 add r7, sp, #0 + 8001d08: 4603 mov r3, r0 + 8001d0a: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); + 8001d0c: f997 3007 ldrsb.w r3, [r7, #7] + 8001d10: 4618 mov r0, r3 + 8001d12: f7ff fefd bl 8001b10 <__NVIC_ClearPendingIRQ> +} + 8001d16: bf00 nop + 8001d18: 3708 adds r7, #8 + 8001d1a: 46bd mov sp, r7 + 8001d1c: bd80 pop {r7, pc} + ... + +08001d20 <HAL_GPIO_Init>: + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 8001d20: b480 push {r7} + 8001d22: b087 sub sp, #28 + 8001d24: af00 add r7, sp, #0 + 8001d26: 6078 str r0, [r7, #4] + 8001d28: 6039 str r1, [r7, #0] + uint32_t position = 0x00u; + 8001d2a: 2300 movs r3, #0 + 8001d2c: 617b str r3, [r7, #20] + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00u) + 8001d2e: e14c b.n 8001fca <HAL_GPIO_Init+0x2aa> + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1uL << position); + 8001d30: 683b ldr r3, [r7, #0] + 8001d32: 681a ldr r2, [r3, #0] + 8001d34: 2101 movs r1, #1 + 8001d36: 697b ldr r3, [r7, #20] + 8001d38: fa01 f303 lsl.w r3, r1, r3 + 8001d3c: 4013 ands r3, r2 + 8001d3e: 60fb str r3, [r7, #12] + + if (iocurrent != 0x00u) + 8001d40: 68fb ldr r3, [r7, #12] + 8001d42: 2b00 cmp r3, #0 + 8001d44: f000 813e beq.w 8001fc4 <HAL_GPIO_Init+0x2a4> + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + 8001d48: 683b ldr r3, [r7, #0] + 8001d4a: 685b ldr r3, [r3, #4] + 8001d4c: f003 0303 and.w r3, r3, #3 + 8001d50: 2b01 cmp r3, #1 + 8001d52: d005 beq.n 8001d60 <HAL_GPIO_Init+0x40> + 8001d54: 683b ldr r3, [r7, #0] + 8001d56: 685b ldr r3, [r3, #4] + 8001d58: f003 0303 and.w r3, r3, #3 + 8001d5c: 2b02 cmp r3, #2 + 8001d5e: d130 bne.n 8001dc2 <HAL_GPIO_Init+0xa2> + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 8001d60: 687b ldr r3, [r7, #4] + 8001d62: 689b ldr r3, [r3, #8] + 8001d64: 613b str r3, [r7, #16] + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); + 8001d66: 697b ldr r3, [r7, #20] + 8001d68: 005b lsls r3, r3, #1 + 8001d6a: 2203 movs r2, #3 + 8001d6c: fa02 f303 lsl.w r3, r2, r3 + 8001d70: 43db mvns r3, r3 + 8001d72: 693a ldr r2, [r7, #16] + 8001d74: 4013 ands r3, r2 + 8001d76: 613b str r3, [r7, #16] + temp |= (GPIO_Init->Speed << (position * 2u)); + 8001d78: 683b ldr r3, [r7, #0] + 8001d7a: 68da ldr r2, [r3, #12] + 8001d7c: 697b ldr r3, [r7, #20] + 8001d7e: 005b lsls r3, r3, #1 + 8001d80: fa02 f303 lsl.w r3, r2, r3 + 8001d84: 693a ldr r2, [r7, #16] + 8001d86: 4313 orrs r3, r2 + 8001d88: 613b str r3, [r7, #16] + GPIOx->OSPEEDR = temp; + 8001d8a: 687b ldr r3, [r7, #4] + 8001d8c: 693a ldr r2, [r7, #16] + 8001d8e: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 8001d90: 687b ldr r3, [r7, #4] + 8001d92: 685b ldr r3, [r3, #4] + 8001d94: 613b str r3, [r7, #16] + temp &= ~(GPIO_OTYPER_OT0 << position) ; + 8001d96: 2201 movs r2, #1 + 8001d98: 697b ldr r3, [r7, #20] + 8001d9a: fa02 f303 lsl.w r3, r2, r3 + 8001d9e: 43db mvns r3, r3 + 8001da0: 693a ldr r2, [r7, #16] + 8001da2: 4013 ands r3, r2 + 8001da4: 613b str r3, [r7, #16] + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 8001da6: 683b ldr r3, [r7, #0] + 8001da8: 685b ldr r3, [r3, #4] + 8001daa: 091b lsrs r3, r3, #4 + 8001dac: f003 0201 and.w r2, r3, #1 + 8001db0: 697b ldr r3, [r7, #20] + 8001db2: fa02 f303 lsl.w r3, r2, r3 + 8001db6: 693a ldr r2, [r7, #16] + 8001db8: 4313 orrs r3, r2 + 8001dba: 613b str r3, [r7, #16] + GPIOx->OTYPER = temp; + 8001dbc: 687b ldr r3, [r7, #4] + 8001dbe: 693a ldr r2, [r7, #16] + 8001dc0: 605a str r2, [r3, #4] + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 8001dc2: 683b ldr r3, [r7, #0] + 8001dc4: 685b ldr r3, [r3, #4] + 8001dc6: f003 0303 and.w r3, r3, #3 + 8001dca: 2b03 cmp r3, #3 + 8001dcc: d017 beq.n 8001dfe <HAL_GPIO_Init+0xde> + { + temp = GPIOx->PUPDR; + 8001dce: 687b ldr r3, [r7, #4] + 8001dd0: 68db ldr r3, [r3, #12] + 8001dd2: 613b str r3, [r7, #16] + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + 8001dd4: 697b ldr r3, [r7, #20] + 8001dd6: 005b lsls r3, r3, #1 + 8001dd8: 2203 movs r2, #3 + 8001dda: fa02 f303 lsl.w r3, r2, r3 + 8001dde: 43db mvns r3, r3 + 8001de0: 693a ldr r2, [r7, #16] + 8001de2: 4013 ands r3, r2 + 8001de4: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Pull) << (position * 2U)); + 8001de6: 683b ldr r3, [r7, #0] + 8001de8: 689a ldr r2, [r3, #8] + 8001dea: 697b ldr r3, [r7, #20] + 8001dec: 005b lsls r3, r3, #1 + 8001dee: fa02 f303 lsl.w r3, r2, r3 + 8001df2: 693a ldr r2, [r7, #16] + 8001df4: 4313 orrs r3, r2 + 8001df6: 613b str r3, [r7, #16] + GPIOx->PUPDR = temp; + 8001df8: 687b ldr r3, [r7, #4] + 8001dfa: 693a ldr r2, [r7, #16] + 8001dfc: 60da str r2, [r3, #12] + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 8001dfe: 683b ldr r3, [r7, #0] + 8001e00: 685b ldr r3, [r3, #4] + 8001e02: f003 0303 and.w r3, r3, #3 + 8001e06: 2b02 cmp r3, #2 + 8001e08: d123 bne.n 8001e52 <HAL_GPIO_Init+0x132> + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3u]; + 8001e0a: 697b ldr r3, [r7, #20] + 8001e0c: 08da lsrs r2, r3, #3 + 8001e0e: 687b ldr r3, [r7, #4] + 8001e10: 3208 adds r2, #8 + 8001e12: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8001e16: 613b str r3, [r7, #16] + temp &= ~(0xFu << ((position & 0x07u) * 4u)); + 8001e18: 697b ldr r3, [r7, #20] + 8001e1a: f003 0307 and.w r3, r3, #7 + 8001e1e: 009b lsls r3, r3, #2 + 8001e20: 220f movs r2, #15 + 8001e22: fa02 f303 lsl.w r3, r2, r3 + 8001e26: 43db mvns r3, r3 + 8001e28: 693a ldr r2, [r7, #16] + 8001e2a: 4013 ands r3, r2 + 8001e2c: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); + 8001e2e: 683b ldr r3, [r7, #0] + 8001e30: 691a ldr r2, [r3, #16] + 8001e32: 697b ldr r3, [r7, #20] + 8001e34: f003 0307 and.w r3, r3, #7 + 8001e38: 009b lsls r3, r3, #2 + 8001e3a: fa02 f303 lsl.w r3, r2, r3 + 8001e3e: 693a ldr r2, [r7, #16] + 8001e40: 4313 orrs r3, r2 + 8001e42: 613b str r3, [r7, #16] + GPIOx->AFR[position >> 3u] = temp; + 8001e44: 697b ldr r3, [r7, #20] + 8001e46: 08da lsrs r2, r3, #3 + 8001e48: 687b ldr r3, [r7, #4] + 8001e4a: 3208 adds r2, #8 + 8001e4c: 6939 ldr r1, [r7, #16] + 8001e4e: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 8001e52: 687b ldr r3, [r7, #4] + 8001e54: 681b ldr r3, [r3, #0] + 8001e56: 613b str r3, [r7, #16] + temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); + 8001e58: 697b ldr r3, [r7, #20] + 8001e5a: 005b lsls r3, r3, #1 + 8001e5c: 2203 movs r2, #3 + 8001e5e: fa02 f303 lsl.w r3, r2, r3 + 8001e62: 43db mvns r3, r3 + 8001e64: 693a ldr r2, [r7, #16] + 8001e66: 4013 ands r3, r2 + 8001e68: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + 8001e6a: 683b ldr r3, [r7, #0] + 8001e6c: 685b ldr r3, [r3, #4] + 8001e6e: f003 0203 and.w r2, r3, #3 + 8001e72: 697b ldr r3, [r7, #20] + 8001e74: 005b lsls r3, r3, #1 + 8001e76: fa02 f303 lsl.w r3, r2, r3 + 8001e7a: 693a ldr r2, [r7, #16] + 8001e7c: 4313 orrs r3, r2 + 8001e7e: 613b str r3, [r7, #16] + GPIOx->MODER = temp; + 8001e80: 687b ldr r3, [r7, #4] + 8001e82: 693a ldr r2, [r7, #16] + 8001e84: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + 8001e86: 683b ldr r3, [r7, #0] + 8001e88: 685b ldr r3, [r3, #4] + 8001e8a: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 8001e8e: 2b00 cmp r3, #0 + 8001e90: f000 8098 beq.w 8001fc4 <HAL_GPIO_Init+0x2a4> + { + temp = SYSCFG->EXTICR[position >> 2u]; + 8001e94: 4a54 ldr r2, [pc, #336] @ (8001fe8 <HAL_GPIO_Init+0x2c8>) + 8001e96: 697b ldr r3, [r7, #20] + 8001e98: 089b lsrs r3, r3, #2 + 8001e9a: 3302 adds r3, #2 + 8001e9c: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8001ea0: 613b str r3, [r7, #16] + temp &= ~(0x0FuL << (4u * (position & 0x03u))); + 8001ea2: 697b ldr r3, [r7, #20] + 8001ea4: f003 0303 and.w r3, r3, #3 + 8001ea8: 009b lsls r3, r3, #2 + 8001eaa: 220f movs r2, #15 + 8001eac: fa02 f303 lsl.w r3, r2, r3 + 8001eb0: 43db mvns r3, r3 + 8001eb2: 693a ldr r2, [r7, #16] + 8001eb4: 4013 ands r3, r2 + 8001eb6: 613b str r3, [r7, #16] + temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); + 8001eb8: 687b ldr r3, [r7, #4] + 8001eba: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 + 8001ebe: d019 beq.n 8001ef4 <HAL_GPIO_Init+0x1d4> + 8001ec0: 687b ldr r3, [r7, #4] + 8001ec2: 4a4a ldr r2, [pc, #296] @ (8001fec <HAL_GPIO_Init+0x2cc>) + 8001ec4: 4293 cmp r3, r2 + 8001ec6: d013 beq.n 8001ef0 <HAL_GPIO_Init+0x1d0> + 8001ec8: 687b ldr r3, [r7, #4] + 8001eca: 4a49 ldr r2, [pc, #292] @ (8001ff0 <HAL_GPIO_Init+0x2d0>) + 8001ecc: 4293 cmp r3, r2 + 8001ece: d00d beq.n 8001eec <HAL_GPIO_Init+0x1cc> + 8001ed0: 687b ldr r3, [r7, #4] + 8001ed2: 4a48 ldr r2, [pc, #288] @ (8001ff4 <HAL_GPIO_Init+0x2d4>) + 8001ed4: 4293 cmp r3, r2 + 8001ed6: d007 beq.n 8001ee8 <HAL_GPIO_Init+0x1c8> + 8001ed8: 687b ldr r3, [r7, #4] + 8001eda: 4a47 ldr r2, [pc, #284] @ (8001ff8 <HAL_GPIO_Init+0x2d8>) + 8001edc: 4293 cmp r3, r2 + 8001ede: d101 bne.n 8001ee4 <HAL_GPIO_Init+0x1c4> + 8001ee0: 2304 movs r3, #4 + 8001ee2: e008 b.n 8001ef6 <HAL_GPIO_Init+0x1d6> + 8001ee4: 2307 movs r3, #7 + 8001ee6: e006 b.n 8001ef6 <HAL_GPIO_Init+0x1d6> + 8001ee8: 2303 movs r3, #3 + 8001eea: e004 b.n 8001ef6 <HAL_GPIO_Init+0x1d6> + 8001eec: 2302 movs r3, #2 + 8001eee: e002 b.n 8001ef6 <HAL_GPIO_Init+0x1d6> + 8001ef0: 2301 movs r3, #1 + 8001ef2: e000 b.n 8001ef6 <HAL_GPIO_Init+0x1d6> + 8001ef4: 2300 movs r3, #0 + 8001ef6: 697a ldr r2, [r7, #20] + 8001ef8: f002 0203 and.w r2, r2, #3 + 8001efc: 0092 lsls r2, r2, #2 + 8001efe: 4093 lsls r3, r2 + 8001f00: 693a ldr r2, [r7, #16] + 8001f02: 4313 orrs r3, r2 + 8001f04: 613b str r3, [r7, #16] + SYSCFG->EXTICR[position >> 2u] = temp; + 8001f06: 4938 ldr r1, [pc, #224] @ (8001fe8 <HAL_GPIO_Init+0x2c8>) + 8001f08: 697b ldr r3, [r7, #20] + 8001f0a: 089b lsrs r3, r3, #2 + 8001f0c: 3302 adds r3, #2 + 8001f0e: 693a ldr r2, [r7, #16] + 8001f10: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR1; + 8001f14: 4b39 ldr r3, [pc, #228] @ (8001ffc <HAL_GPIO_Init+0x2dc>) + 8001f16: 681b ldr r3, [r3, #0] + 8001f18: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 8001f1a: 68fb ldr r3, [r7, #12] + 8001f1c: 43db mvns r3, r3 + 8001f1e: 693a ldr r2, [r7, #16] + 8001f20: 4013 ands r3, r2 + 8001f22: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + 8001f24: 683b ldr r3, [r7, #0] + 8001f26: 685b ldr r3, [r3, #4] + 8001f28: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8001f2c: 2b00 cmp r3, #0 + 8001f2e: d003 beq.n 8001f38 <HAL_GPIO_Init+0x218> + { + temp |= iocurrent; + 8001f30: 693a ldr r2, [r7, #16] + 8001f32: 68fb ldr r3, [r7, #12] + 8001f34: 4313 orrs r3, r2 + 8001f36: 613b str r3, [r7, #16] + } + EXTI->RTSR1 = temp; + 8001f38: 4a30 ldr r2, [pc, #192] @ (8001ffc <HAL_GPIO_Init+0x2dc>) + 8001f3a: 693b ldr r3, [r7, #16] + 8001f3c: 6013 str r3, [r2, #0] + + temp = EXTI->FTSR1; + 8001f3e: 4b2f ldr r3, [pc, #188] @ (8001ffc <HAL_GPIO_Init+0x2dc>) + 8001f40: 685b ldr r3, [r3, #4] + 8001f42: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 8001f44: 68fb ldr r3, [r7, #12] + 8001f46: 43db mvns r3, r3 + 8001f48: 693a ldr r2, [r7, #16] + 8001f4a: 4013 ands r3, r2 + 8001f4c: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + 8001f4e: 683b ldr r3, [r7, #0] + 8001f50: 685b ldr r3, [r3, #4] + 8001f52: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 8001f56: 2b00 cmp r3, #0 + 8001f58: d003 beq.n 8001f62 <HAL_GPIO_Init+0x242> + { + temp |= iocurrent; + 8001f5a: 693a ldr r2, [r7, #16] + 8001f5c: 68fb ldr r3, [r7, #12] + 8001f5e: 4313 orrs r3, r2 + 8001f60: 613b str r3, [r7, #16] + } + EXTI->FTSR1 = temp; + 8001f62: 4a26 ldr r2, [pc, #152] @ (8001ffc <HAL_GPIO_Init+0x2dc>) + 8001f64: 693b ldr r3, [r7, #16] + 8001f66: 6053 str r3, [r2, #4] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR1; + 8001f68: 4b24 ldr r3, [pc, #144] @ (8001ffc <HAL_GPIO_Init+0x2dc>) + 8001f6a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 8001f6e: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 8001f70: 68fb ldr r3, [r7, #12] + 8001f72: 43db mvns r3, r3 + 8001f74: 693a ldr r2, [r7, #16] + 8001f76: 4013 ands r3, r2 + 8001f78: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) + 8001f7a: 683b ldr r3, [r7, #0] + 8001f7c: 685b ldr r3, [r3, #4] + 8001f7e: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8001f82: 2b00 cmp r3, #0 + 8001f84: d003 beq.n 8001f8e <HAL_GPIO_Init+0x26e> + { + temp |= iocurrent; + 8001f86: 693a ldr r2, [r7, #16] + 8001f88: 68fb ldr r3, [r7, #12] + 8001f8a: 4313 orrs r3, r2 + 8001f8c: 613b str r3, [r7, #16] + } + EXTI->IMR1 = temp; + 8001f8e: 4a1b ldr r2, [pc, #108] @ (8001ffc <HAL_GPIO_Init+0x2dc>) + 8001f90: 693b ldr r3, [r7, #16] + 8001f92: f8c2 3080 str.w r3, [r2, #128] @ 0x80 + + temp = EXTI->EMR1; + 8001f96: 4b19 ldr r3, [pc, #100] @ (8001ffc <HAL_GPIO_Init+0x2dc>) + 8001f98: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 + 8001f9c: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 8001f9e: 68fb ldr r3, [r7, #12] + 8001fa0: 43db mvns r3, r3 + 8001fa2: 693a ldr r2, [r7, #16] + 8001fa4: 4013 ands r3, r2 + 8001fa6: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) + 8001fa8: 683b ldr r3, [r7, #0] + 8001faa: 685b ldr r3, [r3, #4] + 8001fac: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001fb0: 2b00 cmp r3, #0 + 8001fb2: d003 beq.n 8001fbc <HAL_GPIO_Init+0x29c> + { + temp |= iocurrent; + 8001fb4: 693a ldr r2, [r7, #16] + 8001fb6: 68fb ldr r3, [r7, #12] + 8001fb8: 4313 orrs r3, r2 + 8001fba: 613b str r3, [r7, #16] + } + EXTI->EMR1 = temp; + 8001fbc: 4a0f ldr r2, [pc, #60] @ (8001ffc <HAL_GPIO_Init+0x2dc>) + 8001fbe: 693b ldr r3, [r7, #16] + 8001fc0: f8c2 3084 str.w r3, [r2, #132] @ 0x84 + } + } + + position++; + 8001fc4: 697b ldr r3, [r7, #20] + 8001fc6: 3301 adds r3, #1 + 8001fc8: 617b str r3, [r7, #20] + while (((GPIO_Init->Pin) >> position) != 0x00u) + 8001fca: 683b ldr r3, [r7, #0] + 8001fcc: 681a ldr r2, [r3, #0] + 8001fce: 697b ldr r3, [r7, #20] + 8001fd0: fa22 f303 lsr.w r3, r2, r3 + 8001fd4: 2b00 cmp r3, #0 + 8001fd6: f47f aeab bne.w 8001d30 <HAL_GPIO_Init+0x10> + } +} + 8001fda: bf00 nop + 8001fdc: bf00 nop + 8001fde: 371c adds r7, #28 + 8001fe0: 46bd mov sp, r7 + 8001fe2: f85d 7b04 ldr.w r7, [sp], #4 + 8001fe6: 4770 bx lr + 8001fe8: 40010000 .word 0x40010000 + 8001fec: 48000400 .word 0x48000400 + 8001ff0: 48000800 .word 0x48000800 + 8001ff4: 48000c00 .word 0x48000c00 + 8001ff8: 48001000 .word 0x48001000 + 8001ffc: 58000800 .word 0x58000800 + +08002000 <HAL_GPIO_WritePin>: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 8002000: b480 push {r7} + 8002002: b083 sub sp, #12 + 8002004: af00 add r7, sp, #0 + 8002006: 6078 str r0, [r7, #4] + 8002008: 460b mov r3, r1 + 800200a: 807b strh r3, [r7, #2] + 800200c: 4613 mov r3, r2 + 800200e: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 8002010: 787b ldrb r3, [r7, #1] + 8002012: 2b00 cmp r3, #0 + 8002014: d003 beq.n 800201e <HAL_GPIO_WritePin+0x1e> + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + 8002016: 887a ldrh r2, [r7, #2] + 8002018: 687b ldr r3, [r7, #4] + 800201a: 619a str r2, [r3, #24] + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + 800201c: e002 b.n 8002024 <HAL_GPIO_WritePin+0x24> + GPIOx->BRR = (uint32_t)GPIO_Pin; + 800201e: 887a ldrh r2, [r7, #2] + 8002020: 687b ldr r3, [r7, #4] + 8002022: 629a str r2, [r3, #40] @ 0x28 +} + 8002024: bf00 nop + 8002026: 370c adds r7, #12 + 8002028: 46bd mov sp, r7 + 800202a: f85d 7b04 ldr.w r7, [sp], #4 + 800202e: 4770 bx lr + +08002030 <HAL_HSEM_IRQHandler>: +/** + * @brief This function handles HSEM interrupt request + * @retval None + */ +void HAL_HSEM_IRQHandler(void) +{ + 8002030: b580 push {r7, lr} + 8002032: b082 sub sp, #8 + 8002034: af00 add r7, sp, #0 + uint32_t statusreg; + /* Get the list of masked freed semaphores*/ + statusreg = HSEM_COMMON->MISR; + 8002036: 4b0a ldr r3, [pc, #40] @ (8002060 <HAL_HSEM_IRQHandler+0x30>) + 8002038: 68db ldr r3, [r3, #12] + 800203a: 607b str r3, [r7, #4] + + /*Disable Interrupts*/ + HSEM_COMMON->IER &= ~((uint32_t)statusreg); + 800203c: 4b08 ldr r3, [pc, #32] @ (8002060 <HAL_HSEM_IRQHandler+0x30>) + 800203e: 681a ldr r2, [r3, #0] + 8002040: 687b ldr r3, [r7, #4] + 8002042: 43db mvns r3, r3 + 8002044: 4906 ldr r1, [pc, #24] @ (8002060 <HAL_HSEM_IRQHandler+0x30>) + 8002046: 4013 ands r3, r2 + 8002048: 600b str r3, [r1, #0] + + /*Clear Flags*/ + HSEM_COMMON->ICR = ((uint32_t)statusreg); + 800204a: 4a05 ldr r2, [pc, #20] @ (8002060 <HAL_HSEM_IRQHandler+0x30>) + 800204c: 687b ldr r3, [r7, #4] + 800204e: 6053 str r3, [r2, #4] + + /* Call FreeCallback */ + HAL_HSEM_FreeCallback(statusreg); + 8002050: 6878 ldr r0, [r7, #4] + 8002052: f000 f807 bl 8002064 <HAL_HSEM_FreeCallback> +} + 8002056: bf00 nop + 8002058: 3708 adds r7, #8 + 800205a: 46bd mov sp, r7 + 800205c: bd80 pop {r7, pc} + 800205e: bf00 nop + 8002060: 58001500 .word 0x58001500 + +08002064 <HAL_HSEM_FreeCallback>: + * @brief Semaphore Released Callback. + * @param SemMask: Mask of Released semaphores + * @retval None + */ +__weak void HAL_HSEM_FreeCallback(uint32_t SemMask) +{ + 8002064: b480 push {r7} + 8002066: b083 sub sp, #12 + 8002068: af00 add r7, sp, #0 + 800206a: 6078 str r0, [r7, #4] + UNUSED(SemMask); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HSEM_FreeCallback can be implemented in the user file + */ +} + 800206c: bf00 nop + 800206e: 370c adds r7, #12 + 8002070: 46bd mov sp, r7 + 8002072: f85d 7b04 ldr.w r7, [sp], #4 + 8002076: 4770 bx lr + +08002078 <HAL_I2C_Init>: + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + 8002078: b580 push {r7, lr} + 800207a: b082 sub sp, #8 + 800207c: af00 add r7, sp, #0 + 800207e: 6078 str r0, [r7, #4] + /* Check the I2C handle allocation */ + if (hi2c == NULL) + 8002080: 687b ldr r3, [r7, #4] + 8002082: 2b00 cmp r3, #0 + 8002084: d101 bne.n 800208a <HAL_I2C_Init+0x12> + { + return HAL_ERROR; + 8002086: 2301 movs r3, #1 + 8002088: e08d b.n 80021a6 <HAL_I2C_Init+0x12e> + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + 800208a: 687b ldr r3, [r7, #4] + 800208c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 + 8002090: b2db uxtb r3, r3 + 8002092: 2b00 cmp r3, #0 + 8002094: d106 bne.n 80020a4 <HAL_I2C_Init+0x2c> + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + 8002096: 687b ldr r3, [r7, #4] + 8002098: 2200 movs r2, #0 + 800209a: f883 2040 strb.w r2, [r3, #64] @ 0x40 + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); + 800209e: 6878 ldr r0, [r7, #4] + 80020a0: f7ff faae bl 8001600 <HAL_I2C_MspInit> +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + 80020a4: 687b ldr r3, [r7, #4] + 80020a6: 2224 movs r2, #36 @ 0x24 + 80020a8: f883 2041 strb.w r2, [r3, #65] @ 0x41 + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + 80020ac: 687b ldr r3, [r7, #4] + 80020ae: 681b ldr r3, [r3, #0] + 80020b0: 681a ldr r2, [r3, #0] + 80020b2: 687b ldr r3, [r7, #4] + 80020b4: 681b ldr r3, [r3, #0] + 80020b6: f022 0201 bic.w r2, r2, #1 + 80020ba: 601a str r2, [r3, #0] + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + 80020bc: 687b ldr r3, [r7, #4] + 80020be: 685a ldr r2, [r3, #4] + 80020c0: 687b ldr r3, [r7, #4] + 80020c2: 681b ldr r3, [r3, #0] + 80020c4: f022 6270 bic.w r2, r2, #251658240 @ 0xf000000 + 80020c8: 611a str r2, [r3, #16] + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + 80020ca: 687b ldr r3, [r7, #4] + 80020cc: 681b ldr r3, [r3, #0] + 80020ce: 689a ldr r2, [r3, #8] + 80020d0: 687b ldr r3, [r7, #4] + 80020d2: 681b ldr r3, [r3, #0] + 80020d4: f422 4200 bic.w r2, r2, #32768 @ 0x8000 + 80020d8: 609a str r2, [r3, #8] + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + 80020da: 687b ldr r3, [r7, #4] + 80020dc: 68db ldr r3, [r3, #12] + 80020de: 2b01 cmp r3, #1 + 80020e0: d107 bne.n 80020f2 <HAL_I2C_Init+0x7a> + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + 80020e2: 687b ldr r3, [r7, #4] + 80020e4: 689a ldr r2, [r3, #8] + 80020e6: 687b ldr r3, [r7, #4] + 80020e8: 681b ldr r3, [r3, #0] + 80020ea: f442 4200 orr.w r2, r2, #32768 @ 0x8000 + 80020ee: 609a str r2, [r3, #8] + 80020f0: e006 b.n 8002100 <HAL_I2C_Init+0x88> + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + 80020f2: 687b ldr r3, [r7, #4] + 80020f4: 689a ldr r2, [r3, #8] + 80020f6: 687b ldr r3, [r7, #4] + 80020f8: 681b ldr r3, [r3, #0] + 80020fa: f442 4204 orr.w r2, r2, #33792 @ 0x8400 + 80020fe: 609a str r2, [r3, #8] + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + 8002100: 687b ldr r3, [r7, #4] + 8002102: 68db ldr r3, [r3, #12] + 8002104: 2b02 cmp r3, #2 + 8002106: d108 bne.n 800211a <HAL_I2C_Init+0xa2> + { + SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + 8002108: 687b ldr r3, [r7, #4] + 800210a: 681b ldr r3, [r3, #0] + 800210c: 685a ldr r2, [r3, #4] + 800210e: 687b ldr r3, [r7, #4] + 8002110: 681b ldr r3, [r3, #0] + 8002112: f442 6200 orr.w r2, r2, #2048 @ 0x800 + 8002116: 605a str r2, [r3, #4] + 8002118: e007 b.n 800212a <HAL_I2C_Init+0xb2> + } + else + { + /* Clear the I2C ADD10 bit */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + 800211a: 687b ldr r3, [r7, #4] + 800211c: 681b ldr r3, [r3, #0] + 800211e: 685a ldr r2, [r3, #4] + 8002120: 687b ldr r3, [r7, #4] + 8002122: 681b ldr r3, [r3, #0] + 8002124: f422 6200 bic.w r2, r2, #2048 @ 0x800 + 8002128: 605a str r2, [r3, #4] + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + 800212a: 687b ldr r3, [r7, #4] + 800212c: 681b ldr r3, [r3, #0] + 800212e: 685b ldr r3, [r3, #4] + 8002130: 687a ldr r2, [r7, #4] + 8002132: 6812 ldr r2, [r2, #0] + 8002134: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 + 8002138: f443 4300 orr.w r3, r3, #32768 @ 0x8000 + 800213c: 6053 str r3, [r2, #4] + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + 800213e: 687b ldr r3, [r7, #4] + 8002140: 681b ldr r3, [r3, #0] + 8002142: 68da ldr r2, [r3, #12] + 8002144: 687b ldr r3, [r7, #4] + 8002146: 681b ldr r3, [r3, #0] + 8002148: f422 4200 bic.w r2, r2, #32768 @ 0x8000 + 800214c: 60da str r2, [r3, #12] + + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + 800214e: 687b ldr r3, [r7, #4] + 8002150: 691a ldr r2, [r3, #16] + 8002152: 687b ldr r3, [r7, #4] + 8002154: 695b ldr r3, [r3, #20] + 8002156: ea42 0103 orr.w r1, r2, r3 + (hi2c->Init.OwnAddress2Masks << 8)); + 800215a: 687b ldr r3, [r7, #4] + 800215c: 699b ldr r3, [r3, #24] + 800215e: 021a lsls r2, r3, #8 + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + 8002160: 687b ldr r3, [r7, #4] + 8002162: 681b ldr r3, [r3, #0] + 8002164: 430a orrs r2, r1 + 8002166: 60da str r2, [r3, #12] + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + 8002168: 687b ldr r3, [r7, #4] + 800216a: 69d9 ldr r1, [r3, #28] + 800216c: 687b ldr r3, [r7, #4] + 800216e: 6a1a ldr r2, [r3, #32] + 8002170: 687b ldr r3, [r7, #4] + 8002172: 681b ldr r3, [r3, #0] + 8002174: 430a orrs r2, r1 + 8002176: 601a str r2, [r3, #0] + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + 8002178: 687b ldr r3, [r7, #4] + 800217a: 681b ldr r3, [r3, #0] + 800217c: 681a ldr r2, [r3, #0] + 800217e: 687b ldr r3, [r7, #4] + 8002180: 681b ldr r3, [r3, #0] + 8002182: f042 0201 orr.w r2, r2, #1 + 8002186: 601a str r2, [r3, #0] + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8002188: 687b ldr r3, [r7, #4] + 800218a: 2200 movs r2, #0 + 800218c: 645a str r2, [r3, #68] @ 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 800218e: 687b ldr r3, [r7, #4] + 8002190: 2220 movs r2, #32 + 8002192: f883 2041 strb.w r2, [r3, #65] @ 0x41 + hi2c->PreviousState = I2C_STATE_NONE; + 8002196: 687b ldr r3, [r7, #4] + 8002198: 2200 movs r2, #0 + 800219a: 631a str r2, [r3, #48] @ 0x30 + hi2c->Mode = HAL_I2C_MODE_NONE; + 800219c: 687b ldr r3, [r7, #4] + 800219e: 2200 movs r2, #0 + 80021a0: f883 2042 strb.w r2, [r3, #66] @ 0x42 + + return HAL_OK; + 80021a4: 2300 movs r3, #0 +} + 80021a6: 4618 mov r0, r3 + 80021a8: 3708 adds r7, #8 + 80021aa: 46bd mov sp, r7 + 80021ac: bd80 pop {r7, pc} + +080021ae <HAL_I2CEx_ConfigAnalogFilter>: + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + 80021ae: b480 push {r7} + 80021b0: b083 sub sp, #12 + 80021b2: af00 add r7, sp, #0 + 80021b4: 6078 str r0, [r7, #4] + 80021b6: 6039 str r1, [r7, #0] + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + 80021b8: 687b ldr r3, [r7, #4] + 80021ba: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 + 80021be: b2db uxtb r3, r3 + 80021c0: 2b20 cmp r3, #32 + 80021c2: d138 bne.n 8002236 <HAL_I2CEx_ConfigAnalogFilter+0x88> + { + /* Process Locked */ + __HAL_LOCK(hi2c); + 80021c4: 687b ldr r3, [r7, #4] + 80021c6: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 + 80021ca: 2b01 cmp r3, #1 + 80021cc: d101 bne.n 80021d2 <HAL_I2CEx_ConfigAnalogFilter+0x24> + 80021ce: 2302 movs r3, #2 + 80021d0: e032 b.n 8002238 <HAL_I2CEx_ConfigAnalogFilter+0x8a> + 80021d2: 687b ldr r3, [r7, #4] + 80021d4: 2201 movs r2, #1 + 80021d6: f883 2040 strb.w r2, [r3, #64] @ 0x40 + + hi2c->State = HAL_I2C_STATE_BUSY; + 80021da: 687b ldr r3, [r7, #4] + 80021dc: 2224 movs r2, #36 @ 0x24 + 80021de: f883 2041 strb.w r2, [r3, #65] @ 0x41 + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + 80021e2: 687b ldr r3, [r7, #4] + 80021e4: 681b ldr r3, [r3, #0] + 80021e6: 681a ldr r2, [r3, #0] + 80021e8: 687b ldr r3, [r7, #4] + 80021ea: 681b ldr r3, [r3, #0] + 80021ec: f022 0201 bic.w r2, r2, #1 + 80021f0: 601a str r2, [r3, #0] + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + 80021f2: 687b ldr r3, [r7, #4] + 80021f4: 681b ldr r3, [r3, #0] + 80021f6: 681a ldr r2, [r3, #0] + 80021f8: 687b ldr r3, [r7, #4] + 80021fa: 681b ldr r3, [r3, #0] + 80021fc: f422 5280 bic.w r2, r2, #4096 @ 0x1000 + 8002200: 601a str r2, [r3, #0] + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + 8002202: 687b ldr r3, [r7, #4] + 8002204: 681b ldr r3, [r3, #0] + 8002206: 6819 ldr r1, [r3, #0] + 8002208: 687b ldr r3, [r7, #4] + 800220a: 681b ldr r3, [r3, #0] + 800220c: 683a ldr r2, [r7, #0] + 800220e: 430a orrs r2, r1 + 8002210: 601a str r2, [r3, #0] + + __HAL_I2C_ENABLE(hi2c); + 8002212: 687b ldr r3, [r7, #4] + 8002214: 681b ldr r3, [r3, #0] + 8002216: 681a ldr r2, [r3, #0] + 8002218: 687b ldr r3, [r7, #4] + 800221a: 681b ldr r3, [r3, #0] + 800221c: f042 0201 orr.w r2, r2, #1 + 8002220: 601a str r2, [r3, #0] + + hi2c->State = HAL_I2C_STATE_READY; + 8002222: 687b ldr r3, [r7, #4] + 8002224: 2220 movs r2, #32 + 8002226: f883 2041 strb.w r2, [r3, #65] @ 0x41 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 800222a: 687b ldr r3, [r7, #4] + 800222c: 2200 movs r2, #0 + 800222e: f883 2040 strb.w r2, [r3, #64] @ 0x40 + + return HAL_OK; + 8002232: 2300 movs r3, #0 + 8002234: e000 b.n 8002238 <HAL_I2CEx_ConfigAnalogFilter+0x8a> + } + else + { + return HAL_BUSY; + 8002236: 2302 movs r3, #2 + } +} + 8002238: 4618 mov r0, r3 + 800223a: 370c adds r7, #12 + 800223c: 46bd mov sp, r7 + 800223e: f85d 7b04 ldr.w r7, [sp], #4 + 8002242: 4770 bx lr + +08002244 <HAL_I2CEx_ConfigDigitalFilter>: + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + 8002244: b480 push {r7} + 8002246: b085 sub sp, #20 + 8002248: af00 add r7, sp, #0 + 800224a: 6078 str r0, [r7, #4] + 800224c: 6039 str r1, [r7, #0] + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + 800224e: 687b ldr r3, [r7, #4] + 8002250: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 + 8002254: b2db uxtb r3, r3 + 8002256: 2b20 cmp r3, #32 + 8002258: d139 bne.n 80022ce <HAL_I2CEx_ConfigDigitalFilter+0x8a> + { + /* Process Locked */ + __HAL_LOCK(hi2c); + 800225a: 687b ldr r3, [r7, #4] + 800225c: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 + 8002260: 2b01 cmp r3, #1 + 8002262: d101 bne.n 8002268 <HAL_I2CEx_ConfigDigitalFilter+0x24> + 8002264: 2302 movs r3, #2 + 8002266: e033 b.n 80022d0 <HAL_I2CEx_ConfigDigitalFilter+0x8c> + 8002268: 687b ldr r3, [r7, #4] + 800226a: 2201 movs r2, #1 + 800226c: f883 2040 strb.w r2, [r3, #64] @ 0x40 + + hi2c->State = HAL_I2C_STATE_BUSY; + 8002270: 687b ldr r3, [r7, #4] + 8002272: 2224 movs r2, #36 @ 0x24 + 8002274: f883 2041 strb.w r2, [r3, #65] @ 0x41 + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + 8002278: 687b ldr r3, [r7, #4] + 800227a: 681b ldr r3, [r3, #0] + 800227c: 681a ldr r2, [r3, #0] + 800227e: 687b ldr r3, [r7, #4] + 8002280: 681b ldr r3, [r3, #0] + 8002282: f022 0201 bic.w r2, r2, #1 + 8002286: 601a str r2, [r3, #0] + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + 8002288: 687b ldr r3, [r7, #4] + 800228a: 681b ldr r3, [r3, #0] + 800228c: 681b ldr r3, [r3, #0] + 800228e: 60fb str r3, [r7, #12] + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + 8002290: 68fb ldr r3, [r7, #12] + 8002292: f423 6370 bic.w r3, r3, #3840 @ 0xf00 + 8002296: 60fb str r3, [r7, #12] + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8U; + 8002298: 683b ldr r3, [r7, #0] + 800229a: 021b lsls r3, r3, #8 + 800229c: 68fa ldr r2, [r7, #12] + 800229e: 4313 orrs r3, r2 + 80022a0: 60fb str r3, [r7, #12] + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + 80022a2: 687b ldr r3, [r7, #4] + 80022a4: 681b ldr r3, [r3, #0] + 80022a6: 68fa ldr r2, [r7, #12] + 80022a8: 601a str r2, [r3, #0] + + __HAL_I2C_ENABLE(hi2c); + 80022aa: 687b ldr r3, [r7, #4] + 80022ac: 681b ldr r3, [r3, #0] + 80022ae: 681a ldr r2, [r3, #0] + 80022b0: 687b ldr r3, [r7, #4] + 80022b2: 681b ldr r3, [r3, #0] + 80022b4: f042 0201 orr.w r2, r2, #1 + 80022b8: 601a str r2, [r3, #0] + + hi2c->State = HAL_I2C_STATE_READY; + 80022ba: 687b ldr r3, [r7, #4] + 80022bc: 2220 movs r2, #32 + 80022be: f883 2041 strb.w r2, [r3, #65] @ 0x41 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 80022c2: 687b ldr r3, [r7, #4] + 80022c4: 2200 movs r2, #0 + 80022c6: f883 2040 strb.w r2, [r3, #64] @ 0x40 + + return HAL_OK; + 80022ca: 2300 movs r3, #0 + 80022cc: e000 b.n 80022d0 <HAL_I2CEx_ConfigDigitalFilter+0x8c> + } + else + { + return HAL_BUSY; + 80022ce: 2302 movs r3, #2 + } +} + 80022d0: 4618 mov r0, r3 + 80022d2: 3714 adds r7, #20 + 80022d4: 46bd mov sp, r7 + 80022d6: f85d 7b04 ldr.w r7, [sp], #4 + 80022da: 4770 bx lr + +080022dc <HAL_IPCC_Init>: + * @brief Initialize the IPCC peripheral. + * @param hipcc IPCC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IPCC_Init(IPCC_HandleTypeDef *hipcc) +{ + 80022dc: b580 push {r7, lr} + 80022de: b084 sub sp, #16 + 80022e0: af00 add r7, sp, #0 + 80022e2: 6078 str r0, [r7, #4] + HAL_StatusTypeDef err = HAL_OK; + 80022e4: 2300 movs r3, #0 + 80022e6: 73fb strb r3, [r7, #15] + + /* Check the IPCC handle allocation */ + if (hipcc != NULL) + 80022e8: 687b ldr r3, [r7, #4] + 80022ea: 2b00 cmp r3, #0 + 80022ec: d01e beq.n 800232c <HAL_IPCC_Init+0x50> + { + /* Check the parameters */ + assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance)); + + IPCC_CommonTypeDef *currentInstance = IPCC_C1; + 80022ee: 4b13 ldr r3, [pc, #76] @ (800233c <HAL_IPCC_Init+0x60>) + 80022f0: 60bb str r3, [r7, #8] + + if (hipcc->State == HAL_IPCC_STATE_RESET) + 80022f2: 687b ldr r3, [r7, #4] + 80022f4: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 80022f8: b2db uxtb r3, r3 + 80022fa: 2b00 cmp r3, #0 + 80022fc: d102 bne.n 8002304 <HAL_IPCC_Init+0x28> + { + /* Init the low level hardware : CLOCK, NVIC */ + HAL_IPCC_MspInit(hipcc); + 80022fe: 6878 ldr r0, [r7, #4] + 8002300: f7ff f9c4 bl 800168c <HAL_IPCC_MspInit> + } + + /* Reset all registers of the current cpu to default state */ + IPCC_Reset_Register(currentInstance); + 8002304: 68b8 ldr r0, [r7, #8] + 8002306: f000 f85b bl 80023c0 <IPCC_Reset_Register> + + /* Activate the interrupts */ + currentInstance->CR |= (IPCC_CR_RXOIE | IPCC_CR_TXFIE); + 800230a: 68bb ldr r3, [r7, #8] + 800230c: 681b ldr r3, [r3, #0] + 800230e: f043 1201 orr.w r2, r3, #65537 @ 0x10001 + 8002312: 68bb ldr r3, [r7, #8] + 8002314: 601a str r2, [r3, #0] + + /* Clear callback pointers */ + IPCC_SetDefaultCallbacks(hipcc); + 8002316: 6878 ldr r0, [r7, #4] + 8002318: f000 f82c bl 8002374 <IPCC_SetDefaultCallbacks> + + /* Reset all callback notification request */ + hipcc->callbackRequest = 0; + 800231c: 687b ldr r3, [r7, #4] + 800231e: 2200 movs r2, #0 + 8002320: 635a str r2, [r3, #52] @ 0x34 + + hipcc->State = HAL_IPCC_STATE_READY; + 8002322: 687b ldr r3, [r7, #4] + 8002324: 2201 movs r2, #1 + 8002326: f883 2038 strb.w r2, [r3, #56] @ 0x38 + 800232a: e001 b.n 8002330 <HAL_IPCC_Init+0x54> + } + else + { + err = HAL_ERROR; + 800232c: 2301 movs r3, #1 + 800232e: 73fb strb r3, [r7, #15] + } + + return err; + 8002330: 7bfb ldrb r3, [r7, #15] +} + 8002332: 4618 mov r0, r3 + 8002334: 3710 adds r7, #16 + 8002336: 46bd mov sp, r7 + 8002338: bd80 pop {r7, pc} + 800233a: bf00 nop + 800233c: 58000c00 .word 0x58000c00 + +08002340 <HAL_IPCC_RxCallback>: + * @arg IPCC_CHANNEL_5: IPCC Channel 5 + * @arg IPCC_CHANNEL_6: IPCC Channel 6 + * @param ChannelDir Channel direction + */ +__weak void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir) +{ + 8002340: b480 push {r7} + 8002342: b085 sub sp, #20 + 8002344: af00 add r7, sp, #0 + 8002346: 60f8 str r0, [r7, #12] + 8002348: 60b9 str r1, [r7, #8] + 800234a: 4613 mov r3, r2 + 800234c: 71fb strb r3, [r7, #7] + UNUSED(ChannelDir); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IPCC_RxCallback can be implemented in the user file + */ +} + 800234e: bf00 nop + 8002350: 3714 adds r7, #20 + 8002352: 46bd mov sp, r7 + 8002354: f85d 7b04 ldr.w r7, [sp], #4 + 8002358: 4770 bx lr + +0800235a <HAL_IPCC_TxCallback>: + * @arg IPCC_CHANNEL_5: IPCC Channel 5 + * @arg IPCC_CHANNEL_6: IPCC Channel 6 + * @param ChannelDir Channel direction + */ +__weak void HAL_IPCC_TxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir) +{ + 800235a: b480 push {r7} + 800235c: b085 sub sp, #20 + 800235e: af00 add r7, sp, #0 + 8002360: 60f8 str r0, [r7, #12] + 8002362: 60b9 str r1, [r7, #8] + 8002364: 4613 mov r3, r2 + 8002366: 71fb strb r3, [r7, #7] + UNUSED(ChannelDir); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IPCC_TxCallback can be implemented in the user file + */ +} + 8002368: bf00 nop + 800236a: 3714 adds r7, #20 + 800236c: 46bd mov sp, r7 + 800236e: f85d 7b04 ldr.w r7, [sp], #4 + 8002372: 4770 bx lr + +08002374 <IPCC_SetDefaultCallbacks>: +/** + * @brief Reset all callbacks of the handle to NULL. + * @param hipcc IPCC handle + */ +void IPCC_SetDefaultCallbacks(IPCC_HandleTypeDef *hipcc) +{ + 8002374: b480 push {r7} + 8002376: b085 sub sp, #20 + 8002378: af00 add r7, sp, #0 + 800237a: 6078 str r0, [r7, #4] + uint32_t i; + /* Set all callbacks to default */ + for (i = 0; i < IPCC_CHANNEL_NUMBER; i++) + 800237c: 2300 movs r3, #0 + 800237e: 60fb str r3, [r7, #12] + 8002380: e00f b.n 80023a2 <IPCC_SetDefaultCallbacks+0x2e> + { + hipcc->ChannelCallbackRx[i] = HAL_IPCC_RxCallback; + 8002382: 687a ldr r2, [r7, #4] + 8002384: 68fb ldr r3, [r7, #12] + 8002386: 009b lsls r3, r3, #2 + 8002388: 4413 add r3, r2 + 800238a: 4a0b ldr r2, [pc, #44] @ (80023b8 <IPCC_SetDefaultCallbacks+0x44>) + 800238c: 605a str r2, [r3, #4] + hipcc->ChannelCallbackTx[i] = HAL_IPCC_TxCallback; + 800238e: 687a ldr r2, [r7, #4] + 8002390: 68fb ldr r3, [r7, #12] + 8002392: 3306 adds r3, #6 + 8002394: 009b lsls r3, r3, #2 + 8002396: 4413 add r3, r2 + 8002398: 4a08 ldr r2, [pc, #32] @ (80023bc <IPCC_SetDefaultCallbacks+0x48>) + 800239a: 605a str r2, [r3, #4] + for (i = 0; i < IPCC_CHANNEL_NUMBER; i++) + 800239c: 68fb ldr r3, [r7, #12] + 800239e: 3301 adds r3, #1 + 80023a0: 60fb str r3, [r7, #12] + 80023a2: 68fb ldr r3, [r7, #12] + 80023a4: 2b05 cmp r3, #5 + 80023a6: d9ec bls.n 8002382 <IPCC_SetDefaultCallbacks+0xe> + } +} + 80023a8: bf00 nop + 80023aa: bf00 nop + 80023ac: 3714 adds r7, #20 + 80023ae: 46bd mov sp, r7 + 80023b0: f85d 7b04 ldr.w r7, [sp], #4 + 80023b4: 4770 bx lr + 80023b6: bf00 nop + 80023b8: 08002341 .word 0x08002341 + 80023bc: 0800235b .word 0x0800235b + +080023c0 <IPCC_Reset_Register>: +/** + * @brief Reset IPCC register to default value for the concerned instance. + * @param Instance pointer to register + */ +void IPCC_Reset_Register(IPCC_CommonTypeDef *Instance) +{ + 80023c0: b480 push {r7} + 80023c2: b083 sub sp, #12 + 80023c4: af00 add r7, sp, #0 + 80023c6: 6078 str r0, [r7, #4] + /* Disable RX and TX interrupts */ + Instance->CR = 0x00000000U; + 80023c8: 687b ldr r3, [r7, #4] + 80023ca: 2200 movs r2, #0 + 80023cc: 601a str r2, [r3, #0] + + /* Mask RX and TX interrupts */ + Instance->MR = (IPCC_ALL_TX_BUF | IPCC_ALL_RX_BUF); + 80023ce: 687b ldr r3, [r7, #4] + 80023d0: f04f 123f mov.w r2, #4128831 @ 0x3f003f + 80023d4: 605a str r2, [r3, #4] + + /* Clear RX status */ + Instance->SCR = IPCC_ALL_RX_BUF; + 80023d6: 687b ldr r3, [r7, #4] + 80023d8: 223f movs r2, #63 @ 0x3f + 80023da: 609a str r2, [r3, #8] +} + 80023dc: bf00 nop + 80023de: 370c adds r7, #12 + 80023e0: 46bd mov sp, r7 + 80023e2: f85d 7b04 ldr.w r7, [sp], #4 + 80023e6: 4770 bx lr + +080023e8 <HAL_PWR_EnableBkUpAccess>: + * @note LSEON bit that switches on and off the LSE crystal belongs as well to the + * back-up domain. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + 80023e8: b480 push {r7} + 80023ea: af00 add r7, sp, #0 + SET_BIT(PWR->CR1, PWR_CR1_DBP); + 80023ec: 4b05 ldr r3, [pc, #20] @ (8002404 <HAL_PWR_EnableBkUpAccess+0x1c>) + 80023ee: 681b ldr r3, [r3, #0] + 80023f0: 4a04 ldr r2, [pc, #16] @ (8002404 <HAL_PWR_EnableBkUpAccess+0x1c>) + 80023f2: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80023f6: 6013 str r3, [r2, #0] +} + 80023f8: bf00 nop + 80023fa: 46bd mov sp, r7 + 80023fc: f85d 7b04 ldr.w r7, [sp], #4 + 8002400: 4770 bx lr + 8002402: bf00 nop + 8002404: 58000400 .word 0x58000400 + +08002408 <HAL_PWREx_GetVoltageRange>: +/** + * @brief Return Voltage Scaling Range. + * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2) + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + 8002408: b480 push {r7} + 800240a: af00 add r7, sp, #0 + return (PWR->CR1 & PWR_CR1_VOS); + 800240c: 4b04 ldr r3, [pc, #16] @ (8002420 <HAL_PWREx_GetVoltageRange+0x18>) + 800240e: 681b ldr r3, [r3, #0] + 8002410: f403 63c0 and.w r3, r3, #1536 @ 0x600 +} + 8002414: 4618 mov r0, r3 + 8002416: 46bd mov sp, r7 + 8002418: f85d 7b04 ldr.w r7, [sp], #4 + 800241c: 4770 bx lr + 800241e: bf00 nop + 8002420: 58000400 .word 0x58000400 + +08002424 <HAL_PWREx_EnterSTOP2Mode>: + * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction + * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry) +{ + 8002424: b480 push {r7} + 8002426: b083 sub sp, #12 + 8002428: af00 add r7, sp, #0 + 800242a: 4603 mov r3, r0 + 800242c: 71fb strb r3, [r7, #7] + /* Check the parameter */ + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Set Stop mode 2 */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP2); + 800242e: 4b11 ldr r3, [pc, #68] @ (8002474 <HAL_PWREx_EnterSTOP2Mode+0x50>) + 8002430: 681b ldr r3, [r3, #0] + 8002432: f023 0307 bic.w r3, r3, #7 + 8002436: 4a0f ldr r2, [pc, #60] @ (8002474 <HAL_PWREx_EnterSTOP2Mode+0x50>) + 8002438: f043 0302 orr.w r3, r3, #2 + 800243c: 6013 str r3, [r2, #0] + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 800243e: 4b0e ldr r3, [pc, #56] @ (8002478 <HAL_PWREx_EnterSTOP2Mode+0x54>) + 8002440: 691b ldr r3, [r3, #16] + 8002442: 4a0d ldr r2, [pc, #52] @ (8002478 <HAL_PWREx_EnterSTOP2Mode+0x54>) + 8002444: f043 0304 orr.w r3, r3, #4 + 8002448: 6113 str r3, [r2, #16] + + /* Select Stop mode entry --------------------------------------------------*/ + if (STOPEntry == PWR_STOPENTRY_WFI) + 800244a: 79fb ldrb r3, [r7, #7] + 800244c: 2b01 cmp r3, #1 + 800244e: d101 bne.n 8002454 <HAL_PWREx_EnterSTOP2Mode+0x30> + { + /* Request Wait For Interrupt */ + __WFI(); + 8002450: bf30 wfi + 8002452: e002 b.n 800245a <HAL_PWREx_EnterSTOP2Mode+0x36> + } + else + { + /* Request Wait For Event */ + __SEV(); + 8002454: bf40 sev + __WFE(); + 8002456: bf20 wfe + __WFE(); + 8002458: bf20 wfe + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 800245a: 4b07 ldr r3, [pc, #28] @ (8002478 <HAL_PWREx_EnterSTOP2Mode+0x54>) + 800245c: 691b ldr r3, [r3, #16] + 800245e: 4a06 ldr r2, [pc, #24] @ (8002478 <HAL_PWREx_EnterSTOP2Mode+0x54>) + 8002460: f023 0304 bic.w r3, r3, #4 + 8002464: 6113 str r3, [r2, #16] +} + 8002466: bf00 nop + 8002468: 370c adds r7, #12 + 800246a: 46bd mov sp, r7 + 800246c: f85d 7b04 ldr.w r7, [sp], #4 + 8002470: 4770 bx lr + 8002472: bf00 nop + 8002474: 58000400 .word 0x58000400 + 8002478: e000ed00 .word 0xe000ed00 + +0800247c <LL_RCC_HSE_IsEnabledDiv2>: +{ + 800247c: b480 push {r7} + 800247e: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == (RCC_CR_HSEPRE)) ? 1UL : 0UL); + 8002480: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002484: 681b ldr r3, [r3, #0] + 8002486: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 800248a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 800248e: d101 bne.n 8002494 <LL_RCC_HSE_IsEnabledDiv2+0x18> + 8002490: 2301 movs r3, #1 + 8002492: e000 b.n 8002496 <LL_RCC_HSE_IsEnabledDiv2+0x1a> + 8002494: 2300 movs r3, #0 +} + 8002496: 4618 mov r0, r3 + 8002498: 46bd mov sp, r7 + 800249a: f85d 7b04 ldr.w r7, [sp], #4 + 800249e: 4770 bx lr + +080024a0 <LL_RCC_HSE_Enable>: +{ + 80024a0: b480 push {r7} + 80024a2: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_HSEON); + 80024a4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80024a8: 681b ldr r3, [r3, #0] + 80024aa: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80024ae: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 80024b2: 6013 str r3, [r2, #0] +} + 80024b4: bf00 nop + 80024b6: 46bd mov sp, r7 + 80024b8: f85d 7b04 ldr.w r7, [sp], #4 + 80024bc: 4770 bx lr + +080024be <LL_RCC_HSE_Disable>: +{ + 80024be: b480 push {r7} + 80024c0: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); + 80024c2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80024c6: 681b ldr r3, [r3, #0] + 80024c8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80024cc: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 80024d0: 6013 str r3, [r2, #0] +} + 80024d2: bf00 nop + 80024d4: 46bd mov sp, r7 + 80024d6: f85d 7b04 ldr.w r7, [sp], #4 + 80024da: 4770 bx lr + +080024dc <LL_RCC_HSE_IsReady>: +{ + 80024dc: b480 push {r7} + 80024de: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); + 80024e0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80024e4: 681b ldr r3, [r3, #0] + 80024e6: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80024ea: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 + 80024ee: d101 bne.n 80024f4 <LL_RCC_HSE_IsReady+0x18> + 80024f0: 2301 movs r3, #1 + 80024f2: e000 b.n 80024f6 <LL_RCC_HSE_IsReady+0x1a> + 80024f4: 2300 movs r3, #0 +} + 80024f6: 4618 mov r0, r3 + 80024f8: 46bd mov sp, r7 + 80024fa: f85d 7b04 ldr.w r7, [sp], #4 + 80024fe: 4770 bx lr + +08002500 <LL_RCC_HSI_Enable>: +{ + 8002500: b480 push {r7} + 8002502: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_HSION); + 8002504: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002508: 681b ldr r3, [r3, #0] + 800250a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 800250e: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8002512: 6013 str r3, [r2, #0] +} + 8002514: bf00 nop + 8002516: 46bd mov sp, r7 + 8002518: f85d 7b04 ldr.w r7, [sp], #4 + 800251c: 4770 bx lr + +0800251e <LL_RCC_HSI_Disable>: +{ + 800251e: b480 push {r7} + 8002520: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_HSION); + 8002522: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002526: 681b ldr r3, [r3, #0] + 8002528: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 800252c: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8002530: 6013 str r3, [r2, #0] +} + 8002532: bf00 nop + 8002534: 46bd mov sp, r7 + 8002536: f85d 7b04 ldr.w r7, [sp], #4 + 800253a: 4770 bx lr + +0800253c <LL_RCC_HSI_IsReady>: +{ + 800253c: b480 push {r7} + 800253e: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL); + 8002540: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002544: 681b ldr r3, [r3, #0] + 8002546: f403 6380 and.w r3, r3, #1024 @ 0x400 + 800254a: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 800254e: d101 bne.n 8002554 <LL_RCC_HSI_IsReady+0x18> + 8002550: 2301 movs r3, #1 + 8002552: e000 b.n 8002556 <LL_RCC_HSI_IsReady+0x1a> + 8002554: 2300 movs r3, #0 +} + 8002556: 4618 mov r0, r3 + 8002558: 46bd mov sp, r7 + 800255a: f85d 7b04 ldr.w r7, [sp], #4 + 800255e: 4770 bx lr + +08002560 <LL_RCC_HSI_SetCalibTrimming>: +{ + 8002560: b480 push {r7} + 8002562: b083 sub sp, #12 + 8002564: af00 add r7, sp, #0 + 8002566: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos); + 8002568: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800256c: 685b ldr r3, [r3, #4] + 800256e: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 + 8002572: 687b ldr r3, [r7, #4] + 8002574: 061b lsls r3, r3, #24 + 8002576: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800257a: 4313 orrs r3, r2 + 800257c: 604b str r3, [r1, #4] +} + 800257e: bf00 nop + 8002580: 370c adds r7, #12 + 8002582: 46bd mov sp, r7 + 8002584: f85d 7b04 ldr.w r7, [sp], #4 + 8002588: 4770 bx lr + +0800258a <LL_RCC_HSI48_Enable>: +{ + 800258a: b480 push {r7} + 800258c: af00 add r7, sp, #0 + SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); + 800258e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002592: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 + 8002596: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 800259a: f043 0301 orr.w r3, r3, #1 + 800259e: f8c2 3098 str.w r3, [r2, #152] @ 0x98 +} + 80025a2: bf00 nop + 80025a4: 46bd mov sp, r7 + 80025a6: f85d 7b04 ldr.w r7, [sp], #4 + 80025aa: 4770 bx lr + +080025ac <LL_RCC_HSI48_Disable>: +{ + 80025ac: b480 push {r7} + 80025ae: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); + 80025b0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80025b4: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 + 80025b8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80025bc: f023 0301 bic.w r3, r3, #1 + 80025c0: f8c2 3098 str.w r3, [r2, #152] @ 0x98 +} + 80025c4: bf00 nop + 80025c6: 46bd mov sp, r7 + 80025c8: f85d 7b04 ldr.w r7, [sp], #4 + 80025cc: 4770 bx lr + +080025ce <LL_RCC_HSI48_IsReady>: +{ + 80025ce: b480 push {r7} + 80025d0: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)) ? 1UL : 0UL); + 80025d2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80025d6: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 + 80025da: f003 0302 and.w r3, r3, #2 + 80025de: 2b02 cmp r3, #2 + 80025e0: d101 bne.n 80025e6 <LL_RCC_HSI48_IsReady+0x18> + 80025e2: 2301 movs r3, #1 + 80025e4: e000 b.n 80025e8 <LL_RCC_HSI48_IsReady+0x1a> + 80025e6: 2300 movs r3, #0 +} + 80025e8: 4618 mov r0, r3 + 80025ea: 46bd mov sp, r7 + 80025ec: f85d 7b04 ldr.w r7, [sp], #4 + 80025f0: 4770 bx lr + +080025f2 <LL_RCC_LSE_Enable>: +{ + 80025f2: b480 push {r7} + 80025f4: af00 add r7, sp, #0 + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); + 80025f6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80025fa: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80025fe: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002602: f043 0301 orr.w r3, r3, #1 + 8002606: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 800260a: bf00 nop + 800260c: 46bd mov sp, r7 + 800260e: f85d 7b04 ldr.w r7, [sp], #4 + 8002612: 4770 bx lr + +08002614 <LL_RCC_LSE_Disable>: +{ + 8002614: b480 push {r7} + 8002616: af00 add r7, sp, #0 + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); + 8002618: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800261c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8002620: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002624: f023 0301 bic.w r3, r3, #1 + 8002628: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 800262c: bf00 nop + 800262e: 46bd mov sp, r7 + 8002630: f85d 7b04 ldr.w r7, [sp], #4 + 8002634: 4770 bx lr + +08002636 <LL_RCC_LSE_EnableBypass>: +{ + 8002636: b480 push {r7} + 8002638: af00 add r7, sp, #0 + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); + 800263a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800263e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8002642: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002646: f043 0304 orr.w r3, r3, #4 + 800264a: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 800264e: bf00 nop + 8002650: 46bd mov sp, r7 + 8002652: f85d 7b04 ldr.w r7, [sp], #4 + 8002656: 4770 bx lr + +08002658 <LL_RCC_LSE_DisableBypass>: +{ + 8002658: b480 push {r7} + 800265a: af00 add r7, sp, #0 + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); + 800265c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002660: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8002664: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002668: f023 0304 bic.w r3, r3, #4 + 800266c: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 8002670: bf00 nop + 8002672: 46bd mov sp, r7 + 8002674: f85d 7b04 ldr.w r7, [sp], #4 + 8002678: 4770 bx lr + +0800267a <LL_RCC_LSE_IsReady>: +{ + 800267a: b480 push {r7} + 800267c: af00 add r7, sp, #0 + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); + 800267e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002682: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8002686: f003 0302 and.w r3, r3, #2 + 800268a: 2b02 cmp r3, #2 + 800268c: d101 bne.n 8002692 <LL_RCC_LSE_IsReady+0x18> + 800268e: 2301 movs r3, #1 + 8002690: e000 b.n 8002694 <LL_RCC_LSE_IsReady+0x1a> + 8002692: 2300 movs r3, #0 +} + 8002694: 4618 mov r0, r3 + 8002696: 46bd mov sp, r7 + 8002698: f85d 7b04 ldr.w r7, [sp], #4 + 800269c: 4770 bx lr + +0800269e <LL_RCC_LSI1_Enable>: +{ + 800269e: b480 push {r7} + 80026a0: af00 add r7, sp, #0 + SET_BIT(RCC->CSR, RCC_CSR_LSI1ON); + 80026a2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80026a6: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 80026aa: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80026ae: f043 0301 orr.w r3, r3, #1 + 80026b2: f8c2 3094 str.w r3, [r2, #148] @ 0x94 +} + 80026b6: bf00 nop + 80026b8: 46bd mov sp, r7 + 80026ba: f85d 7b04 ldr.w r7, [sp], #4 + 80026be: 4770 bx lr + +080026c0 <LL_RCC_LSI1_Disable>: +{ + 80026c0: b480 push {r7} + 80026c2: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CSR, RCC_CSR_LSI1ON); + 80026c4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80026c8: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 80026cc: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80026d0: f023 0301 bic.w r3, r3, #1 + 80026d4: f8c2 3094 str.w r3, [r2, #148] @ 0x94 +} + 80026d8: bf00 nop + 80026da: 46bd mov sp, r7 + 80026dc: f85d 7b04 ldr.w r7, [sp], #4 + 80026e0: 4770 bx lr + +080026e2 <LL_RCC_LSI1_IsReady>: +{ + 80026e2: b480 push {r7} + 80026e4: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CSR, RCC_CSR_LSI1RDY) == (RCC_CSR_LSI1RDY)) ? 1UL : 0UL); + 80026e6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80026ea: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 80026ee: f003 0302 and.w r3, r3, #2 + 80026f2: 2b02 cmp r3, #2 + 80026f4: d101 bne.n 80026fa <LL_RCC_LSI1_IsReady+0x18> + 80026f6: 2301 movs r3, #1 + 80026f8: e000 b.n 80026fc <LL_RCC_LSI1_IsReady+0x1a> + 80026fa: 2300 movs r3, #0 +} + 80026fc: 4618 mov r0, r3 + 80026fe: 46bd mov sp, r7 + 8002700: f85d 7b04 ldr.w r7, [sp], #4 + 8002704: 4770 bx lr + +08002706 <LL_RCC_LSI2_Enable>: +{ + 8002706: b480 push {r7} + 8002708: af00 add r7, sp, #0 + SET_BIT(RCC->CSR, RCC_CSR_LSI2ON); + 800270a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800270e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8002712: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002716: f043 0304 orr.w r3, r3, #4 + 800271a: f8c2 3094 str.w r3, [r2, #148] @ 0x94 +} + 800271e: bf00 nop + 8002720: 46bd mov sp, r7 + 8002722: f85d 7b04 ldr.w r7, [sp], #4 + 8002726: 4770 bx lr + +08002728 <LL_RCC_LSI2_Disable>: +{ + 8002728: b480 push {r7} + 800272a: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CSR, RCC_CSR_LSI2ON); + 800272c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002730: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8002734: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002738: f023 0304 bic.w r3, r3, #4 + 800273c: f8c2 3094 str.w r3, [r2, #148] @ 0x94 +} + 8002740: bf00 nop + 8002742: 46bd mov sp, r7 + 8002744: f85d 7b04 ldr.w r7, [sp], #4 + 8002748: 4770 bx lr + +0800274a <LL_RCC_LSI2_IsReady>: +{ + 800274a: b480 push {r7} + 800274c: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CSR, RCC_CSR_LSI2RDY) == (RCC_CSR_LSI2RDY)) ? 1UL : 0UL); + 800274e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002752: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8002756: f003 0308 and.w r3, r3, #8 + 800275a: 2b08 cmp r3, #8 + 800275c: d101 bne.n 8002762 <LL_RCC_LSI2_IsReady+0x18> + 800275e: 2301 movs r3, #1 + 8002760: e000 b.n 8002764 <LL_RCC_LSI2_IsReady+0x1a> + 8002762: 2300 movs r3, #0 +} + 8002764: 4618 mov r0, r3 + 8002766: 46bd mov sp, r7 + 8002768: f85d 7b04 ldr.w r7, [sp], #4 + 800276c: 4770 bx lr + +0800276e <LL_RCC_LSI2_SetTrimming>: +{ + 800276e: b480 push {r7} + 8002770: b083 sub sp, #12 + 8002772: af00 add r7, sp, #0 + 8002774: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CSR, RCC_CSR_LSI2TRIM, Value << RCC_CSR_LSI2TRIM_Pos); + 8002776: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800277a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 800277e: f423 6270 bic.w r2, r3, #3840 @ 0xf00 + 8002782: 687b ldr r3, [r7, #4] + 8002784: 021b lsls r3, r3, #8 + 8002786: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800278a: 4313 orrs r3, r2 + 800278c: f8c1 3094 str.w r3, [r1, #148] @ 0x94 +} + 8002790: bf00 nop + 8002792: 370c adds r7, #12 + 8002794: 46bd mov sp, r7 + 8002796: f85d 7b04 ldr.w r7, [sp], #4 + 800279a: 4770 bx lr + +0800279c <LL_RCC_MSI_Enable>: +{ + 800279c: b480 push {r7} + 800279e: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_MSION); + 80027a0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80027a4: 681b ldr r3, [r3, #0] + 80027a6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80027aa: f043 0301 orr.w r3, r3, #1 + 80027ae: 6013 str r3, [r2, #0] +} + 80027b0: bf00 nop + 80027b2: 46bd mov sp, r7 + 80027b4: f85d 7b04 ldr.w r7, [sp], #4 + 80027b8: 4770 bx lr + +080027ba <LL_RCC_MSI_Disable>: +{ + 80027ba: b480 push {r7} + 80027bc: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_MSION); + 80027be: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80027c2: 681b ldr r3, [r3, #0] + 80027c4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80027c8: f023 0301 bic.w r3, r3, #1 + 80027cc: 6013 str r3, [r2, #0] +} + 80027ce: bf00 nop + 80027d0: 46bd mov sp, r7 + 80027d2: f85d 7b04 ldr.w r7, [sp], #4 + 80027d6: 4770 bx lr + +080027d8 <LL_RCC_MSI_IsReady>: +{ + 80027d8: b480 push {r7} + 80027da: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)) ? 1UL : 0UL); + 80027dc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80027e0: 681b ldr r3, [r3, #0] + 80027e2: f003 0302 and.w r3, r3, #2 + 80027e6: 2b02 cmp r3, #2 + 80027e8: d101 bne.n 80027ee <LL_RCC_MSI_IsReady+0x16> + 80027ea: 2301 movs r3, #1 + 80027ec: e000 b.n 80027f0 <LL_RCC_MSI_IsReady+0x18> + 80027ee: 2300 movs r3, #0 +} + 80027f0: 4618 mov r0, r3 + 80027f2: 46bd mov sp, r7 + 80027f4: f85d 7b04 ldr.w r7, [sp], #4 + 80027f8: 4770 bx lr + +080027fa <LL_RCC_MSI_SetRange>: +{ + 80027fa: b480 push {r7} + 80027fc: b083 sub sp, #12 + 80027fe: af00 add r7, sp, #0 + 8002800: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range); + 8002802: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002806: 681b ldr r3, [r3, #0] + 8002808: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 800280c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002810: 687b ldr r3, [r7, #4] + 8002812: 4313 orrs r3, r2 + 8002814: 600b str r3, [r1, #0] +} + 8002816: bf00 nop + 8002818: 370c adds r7, #12 + 800281a: 46bd mov sp, r7 + 800281c: f85d 7b04 ldr.w r7, [sp], #4 + 8002820: 4770 bx lr + +08002822 <LL_RCC_MSI_GetRange>: +{ + 8002822: b480 push {r7} + 8002824: b083 sub sp, #12 + 8002826: af00 add r7, sp, #0 + uint32_t msiRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE); + 8002828: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800282c: 681b ldr r3, [r3, #0] + 800282e: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 8002832: 607b str r3, [r7, #4] + if (msiRange > LL_RCC_MSIRANGE_11) + 8002834: 687b ldr r3, [r7, #4] + 8002836: 2bb0 cmp r3, #176 @ 0xb0 + 8002838: d901 bls.n 800283e <LL_RCC_MSI_GetRange+0x1c> + msiRange = LL_RCC_MSIRANGE_11; + 800283a: 23b0 movs r3, #176 @ 0xb0 + 800283c: 607b str r3, [r7, #4] + return msiRange; + 800283e: 687b ldr r3, [r7, #4] +} + 8002840: 4618 mov r0, r3 + 8002842: 370c adds r7, #12 + 8002844: 46bd mov sp, r7 + 8002846: f85d 7b04 ldr.w r7, [sp], #4 + 800284a: 4770 bx lr + +0800284c <LL_RCC_MSI_SetCalibTrimming>: +{ + 800284c: b480 push {r7} + 800284e: b083 sub sp, #12 + 8002850: af00 add r7, sp, #0 + 8002852: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos); + 8002854: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002858: 685b ldr r3, [r3, #4] + 800285a: f423 427f bic.w r2, r3, #65280 @ 0xff00 + 800285e: 687b ldr r3, [r7, #4] + 8002860: 021b lsls r3, r3, #8 + 8002862: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002866: 4313 orrs r3, r2 + 8002868: 604b str r3, [r1, #4] +} + 800286a: bf00 nop + 800286c: 370c adds r7, #12 + 800286e: 46bd mov sp, r7 + 8002870: f85d 7b04 ldr.w r7, [sp], #4 + 8002874: 4770 bx lr + +08002876 <LL_RCC_SetSysClkSource>: +{ + 8002876: b480 push {r7} + 8002878: b083 sub sp, #12 + 800287a: af00 add r7, sp, #0 + 800287c: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); + 800287e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002882: 689b ldr r3, [r3, #8] + 8002884: f023 0203 bic.w r2, r3, #3 + 8002888: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800288c: 687b ldr r3, [r7, #4] + 800288e: 4313 orrs r3, r2 + 8002890: 608b str r3, [r1, #8] +} + 8002892: bf00 nop + 8002894: 370c adds r7, #12 + 8002896: 46bd mov sp, r7 + 8002898: f85d 7b04 ldr.w r7, [sp], #4 + 800289c: 4770 bx lr + +0800289e <LL_RCC_GetSysClkSource>: +{ + 800289e: b480 push {r7} + 80028a0: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); + 80028a2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80028a6: 689b ldr r3, [r3, #8] + 80028a8: f003 030c and.w r3, r3, #12 +} + 80028ac: 4618 mov r0, r3 + 80028ae: 46bd mov sp, r7 + 80028b0: f85d 7b04 ldr.w r7, [sp], #4 + 80028b4: 4770 bx lr + +080028b6 <LL_RCC_SetAHBPrescaler>: +{ + 80028b6: b480 push {r7} + 80028b8: b083 sub sp, #12 + 80028ba: af00 add r7, sp, #0 + 80028bc: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); + 80028be: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80028c2: 689b ldr r3, [r3, #8] + 80028c4: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 80028c8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80028cc: 687b ldr r3, [r7, #4] + 80028ce: 4313 orrs r3, r2 + 80028d0: 608b str r3, [r1, #8] +} + 80028d2: bf00 nop + 80028d4: 370c adds r7, #12 + 80028d6: 46bd mov sp, r7 + 80028d8: f85d 7b04 ldr.w r7, [sp], #4 + 80028dc: 4770 bx lr + +080028de <LL_C2_RCC_SetAHBPrescaler>: +{ + 80028de: b480 push {r7} + 80028e0: b083 sub sp, #12 + 80028e2: af00 add r7, sp, #0 + 80028e4: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE, Prescaler); + 80028e6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80028ea: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 + 80028ee: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 80028f2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80028f6: 687b ldr r3, [r7, #4] + 80028f8: 4313 orrs r3, r2 + 80028fa: f8c1 3108 str.w r3, [r1, #264] @ 0x108 +} + 80028fe: bf00 nop + 8002900: 370c adds r7, #12 + 8002902: 46bd mov sp, r7 + 8002904: f85d 7b04 ldr.w r7, [sp], #4 + 8002908: 4770 bx lr + +0800290a <LL_RCC_SetAHB4Prescaler>: +{ + 800290a: b480 push {r7} + 800290c: b083 sub sp, #12 + 800290e: af00 add r7, sp, #0 + 8002910: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE, Prescaler >> 4); + 8002912: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002916: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 + 800291a: f023 020f bic.w r2, r3, #15 + 800291e: 687b ldr r3, [r7, #4] + 8002920: 091b lsrs r3, r3, #4 + 8002922: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002926: 4313 orrs r3, r2 + 8002928: f8c1 3108 str.w r3, [r1, #264] @ 0x108 +} + 800292c: bf00 nop + 800292e: 370c adds r7, #12 + 8002930: 46bd mov sp, r7 + 8002932: f85d 7b04 ldr.w r7, [sp], #4 + 8002936: 4770 bx lr + +08002938 <LL_RCC_SetAPB1Prescaler>: +{ + 8002938: b480 push {r7} + 800293a: b083 sub sp, #12 + 800293c: af00 add r7, sp, #0 + 800293e: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); + 8002940: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002944: 689b ldr r3, [r3, #8] + 8002946: f423 62e0 bic.w r2, r3, #1792 @ 0x700 + 800294a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800294e: 687b ldr r3, [r7, #4] + 8002950: 4313 orrs r3, r2 + 8002952: 608b str r3, [r1, #8] +} + 8002954: bf00 nop + 8002956: 370c adds r7, #12 + 8002958: 46bd mov sp, r7 + 800295a: f85d 7b04 ldr.w r7, [sp], #4 + 800295e: 4770 bx lr + +08002960 <LL_RCC_SetAPB2Prescaler>: +{ + 8002960: b480 push {r7} + 8002962: b083 sub sp, #12 + 8002964: af00 add r7, sp, #0 + 8002966: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); + 8002968: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800296c: 689b ldr r3, [r3, #8] + 800296e: f423 5260 bic.w r2, r3, #14336 @ 0x3800 + 8002972: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002976: 687b ldr r3, [r7, #4] + 8002978: 4313 orrs r3, r2 + 800297a: 608b str r3, [r1, #8] +} + 800297c: bf00 nop + 800297e: 370c adds r7, #12 + 8002980: 46bd mov sp, r7 + 8002982: f85d 7b04 ldr.w r7, [sp], #4 + 8002986: 4770 bx lr + +08002988 <LL_RCC_GetAHBPrescaler>: +{ + 8002988: b480 push {r7} + 800298a: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); + 800298c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002990: 689b ldr r3, [r3, #8] + 8002992: f003 03f0 and.w r3, r3, #240 @ 0xf0 +} + 8002996: 4618 mov r0, r3 + 8002998: 46bd mov sp, r7 + 800299a: f85d 7b04 ldr.w r7, [sp], #4 + 800299e: 4770 bx lr + +080029a0 <LL_RCC_GetAHB4Prescaler>: +{ + 80029a0: b480 push {r7} + 80029a2: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE) << 4); + 80029a4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80029a8: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 + 80029ac: 011b lsls r3, r3, #4 + 80029ae: f003 03f0 and.w r3, r3, #240 @ 0xf0 +} + 80029b2: 4618 mov r0, r3 + 80029b4: 46bd mov sp, r7 + 80029b6: f85d 7b04 ldr.w r7, [sp], #4 + 80029ba: 4770 bx lr + +080029bc <LL_RCC_PLL_Enable>: + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + 80029bc: b480 push {r7} + 80029be: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_PLLON); + 80029c0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80029c4: 681b ldr r3, [r3, #0] + 80029c6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80029ca: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 + 80029ce: 6013 str r3, [r2, #0] +} + 80029d0: bf00 nop + 80029d2: 46bd mov sp, r7 + 80029d4: f85d 7b04 ldr.w r7, [sp], #4 + 80029d8: 4770 bx lr + +080029da <LL_RCC_PLL_Disable>: + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + 80029da: b480 push {r7} + 80029dc: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + 80029de: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80029e2: 681b ldr r3, [r3, #0] + 80029e4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80029e8: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 + 80029ec: 6013 str r3, [r2, #0] +} + 80029ee: bf00 nop + 80029f0: 46bd mov sp, r7 + 80029f2: f85d 7b04 ldr.w r7, [sp], #4 + 80029f6: 4770 bx lr + +080029f8 <LL_RCC_PLL_IsReady>: + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + 80029f8: b480 push {r7} + 80029fa: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL); + 80029fc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002a00: 681b ldr r3, [r3, #0] + 8002a02: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8002a06: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 + 8002a0a: d101 bne.n 8002a10 <LL_RCC_PLL_IsReady+0x18> + 8002a0c: 2301 movs r3, #1 + 8002a0e: e000 b.n 8002a12 <LL_RCC_PLL_IsReady+0x1a> + 8002a10: 2300 movs r3, #0 +} + 8002a12: 4618 mov r0, r3 + 8002a14: 46bd mov sp, r7 + 8002a16: f85d 7b04 ldr.w r7, [sp], #4 + 8002a1a: 4770 bx lr + +08002a1c <LL_RCC_PLL_GetN>: + * @brief Get Main PLL multiplication factor for VCO + * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN + * @retval Between 6 and 127 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) +{ + 8002a1c: b480 push {r7} + 8002a1e: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + 8002a20: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002a24: 68db ldr r3, [r3, #12] + 8002a26: 0a1b lsrs r3, r3, #8 + 8002a28: f003 037f and.w r3, r3, #127 @ 0x7f +} + 8002a2c: 4618 mov r0, r3 + 8002a2e: 46bd mov sp, r7 + 8002a30: f85d 7b04 ldr.w r7, [sp], #4 + 8002a34: 4770 bx lr + +08002a36 <LL_RCC_PLL_GetR>: + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @arg @ref LL_RCC_PLLR_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) +{ + 8002a36: b480 push {r7} + 8002a38: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); + 8002a3a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002a3e: 68db ldr r3, [r3, #12] + 8002a40: f003 4360 and.w r3, r3, #3758096384 @ 0xe0000000 +} + 8002a44: 4618 mov r0, r3 + 8002a46: 46bd mov sp, r7 + 8002a48: f85d 7b04 ldr.w r7, [sp], #4 + 8002a4c: 4770 bx lr + +08002a4e <LL_RCC_PLL_GetDivider>: + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) +{ + 8002a4e: b480 push {r7} + 8002a50: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); + 8002a52: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002a56: 68db ldr r3, [r3, #12] + 8002a58: f003 0370 and.w r3, r3, #112 @ 0x70 +} + 8002a5c: 4618 mov r0, r3 + 8002a5e: 46bd mov sp, r7 + 8002a60: f85d 7b04 ldr.w r7, [sp], #4 + 8002a64: 4770 bx lr + +08002a66 <LL_RCC_PLL_GetMainSource>: + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + 8002a66: b480 push {r7} + 8002a68: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); + 8002a6a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002a6e: 68db ldr r3, [r3, #12] + 8002a70: f003 0303 and.w r3, r3, #3 +} + 8002a74: 4618 mov r0, r3 + 8002a76: 46bd mov sp, r7 + 8002a78: f85d 7b04 ldr.w r7, [sp], #4 + 8002a7c: 4770 bx lr + +08002a7e <LL_RCC_IsActiveFlag_HPRE>: + * @brief Check if HCLK1 prescaler flag value has been applied or not + * @rmtoll CFGR HPREF LL_RCC_IsActiveFlag_HPRE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HPRE(void) +{ + 8002a7e: b480 push {r7} + 8002a80: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CFGR, RCC_CFGR_HPREF) == (RCC_CFGR_HPREF)) ? 1UL : 0UL); + 8002a82: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002a86: 689b ldr r3, [r3, #8] + 8002a88: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8002a8c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8002a90: d101 bne.n 8002a96 <LL_RCC_IsActiveFlag_HPRE+0x18> + 8002a92: 2301 movs r3, #1 + 8002a94: e000 b.n 8002a98 <LL_RCC_IsActiveFlag_HPRE+0x1a> + 8002a96: 2300 movs r3, #0 +} + 8002a98: 4618 mov r0, r3 + 8002a9a: 46bd mov sp, r7 + 8002a9c: f85d 7b04 ldr.w r7, [sp], #4 + 8002aa0: 4770 bx lr + +08002aa2 <LL_RCC_IsActiveFlag_C2HPRE>: + * @brief Check if HCLK2 prescaler flag value has been applied or not + * @rmtoll EXTCFGR C2HPREF LL_RCC_IsActiveFlag_C2HPRE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_C2HPRE(void) +{ + 8002aa2: b480 push {r7} + 8002aa4: af00 add r7, sp, #0 + return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPREF) == (RCC_EXTCFGR_C2HPREF)) ? 1UL : 0UL); + 8002aa6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002aaa: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 + 8002aae: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8002ab2: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 + 8002ab6: d101 bne.n 8002abc <LL_RCC_IsActiveFlag_C2HPRE+0x1a> + 8002ab8: 2301 movs r3, #1 + 8002aba: e000 b.n 8002abe <LL_RCC_IsActiveFlag_C2HPRE+0x1c> + 8002abc: 2300 movs r3, #0 +} + 8002abe: 4618 mov r0, r3 + 8002ac0: 46bd mov sp, r7 + 8002ac2: f85d 7b04 ldr.w r7, [sp], #4 + 8002ac6: 4770 bx lr + +08002ac8 <LL_RCC_IsActiveFlag_SHDHPRE>: + * @brief Check if HCLK4 prescaler flag value has been applied or not + * @rmtoll EXTCFGR SHDHPREF LL_RCC_IsActiveFlag_SHDHPRE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHDHPRE(void) +{ + 8002ac8: b480 push {r7} + 8002aca: af00 add r7, sp, #0 + return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPREF) == (RCC_EXTCFGR_SHDHPREF)) ? 1UL : 0UL); + 8002acc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002ad0: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 + 8002ad4: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8002ad8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8002adc: d101 bne.n 8002ae2 <LL_RCC_IsActiveFlag_SHDHPRE+0x1a> + 8002ade: 2301 movs r3, #1 + 8002ae0: e000 b.n 8002ae4 <LL_RCC_IsActiveFlag_SHDHPRE+0x1c> + 8002ae2: 2300 movs r3, #0 +} + 8002ae4: 4618 mov r0, r3 + 8002ae6: 46bd mov sp, r7 + 8002ae8: f85d 7b04 ldr.w r7, [sp], #4 + 8002aec: 4770 bx lr + +08002aee <LL_RCC_IsActiveFlag_PPRE1>: + * @brief Check if PLCK1 prescaler flag value has been applied or not + * @rmtoll CFGR PPRE1F LL_RCC_IsActiveFlag_PPRE1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE1(void) +{ + 8002aee: b480 push {r7} + 8002af0: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1F) == (RCC_CFGR_PPRE1F)) ? 1UL : 0UL); + 8002af2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002af6: 689b ldr r3, [r3, #8] + 8002af8: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8002afc: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 + 8002b00: d101 bne.n 8002b06 <LL_RCC_IsActiveFlag_PPRE1+0x18> + 8002b02: 2301 movs r3, #1 + 8002b04: e000 b.n 8002b08 <LL_RCC_IsActiveFlag_PPRE1+0x1a> + 8002b06: 2300 movs r3, #0 +} + 8002b08: 4618 mov r0, r3 + 8002b0a: 46bd mov sp, r7 + 8002b0c: f85d 7b04 ldr.w r7, [sp], #4 + 8002b10: 4770 bx lr + +08002b12 <LL_RCC_IsActiveFlag_PPRE2>: + * @brief Check if PLCK2 prescaler flag value has been applied or not + * @rmtoll CFGR PPRE2F LL_RCC_IsActiveFlag_PPRE2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE2(void) +{ + 8002b12: b480 push {r7} + 8002b14: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2F) == (RCC_CFGR_PPRE2F)) ? 1UL : 0UL); + 8002b16: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002b1a: 689b ldr r3, [r3, #8] + 8002b1c: f403 2380 and.w r3, r3, #262144 @ 0x40000 + 8002b20: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 + 8002b24: d101 bne.n 8002b2a <LL_RCC_IsActiveFlag_PPRE2+0x18> + 8002b26: 2301 movs r3, #1 + 8002b28: e000 b.n 8002b2c <LL_RCC_IsActiveFlag_PPRE2+0x1a> + 8002b2a: 2300 movs r3, #0 +} + 8002b2c: 4618 mov r0, r3 + 8002b2e: 46bd mov sp, r7 + 8002b30: f85d 7b04 ldr.w r7, [sp], #4 + 8002b34: 4770 bx lr + ... + +08002b38 <HAL_RCC_OscConfig>: + * @note The PLL is not disabled when used as system clock. + * @note The PLL source is not updated when used as PLLSAI1 clock source. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8002b38: b590 push {r4, r7, lr} + 8002b3a: b08d sub sp, #52 @ 0x34 + 8002b3c: af00 add r7, sp, #0 + 8002b3e: 6078 str r0, [r7, #4] + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + 8002b40: 687b ldr r3, [r7, #4] + 8002b42: 2b00 cmp r3, #0 + 8002b44: d101 bne.n 8002b4a <HAL_RCC_OscConfig+0x12> + { + return HAL_ERROR; + 8002b46: 2301 movs r3, #1 + 8002b48: e363 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*----------------------------- MSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + 8002b4a: 687b ldr r3, [r7, #4] + 8002b4c: 681b ldr r3, [r3, #0] + 8002b4e: f003 0320 and.w r3, r3, #32 + 8002b52: 2b00 cmp r3, #0 + 8002b54: f000 808d beq.w 8002c72 <HAL_RCC_OscConfig+0x13a> + assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); + assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* When the MSI is used as system clock it will not be disabled */ + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8002b58: f7ff fea1 bl 800289e <LL_RCC_GetSysClkSource> + 8002b5c: 62f8 str r0, [r7, #44] @ 0x2c + const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE(); + 8002b5e: f7ff ff82 bl 8002a66 <LL_RCC_PLL_GetMainSource> + 8002b62: 62b8 str r0, [r7, #40] @ 0x28 + if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_MSI) || + 8002b64: 6afb ldr r3, [r7, #44] @ 0x2c + 8002b66: 2b00 cmp r3, #0 + 8002b68: d005 beq.n 8002b76 <HAL_RCC_OscConfig+0x3e> + 8002b6a: 6afb ldr r3, [r7, #44] @ 0x2c + 8002b6c: 2b0c cmp r3, #12 + 8002b6e: d147 bne.n 8002c00 <HAL_RCC_OscConfig+0xc8> + ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_MSI))) + 8002b70: 6abb ldr r3, [r7, #40] @ 0x28 + 8002b72: 2b01 cmp r3, #1 + 8002b74: d144 bne.n 8002c00 <HAL_RCC_OscConfig+0xc8> + { + if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF) + 8002b76: 687b ldr r3, [r7, #4] + 8002b78: 69db ldr r3, [r3, #28] + 8002b7a: 2b00 cmp r3, #0 + 8002b7c: d101 bne.n 8002b82 <HAL_RCC_OscConfig+0x4a> + { + return HAL_ERROR; + 8002b7e: 2301 movs r3, #1 + 8002b80: e347 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + else + { + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the AHB4 clock + and the supply voltage of the device. */ + if (RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) + 8002b82: 687b ldr r3, [r7, #4] + 8002b84: 6a5c ldr r4, [r3, #36] @ 0x24 + 8002b86: f7ff fe4c bl 8002822 <LL_RCC_MSI_GetRange> + 8002b8a: 4603 mov r3, r0 + 8002b8c: 429c cmp r4, r3 + 8002b8e: d914 bls.n 8002bba <HAL_RCC_OscConfig+0x82> + { + /* First increase number of wait states update if necessary */ + if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 8002b90: 687b ldr r3, [r7, #4] + 8002b92: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002b94: 4618 mov r0, r3 + 8002b96: f000 fd03 bl 80035a0 <RCC_SetFlashLatencyFromMSIRange> + 8002b9a: 4603 mov r3, r0 + 8002b9c: 2b00 cmp r3, #0 + 8002b9e: d001 beq.n 8002ba4 <HAL_RCC_OscConfig+0x6c> + { + return HAL_ERROR; + 8002ba0: 2301 movs r3, #1 + 8002ba2: e336 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + } + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8002ba4: 687b ldr r3, [r7, #4] + 8002ba6: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002ba8: 4618 mov r0, r3 + 8002baa: f7ff fe26 bl 80027fa <LL_RCC_MSI_SetRange> + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8002bae: 687b ldr r3, [r7, #4] + 8002bb0: 6a1b ldr r3, [r3, #32] + 8002bb2: 4618 mov r0, r3 + 8002bb4: f7ff fe4a bl 800284c <LL_RCC_MSI_SetCalibTrimming> + 8002bb8: e013 b.n 8002be2 <HAL_RCC_OscConfig+0xaa> + } + else + { + /* Else, keep current flash latency while decreasing applies */ + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8002bba: 687b ldr r3, [r7, #4] + 8002bbc: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002bbe: 4618 mov r0, r3 + 8002bc0: f7ff fe1b bl 80027fa <LL_RCC_MSI_SetRange> + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8002bc4: 687b ldr r3, [r7, #4] + 8002bc6: 6a1b ldr r3, [r3, #32] + 8002bc8: 4618 mov r0, r3 + 8002bca: f7ff fe3f bl 800284c <LL_RCC_MSI_SetCalibTrimming> + + /* Decrease number of wait states update if necessary */ + if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 8002bce: 687b ldr r3, [r7, #4] + 8002bd0: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002bd2: 4618 mov r0, r3 + 8002bd4: f000 fce4 bl 80035a0 <RCC_SetFlashLatencyFromMSIRange> + 8002bd8: 4603 mov r3, r0 + 8002bda: 2b00 cmp r3, #0 + 8002bdc: d001 beq.n 8002be2 <HAL_RCC_OscConfig+0xaa> + { + return HAL_ERROR; + 8002bde: 2301 movs r3, #1 + 8002be0: e317 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetHCLKFreq(); + 8002be2: f000 fcc9 bl 8003578 <HAL_RCC_GetHCLKFreq> + 8002be6: 4603 mov r3, r0 + 8002be8: 4aa4 ldr r2, [pc, #656] @ (8002e7c <HAL_RCC_OscConfig+0x344>) + 8002bea: 6013 str r3, [r2, #0] + + if (HAL_InitTick(uwTickPrio) != HAL_OK) + 8002bec: 4ba4 ldr r3, [pc, #656] @ (8002e80 <HAL_RCC_OscConfig+0x348>) + 8002bee: 681b ldr r3, [r3, #0] + 8002bf0: 4618 mov r0, r3 + 8002bf2: f7fe fe89 bl 8001908 <HAL_InitTick> + 8002bf6: 4603 mov r3, r0 + 8002bf8: 2b00 cmp r3, #0 + 8002bfa: d039 beq.n 8002c70 <HAL_RCC_OscConfig+0x138> + { + return HAL_ERROR; + 8002bfc: 2301 movs r3, #1 + 8002bfe: e308 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + } + } + else + { + /* Check the MSI State */ + if (RCC_OscInitStruct->MSIState != RCC_MSI_OFF) + 8002c00: 687b ldr r3, [r7, #4] + 8002c02: 69db ldr r3, [r3, #28] + 8002c04: 2b00 cmp r3, #0 + 8002c06: d01e beq.n 8002c46 <HAL_RCC_OscConfig+0x10e> + { + /* Enable the Internal High Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + 8002c08: f7ff fdc8 bl 800279c <LL_RCC_MSI_Enable> + + /* Get timeout */ + tickstart = HAL_GetTick(); + 8002c0c: f7fe feca bl 80019a4 <HAL_GetTick> + 8002c10: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till MSI is ready */ + while (LL_RCC_MSI_IsReady() == 0U) + 8002c12: e008 b.n 8002c26 <HAL_RCC_OscConfig+0xee> + { + if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 8002c14: f7fe fec6 bl 80019a4 <HAL_GetTick> + 8002c18: 4602 mov r2, r0 + 8002c1a: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002c1c: 1ad3 subs r3, r2, r3 + 8002c1e: 2b02 cmp r3, #2 + 8002c20: d901 bls.n 8002c26 <HAL_RCC_OscConfig+0xee> + { + return HAL_TIMEOUT; + 8002c22: 2303 movs r3, #3 + 8002c24: e2f5 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_MSI_IsReady() == 0U) + 8002c26: f7ff fdd7 bl 80027d8 <LL_RCC_MSI_IsReady> + 8002c2a: 4603 mov r3, r0 + 8002c2c: 2b00 cmp r3, #0 + 8002c2e: d0f1 beq.n 8002c14 <HAL_RCC_OscConfig+0xdc> + } + } + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8002c30: 687b ldr r3, [r7, #4] + 8002c32: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002c34: 4618 mov r0, r3 + 8002c36: f7ff fde0 bl 80027fa <LL_RCC_MSI_SetRange> + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8002c3a: 687b ldr r3, [r7, #4] + 8002c3c: 6a1b ldr r3, [r3, #32] + 8002c3e: 4618 mov r0, r3 + 8002c40: f7ff fe04 bl 800284c <LL_RCC_MSI_SetCalibTrimming> + 8002c44: e015 b.n 8002c72 <HAL_RCC_OscConfig+0x13a> + + } + else + { + /* Disable the Internal High Speed oscillator (MSI). */ + __HAL_RCC_MSI_DISABLE(); + 8002c46: f7ff fdb8 bl 80027ba <LL_RCC_MSI_Disable> + + /* Get timeout */ + tickstart = HAL_GetTick(); + 8002c4a: f7fe feab bl 80019a4 <HAL_GetTick> + 8002c4e: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till MSI is disabled */ + while (LL_RCC_MSI_IsReady() != 0U) + 8002c50: e008 b.n 8002c64 <HAL_RCC_OscConfig+0x12c> + { + if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 8002c52: f7fe fea7 bl 80019a4 <HAL_GetTick> + 8002c56: 4602 mov r2, r0 + 8002c58: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002c5a: 1ad3 subs r3, r2, r3 + 8002c5c: 2b02 cmp r3, #2 + 8002c5e: d901 bls.n 8002c64 <HAL_RCC_OscConfig+0x12c> + { + return HAL_TIMEOUT; + 8002c60: 2303 movs r3, #3 + 8002c62: e2d6 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_MSI_IsReady() != 0U) + 8002c64: f7ff fdb8 bl 80027d8 <LL_RCC_MSI_IsReady> + 8002c68: 4603 mov r3, r0 + 8002c6a: 2b00 cmp r3, #0 + 8002c6c: d1f1 bne.n 8002c52 <HAL_RCC_OscConfig+0x11a> + 8002c6e: e000 b.n 8002c72 <HAL_RCC_OscConfig+0x13a> + if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF) + 8002c70: bf00 nop + } + } + } + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 8002c72: 687b ldr r3, [r7, #4] + 8002c74: 681b ldr r3, [r3, #0] + 8002c76: f003 0301 and.w r3, r3, #1 + 8002c7a: 2b00 cmp r3, #0 + 8002c7c: d047 beq.n 8002d0e <HAL_RCC_OscConfig+0x1d6> + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8002c7e: f7ff fe0e bl 800289e <LL_RCC_GetSysClkSource> + 8002c82: 6238 str r0, [r7, #32] + const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE(); + 8002c84: f7ff feef bl 8002a66 <LL_RCC_PLL_GetMainSource> + 8002c88: 61f8 str r0, [r7, #28] + if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE) || + 8002c8a: 6a3b ldr r3, [r7, #32] + 8002c8c: 2b08 cmp r3, #8 + 8002c8e: d005 beq.n 8002c9c <HAL_RCC_OscConfig+0x164> + 8002c90: 6a3b ldr r3, [r7, #32] + 8002c92: 2b0c cmp r3, #12 + 8002c94: d108 bne.n 8002ca8 <HAL_RCC_OscConfig+0x170> + ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_HSE))) + 8002c96: 69fb ldr r3, [r7, #28] + 8002c98: 2b03 cmp r3, #3 + 8002c9a: d105 bne.n 8002ca8 <HAL_RCC_OscConfig+0x170> + { + if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF) + 8002c9c: 687b ldr r3, [r7, #4] + 8002c9e: 685b ldr r3, [r3, #4] + 8002ca0: 2b00 cmp r3, #0 + 8002ca2: d134 bne.n 8002d0e <HAL_RCC_OscConfig+0x1d6> + { + return HAL_ERROR; + 8002ca4: 2301 movs r3, #1 + 8002ca6: e2b4 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 8002ca8: 687b ldr r3, [r7, #4] + 8002caa: 685b ldr r3, [r3, #4] + 8002cac: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8002cb0: d102 bne.n 8002cb8 <HAL_RCC_OscConfig+0x180> + 8002cb2: f7ff fbf5 bl 80024a0 <LL_RCC_HSE_Enable> + 8002cb6: e001 b.n 8002cbc <HAL_RCC_OscConfig+0x184> + 8002cb8: f7ff fc01 bl 80024be <LL_RCC_HSE_Disable> + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 8002cbc: 687b ldr r3, [r7, #4] + 8002cbe: 685b ldr r3, [r3, #4] + 8002cc0: 2b00 cmp r3, #0 + 8002cc2: d012 beq.n 8002cea <HAL_RCC_OscConfig+0x1b2> + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002cc4: f7fe fe6e bl 80019a4 <HAL_GetTick> + 8002cc8: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till HSE is ready */ + while (LL_RCC_HSE_IsReady() == 0U) + 8002cca: e008 b.n 8002cde <HAL_RCC_OscConfig+0x1a6> + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 8002ccc: f7fe fe6a bl 80019a4 <HAL_GetTick> + 8002cd0: 4602 mov r2, r0 + 8002cd2: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002cd4: 1ad3 subs r3, r2, r3 + 8002cd6: 2b64 cmp r3, #100 @ 0x64 + 8002cd8: d901 bls.n 8002cde <HAL_RCC_OscConfig+0x1a6> + { + return HAL_TIMEOUT; + 8002cda: 2303 movs r3, #3 + 8002cdc: e299 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_HSE_IsReady() == 0U) + 8002cde: f7ff fbfd bl 80024dc <LL_RCC_HSE_IsReady> + 8002ce2: 4603 mov r3, r0 + 8002ce4: 2b00 cmp r3, #0 + 8002ce6: d0f1 beq.n 8002ccc <HAL_RCC_OscConfig+0x194> + 8002ce8: e011 b.n 8002d0e <HAL_RCC_OscConfig+0x1d6> + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002cea: f7fe fe5b bl 80019a4 <HAL_GetTick> + 8002cee: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till HSE is disabled */ + while (LL_RCC_HSE_IsReady() != 0U) + 8002cf0: e008 b.n 8002d04 <HAL_RCC_OscConfig+0x1cc> + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 8002cf2: f7fe fe57 bl 80019a4 <HAL_GetTick> + 8002cf6: 4602 mov r2, r0 + 8002cf8: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002cfa: 1ad3 subs r3, r2, r3 + 8002cfc: 2b64 cmp r3, #100 @ 0x64 + 8002cfe: d901 bls.n 8002d04 <HAL_RCC_OscConfig+0x1cc> + { + return HAL_TIMEOUT; + 8002d00: 2303 movs r3, #3 + 8002d02: e286 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_HSE_IsReady() != 0U) + 8002d04: f7ff fbea bl 80024dc <LL_RCC_HSE_IsReady> + 8002d08: 4603 mov r3, r0 + 8002d0a: 2b00 cmp r3, #0 + 8002d0c: d1f1 bne.n 8002cf2 <HAL_RCC_OscConfig+0x1ba> + } + } + } + + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 8002d0e: 687b ldr r3, [r7, #4] + 8002d10: 681b ldr r3, [r3, #0] + 8002d12: f003 0302 and.w r3, r3, #2 + 8002d16: 2b00 cmp r3, #0 + 8002d18: d04c beq.n 8002db4 <HAL_RCC_OscConfig+0x27c> + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8002d1a: f7ff fdc0 bl 800289e <LL_RCC_GetSysClkSource> + 8002d1e: 61b8 str r0, [r7, #24] + const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE(); + 8002d20: f7ff fea1 bl 8002a66 <LL_RCC_PLL_GetMainSource> + 8002d24: 6178 str r0, [r7, #20] + if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) || + 8002d26: 69bb ldr r3, [r7, #24] + 8002d28: 2b04 cmp r3, #4 + 8002d2a: d005 beq.n 8002d38 <HAL_RCC_OscConfig+0x200> + 8002d2c: 69bb ldr r3, [r7, #24] + 8002d2e: 2b0c cmp r3, #12 + 8002d30: d10e bne.n 8002d50 <HAL_RCC_OscConfig+0x218> + ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_HSI))) + 8002d32: 697b ldr r3, [r7, #20] + 8002d34: 2b02 cmp r3, #2 + 8002d36: d10b bne.n 8002d50 <HAL_RCC_OscConfig+0x218> + { + /* When HSI is used as system clock it will not be disabled */ + if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) + 8002d38: 687b ldr r3, [r7, #4] + 8002d3a: 68db ldr r3, [r3, #12] + 8002d3c: 2b00 cmp r3, #0 + 8002d3e: d101 bne.n 8002d44 <HAL_RCC_OscConfig+0x20c> + { + return HAL_ERROR; + 8002d40: 2301 movs r3, #1 + 8002d42: e266 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8002d44: 687b ldr r3, [r7, #4] + 8002d46: 691b ldr r3, [r3, #16] + 8002d48: 4618 mov r0, r3 + 8002d4a: f7ff fc09 bl 8002560 <LL_RCC_HSI_SetCalibTrimming> + if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) + 8002d4e: e031 b.n 8002db4 <HAL_RCC_OscConfig+0x27c> + } + } + else + { + /* Check the HSI State */ + if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 8002d50: 687b ldr r3, [r7, #4] + 8002d52: 68db ldr r3, [r3, #12] + 8002d54: 2b00 cmp r3, #0 + 8002d56: d019 beq.n 8002d8c <HAL_RCC_OscConfig+0x254> + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 8002d58: f7ff fbd2 bl 8002500 <LL_RCC_HSI_Enable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002d5c: f7fe fe22 bl 80019a4 <HAL_GetTick> + 8002d60: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till HSI is ready */ + while (LL_RCC_HSI_IsReady() == 0U) + 8002d62: e008 b.n 8002d76 <HAL_RCC_OscConfig+0x23e> + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 8002d64: f7fe fe1e bl 80019a4 <HAL_GetTick> + 8002d68: 4602 mov r2, r0 + 8002d6a: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002d6c: 1ad3 subs r3, r2, r3 + 8002d6e: 2b02 cmp r3, #2 + 8002d70: d901 bls.n 8002d76 <HAL_RCC_OscConfig+0x23e> + { + return HAL_TIMEOUT; + 8002d72: 2303 movs r3, #3 + 8002d74: e24d b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_HSI_IsReady() == 0U) + 8002d76: f7ff fbe1 bl 800253c <LL_RCC_HSI_IsReady> + 8002d7a: 4603 mov r3, r0 + 8002d7c: 2b00 cmp r3, #0 + 8002d7e: d0f1 beq.n 8002d64 <HAL_RCC_OscConfig+0x22c> + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8002d80: 687b ldr r3, [r7, #4] + 8002d82: 691b ldr r3, [r3, #16] + 8002d84: 4618 mov r0, r3 + 8002d86: f7ff fbeb bl 8002560 <LL_RCC_HSI_SetCalibTrimming> + 8002d8a: e013 b.n 8002db4 <HAL_RCC_OscConfig+0x27c> + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 8002d8c: f7ff fbc7 bl 800251e <LL_RCC_HSI_Disable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002d90: f7fe fe08 bl 80019a4 <HAL_GetTick> + 8002d94: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till HSI is disabled */ + while (LL_RCC_HSI_IsReady() != 0U) + 8002d96: e008 b.n 8002daa <HAL_RCC_OscConfig+0x272> + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 8002d98: f7fe fe04 bl 80019a4 <HAL_GetTick> + 8002d9c: 4602 mov r2, r0 + 8002d9e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002da0: 1ad3 subs r3, r2, r3 + 8002da2: 2b02 cmp r3, #2 + 8002da4: d901 bls.n 8002daa <HAL_RCC_OscConfig+0x272> + { + return HAL_TIMEOUT; + 8002da6: 2303 movs r3, #3 + 8002da8: e233 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_HSI_IsReady() != 0U) + 8002daa: f7ff fbc7 bl 800253c <LL_RCC_HSI_IsReady> + 8002dae: 4603 mov r3, r0 + 8002db0: 2b00 cmp r3, #0 + 8002db2: d1f1 bne.n 8002d98 <HAL_RCC_OscConfig+0x260> + } + } + } + /*------------------------------ LSI Configuration (LSI1 or LSI2) -------------------------*/ + + if ((((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \ + 8002db4: 687b ldr r3, [r7, #4] + 8002db6: 681b ldr r3, [r3, #0] + 8002db8: f003 0308 and.w r3, r3, #8 + 8002dbc: 2b00 cmp r3, #0 + 8002dbe: d106 bne.n 8002dce <HAL_RCC_OscConfig+0x296> + (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2)) + 8002dc0: 687b ldr r3, [r7, #4] + 8002dc2: 681b ldr r3, [r3, #0] + 8002dc4: f003 0310 and.w r3, r3, #16 + if ((((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \ + 8002dc8: 2b00 cmp r3, #0 + 8002dca: f000 80a3 beq.w 8002f14 <HAL_RCC_OscConfig+0x3dc> + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 8002dce: 687b ldr r3, [r7, #4] + 8002dd0: 695b ldr r3, [r3, #20] + 8002dd2: 2b00 cmp r3, #0 + 8002dd4: d076 beq.n 8002ec4 <HAL_RCC_OscConfig+0x38c> + { + /*------------------------------ LSI2 selected by default (when Switch ON) -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2) + 8002dd6: 687b ldr r3, [r7, #4] + 8002dd8: 681b ldr r3, [r3, #0] + 8002dda: f003 0310 and.w r3, r3, #16 + 8002dde: 2b00 cmp r3, #0 + 8002de0: d046 beq.n 8002e70 <HAL_RCC_OscConfig+0x338> + { + assert_param(IS_RCC_LSI2_CALIBRATION_VALUE(RCC_OscInitStruct->LSI2CalibrationValue)); + + /* 1. Check LSI1 state and enable if required */ + if (LL_RCC_LSI1_IsReady() == 0U) + 8002de2: f7ff fc7e bl 80026e2 <LL_RCC_LSI1_IsReady> + 8002de6: 4603 mov r3, r0 + 8002de8: 2b00 cmp r3, #0 + 8002dea: d113 bne.n 8002e14 <HAL_RCC_OscConfig+0x2dc> + { + /* This is required to enable LSI1 before enabling LSI2 */ + __HAL_RCC_LSI1_ENABLE(); + 8002dec: f7ff fc57 bl 800269e <LL_RCC_LSI1_Enable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002df0: f7fe fdd8 bl 80019a4 <HAL_GetTick> + 8002df4: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till LSI1 is ready */ + while (LL_RCC_LSI1_IsReady() == 0U) + 8002df6: e008 b.n 8002e0a <HAL_RCC_OscConfig+0x2d2> + { + if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE) + 8002df8: f7fe fdd4 bl 80019a4 <HAL_GetTick> + 8002dfc: 4602 mov r2, r0 + 8002dfe: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002e00: 1ad3 subs r3, r2, r3 + 8002e02: 2b02 cmp r3, #2 + 8002e04: d901 bls.n 8002e0a <HAL_RCC_OscConfig+0x2d2> + { + return HAL_TIMEOUT; + 8002e06: 2303 movs r3, #3 + 8002e08: e203 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_LSI1_IsReady() == 0U) + 8002e0a: f7ff fc6a bl 80026e2 <LL_RCC_LSI1_IsReady> + 8002e0e: 4603 mov r3, r0 + 8002e10: 2b00 cmp r3, #0 + 8002e12: d0f1 beq.n 8002df8 <HAL_RCC_OscConfig+0x2c0> + } + } + } + + /* 2. Enable the Internal Low Speed oscillator (LSI2) and set trimming value */ + __HAL_RCC_LSI2_ENABLE(); + 8002e14: f7ff fc77 bl 8002706 <LL_RCC_LSI2_Enable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002e18: f7fe fdc4 bl 80019a4 <HAL_GetTick> + 8002e1c: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till LSI2 is ready */ + while (LL_RCC_LSI2_IsReady() == 0U) + 8002e1e: e008 b.n 8002e32 <HAL_RCC_OscConfig+0x2fa> + { + if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE) + 8002e20: f7fe fdc0 bl 80019a4 <HAL_GetTick> + 8002e24: 4602 mov r2, r0 + 8002e26: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002e28: 1ad3 subs r3, r2, r3 + 8002e2a: 2b03 cmp r3, #3 + 8002e2c: d901 bls.n 8002e32 <HAL_RCC_OscConfig+0x2fa> + { + return HAL_TIMEOUT; + 8002e2e: 2303 movs r3, #3 + 8002e30: e1ef b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_LSI2_IsReady() == 0U) + 8002e32: f7ff fc8a bl 800274a <LL_RCC_LSI2_IsReady> + 8002e36: 4603 mov r3, r0 + 8002e38: 2b00 cmp r3, #0 + 8002e3a: d0f1 beq.n 8002e20 <HAL_RCC_OscConfig+0x2e8> + } + } + /* Adjusts the Internal Low Spee oscillator (LSI2) calibration value */ + __HAL_RCC_LSI2_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->LSI2CalibrationValue); + 8002e3c: 687b ldr r3, [r7, #4] + 8002e3e: 699b ldr r3, [r3, #24] + 8002e40: 4618 mov r0, r3 + 8002e42: f7ff fc94 bl 800276e <LL_RCC_LSI2_SetTrimming> + + /* 3. Disable LSI1 */ + + /* LSI1 was initially not enable, require to disable it */ + __HAL_RCC_LSI1_DISABLE(); + 8002e46: f7ff fc3b bl 80026c0 <LL_RCC_LSI1_Disable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002e4a: f7fe fdab bl 80019a4 <HAL_GetTick> + 8002e4e: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till LSI1 is disabled */ + while (LL_RCC_LSI1_IsReady() != 0U) + 8002e50: e008 b.n 8002e64 <HAL_RCC_OscConfig+0x32c> + { + if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE) + 8002e52: f7fe fda7 bl 80019a4 <HAL_GetTick> + 8002e56: 4602 mov r2, r0 + 8002e58: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002e5a: 1ad3 subs r3, r2, r3 + 8002e5c: 2b02 cmp r3, #2 + 8002e5e: d901 bls.n 8002e64 <HAL_RCC_OscConfig+0x32c> + { + return HAL_TIMEOUT; + 8002e60: 2303 movs r3, #3 + 8002e62: e1d6 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_LSI1_IsReady() != 0U) + 8002e64: f7ff fc3d bl 80026e2 <LL_RCC_LSI1_IsReady> + 8002e68: 4603 mov r3, r0 + 8002e6a: 2b00 cmp r3, #0 + 8002e6c: d1f1 bne.n 8002e52 <HAL_RCC_OscConfig+0x31a> + 8002e6e: e051 b.n 8002f14 <HAL_RCC_OscConfig+0x3dc> + else + { + /*------------------------------ LSI1 selected (only if LSI2 OFF)-------------------------*/ + + /* 1. Enable the Internal Low Speed oscillator (LSI1). */ + __HAL_RCC_LSI1_ENABLE(); + 8002e70: f7ff fc15 bl 800269e <LL_RCC_LSI1_Enable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002e74: f7fe fd96 bl 80019a4 <HAL_GetTick> + 8002e78: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till LSI1 is ready */ + while (LL_RCC_LSI1_IsReady() == 0U) + 8002e7a: e00c b.n 8002e96 <HAL_RCC_OscConfig+0x35e> + 8002e7c: 20000008 .word 0x20000008 + 8002e80: 2000000c .word 0x2000000c + { + if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE) + 8002e84: f7fe fd8e bl 80019a4 <HAL_GetTick> + 8002e88: 4602 mov r2, r0 + 8002e8a: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002e8c: 1ad3 subs r3, r2, r3 + 8002e8e: 2b02 cmp r3, #2 + 8002e90: d901 bls.n 8002e96 <HAL_RCC_OscConfig+0x35e> + { + return HAL_TIMEOUT; + 8002e92: 2303 movs r3, #3 + 8002e94: e1bd b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_LSI1_IsReady() == 0U) + 8002e96: f7ff fc24 bl 80026e2 <LL_RCC_LSI1_IsReady> + 8002e9a: 4603 mov r3, r0 + 8002e9c: 2b00 cmp r3, #0 + 8002e9e: d0f1 beq.n 8002e84 <HAL_RCC_OscConfig+0x34c> + } + } + /*2. Switch OFF LSI2*/ + + /* Disable the Internal Low Speed oscillator (LSI2). */ + __HAL_RCC_LSI2_DISABLE(); + 8002ea0: f7ff fc42 bl 8002728 <LL_RCC_LSI2_Disable> + + /* Wait till LSI2 is disabled */ + while (LL_RCC_LSI2_IsReady() != 0U) + 8002ea4: e008 b.n 8002eb8 <HAL_RCC_OscConfig+0x380> + { + if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE) + 8002ea6: f7fe fd7d bl 80019a4 <HAL_GetTick> + 8002eaa: 4602 mov r2, r0 + 8002eac: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002eae: 1ad3 subs r3, r2, r3 + 8002eb0: 2b03 cmp r3, #3 + 8002eb2: d901 bls.n 8002eb8 <HAL_RCC_OscConfig+0x380> + { + return HAL_TIMEOUT; + 8002eb4: 2303 movs r3, #3 + 8002eb6: e1ac b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_LSI2_IsReady() != 0U) + 8002eb8: f7ff fc47 bl 800274a <LL_RCC_LSI2_IsReady> + 8002ebc: 4603 mov r3, r0 + 8002ebe: 2b00 cmp r3, #0 + 8002ec0: d1f1 bne.n 8002ea6 <HAL_RCC_OscConfig+0x36e> + 8002ec2: e027 b.n 8002f14 <HAL_RCC_OscConfig+0x3dc> + } + else + { + + /* Disable the Internal Low Speed oscillator (LSI2). */ + __HAL_RCC_LSI2_DISABLE(); + 8002ec4: f7ff fc30 bl 8002728 <LL_RCC_LSI2_Disable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002ec8: f7fe fd6c bl 80019a4 <HAL_GetTick> + 8002ecc: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till LSI2 is disabled */ + while (LL_RCC_LSI2_IsReady() != 0U) + 8002ece: e008 b.n 8002ee2 <HAL_RCC_OscConfig+0x3aa> + { + if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE) + 8002ed0: f7fe fd68 bl 80019a4 <HAL_GetTick> + 8002ed4: 4602 mov r2, r0 + 8002ed6: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002ed8: 1ad3 subs r3, r2, r3 + 8002eda: 2b03 cmp r3, #3 + 8002edc: d901 bls.n 8002ee2 <HAL_RCC_OscConfig+0x3aa> + { + return HAL_TIMEOUT; + 8002ede: 2303 movs r3, #3 + 8002ee0: e197 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_LSI2_IsReady() != 0U) + 8002ee2: f7ff fc32 bl 800274a <LL_RCC_LSI2_IsReady> + 8002ee6: 4603 mov r3, r0 + 8002ee8: 2b00 cmp r3, #0 + 8002eea: d1f1 bne.n 8002ed0 <HAL_RCC_OscConfig+0x398> + } + } + + /* Disable the Internal Low Speed oscillator (LSI1). */ + __HAL_RCC_LSI1_DISABLE(); + 8002eec: f7ff fbe8 bl 80026c0 <LL_RCC_LSI1_Disable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002ef0: f7fe fd58 bl 80019a4 <HAL_GetTick> + 8002ef4: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till LSI1 is disabled */ + while (LL_RCC_LSI1_IsReady() != 0U) + 8002ef6: e008 b.n 8002f0a <HAL_RCC_OscConfig+0x3d2> + { + if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE) + 8002ef8: f7fe fd54 bl 80019a4 <HAL_GetTick> + 8002efc: 4602 mov r2, r0 + 8002efe: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002f00: 1ad3 subs r3, r2, r3 + 8002f02: 2b02 cmp r3, #2 + 8002f04: d901 bls.n 8002f0a <HAL_RCC_OscConfig+0x3d2> + { + return HAL_TIMEOUT; + 8002f06: 2303 movs r3, #3 + 8002f08: e183 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_LSI1_IsReady() != 0U) + 8002f0a: f7ff fbea bl 80026e2 <LL_RCC_LSI1_IsReady> + 8002f0e: 4603 mov r3, r0 + 8002f10: 2b00 cmp r3, #0 + 8002f12: d1f1 bne.n 8002ef8 <HAL_RCC_OscConfig+0x3c0> + } + } + } + + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 8002f14: 687b ldr r3, [r7, #4] + 8002f16: 681b ldr r3, [r3, #0] + 8002f18: f003 0304 and.w r3, r3, #4 + 8002f1c: 2b00 cmp r3, #0 + 8002f1e: d05b beq.n 8002fd8 <HAL_RCC_OscConfig+0x4a0> + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + + if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 8002f20: 4ba7 ldr r3, [pc, #668] @ (80031c0 <HAL_RCC_OscConfig+0x688>) + 8002f22: 681b ldr r3, [r3, #0] + 8002f24: f403 7380 and.w r3, r3, #256 @ 0x100 + 8002f28: 2b00 cmp r3, #0 + 8002f2a: d114 bne.n 8002f56 <HAL_RCC_OscConfig+0x41e> + { + /* Enable write access to Backup domain */ + HAL_PWR_EnableBkUpAccess(); + 8002f2c: f7ff fa5c bl 80023e8 <HAL_PWR_EnableBkUpAccess> + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8002f30: f7fe fd38 bl 80019a4 <HAL_GetTick> + 8002f34: 6278 str r0, [r7, #36] @ 0x24 + + while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 8002f36: e008 b.n 8002f4a <HAL_RCC_OscConfig+0x412> + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8002f38: f7fe fd34 bl 80019a4 <HAL_GetTick> + 8002f3c: 4602 mov r2, r0 + 8002f3e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002f40: 1ad3 subs r3, r2, r3 + 8002f42: 2b02 cmp r3, #2 + 8002f44: d901 bls.n 8002f4a <HAL_RCC_OscConfig+0x412> + { + return HAL_TIMEOUT; + 8002f46: 2303 movs r3, #3 + 8002f48: e163 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 8002f4a: 4b9d ldr r3, [pc, #628] @ (80031c0 <HAL_RCC_OscConfig+0x688>) + 8002f4c: 681b ldr r3, [r3, #0] + 8002f4e: f403 7380 and.w r3, r3, #256 @ 0x100 + 8002f52: 2b00 cmp r3, #0 + 8002f54: d0f0 beq.n 8002f38 <HAL_RCC_OscConfig+0x400> + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 8002f56: 687b ldr r3, [r7, #4] + 8002f58: 689b ldr r3, [r3, #8] + 8002f5a: 2b01 cmp r3, #1 + 8002f5c: d102 bne.n 8002f64 <HAL_RCC_OscConfig+0x42c> + 8002f5e: f7ff fb48 bl 80025f2 <LL_RCC_LSE_Enable> + 8002f62: e00c b.n 8002f7e <HAL_RCC_OscConfig+0x446> + 8002f64: 687b ldr r3, [r7, #4] + 8002f66: 689b ldr r3, [r3, #8] + 8002f68: 2b05 cmp r3, #5 + 8002f6a: d104 bne.n 8002f76 <HAL_RCC_OscConfig+0x43e> + 8002f6c: f7ff fb63 bl 8002636 <LL_RCC_LSE_EnableBypass> + 8002f70: f7ff fb3f bl 80025f2 <LL_RCC_LSE_Enable> + 8002f74: e003 b.n 8002f7e <HAL_RCC_OscConfig+0x446> + 8002f76: f7ff fb4d bl 8002614 <LL_RCC_LSE_Disable> + 8002f7a: f7ff fb6d bl 8002658 <LL_RCC_LSE_DisableBypass> + + /* Check the LSE State */ + if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 8002f7e: 687b ldr r3, [r7, #4] + 8002f80: 689b ldr r3, [r3, #8] + 8002f82: 2b00 cmp r3, #0 + 8002f84: d014 beq.n 8002fb0 <HAL_RCC_OscConfig+0x478> + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002f86: f7fe fd0d bl 80019a4 <HAL_GetTick> + 8002f8a: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till LSE is ready */ + while (LL_RCC_LSE_IsReady() == 0U) + 8002f8c: e00a b.n 8002fa4 <HAL_RCC_OscConfig+0x46c> + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8002f8e: f7fe fd09 bl 80019a4 <HAL_GetTick> + 8002f92: 4602 mov r2, r0 + 8002f94: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002f96: 1ad3 subs r3, r2, r3 + 8002f98: f241 3288 movw r2, #5000 @ 0x1388 + 8002f9c: 4293 cmp r3, r2 + 8002f9e: d901 bls.n 8002fa4 <HAL_RCC_OscConfig+0x46c> + { + return HAL_TIMEOUT; + 8002fa0: 2303 movs r3, #3 + 8002fa2: e136 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_LSE_IsReady() == 0U) + 8002fa4: f7ff fb69 bl 800267a <LL_RCC_LSE_IsReady> + 8002fa8: 4603 mov r3, r0 + 8002faa: 2b00 cmp r3, #0 + 8002fac: d0ef beq.n 8002f8e <HAL_RCC_OscConfig+0x456> + 8002fae: e013 b.n 8002fd8 <HAL_RCC_OscConfig+0x4a0> + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002fb0: f7fe fcf8 bl 80019a4 <HAL_GetTick> + 8002fb4: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till LSE is disabled */ + while (LL_RCC_LSE_IsReady() != 0U) + 8002fb6: e00a b.n 8002fce <HAL_RCC_OscConfig+0x496> + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8002fb8: f7fe fcf4 bl 80019a4 <HAL_GetTick> + 8002fbc: 4602 mov r2, r0 + 8002fbe: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002fc0: 1ad3 subs r3, r2, r3 + 8002fc2: f241 3288 movw r2, #5000 @ 0x1388 + 8002fc6: 4293 cmp r3, r2 + 8002fc8: d901 bls.n 8002fce <HAL_RCC_OscConfig+0x496> + { + return HAL_TIMEOUT; + 8002fca: 2303 movs r3, #3 + 8002fcc: e121 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_LSE_IsReady() != 0U) + 8002fce: f7ff fb54 bl 800267a <LL_RCC_LSE_IsReady> + 8002fd2: 4603 mov r3, r0 + 8002fd4: 2b00 cmp r3, #0 + 8002fd6: d1ef bne.n 8002fb8 <HAL_RCC_OscConfig+0x480> + } + + } +#if defined(RCC_HSI48_SUPPORT) + /*------------------------------ HSI48 Configuration -----------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + 8002fd8: 687b ldr r3, [r7, #4] + 8002fda: 681b ldr r3, [r3, #0] + 8002fdc: f003 0340 and.w r3, r3, #64 @ 0x40 + 8002fe0: 2b00 cmp r3, #0 + 8002fe2: d02c beq.n 800303e <HAL_RCC_OscConfig+0x506> + { + /* Check the parameters */ + assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + + /* Check the HSI State */ + if (RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) + 8002fe4: 687b ldr r3, [r7, #4] + 8002fe6: 6a9b ldr r3, [r3, #40] @ 0x28 + 8002fe8: 2b00 cmp r3, #0 + 8002fea: d014 beq.n 8003016 <HAL_RCC_OscConfig+0x4de> + { + /* Enable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_ENABLE(); + 8002fec: f7ff facd bl 800258a <LL_RCC_HSI48_Enable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002ff0: f7fe fcd8 bl 80019a4 <HAL_GetTick> + 8002ff4: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till HSI48 is ready */ + while (LL_RCC_HSI48_IsReady() == 0U) + 8002ff6: e008 b.n 800300a <HAL_RCC_OscConfig+0x4d2> + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + 8002ff8: f7fe fcd4 bl 80019a4 <HAL_GetTick> + 8002ffc: 4602 mov r2, r0 + 8002ffe: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003000: 1ad3 subs r3, r2, r3 + 8003002: 2b02 cmp r3, #2 + 8003004: d901 bls.n 800300a <HAL_RCC_OscConfig+0x4d2> + { + return HAL_TIMEOUT; + 8003006: 2303 movs r3, #3 + 8003008: e103 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_HSI48_IsReady() == 0U) + 800300a: f7ff fae0 bl 80025ce <LL_RCC_HSI48_IsReady> + 800300e: 4603 mov r3, r0 + 8003010: 2b00 cmp r3, #0 + 8003012: d0f1 beq.n 8002ff8 <HAL_RCC_OscConfig+0x4c0> + 8003014: e013 b.n 800303e <HAL_RCC_OscConfig+0x506> + } + } + else + { + /* Disable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_DISABLE(); + 8003016: f7ff fac9 bl 80025ac <LL_RCC_HSI48_Disable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800301a: f7fe fcc3 bl 80019a4 <HAL_GetTick> + 800301e: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till HSI48 is disabled */ + while (LL_RCC_HSI48_IsReady() != 0U) + 8003020: e008 b.n 8003034 <HAL_RCC_OscConfig+0x4fc> + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + 8003022: f7fe fcbf bl 80019a4 <HAL_GetTick> + 8003026: 4602 mov r2, r0 + 8003028: 6a7b ldr r3, [r7, #36] @ 0x24 + 800302a: 1ad3 subs r3, r2, r3 + 800302c: 2b02 cmp r3, #2 + 800302e: d901 bls.n 8003034 <HAL_RCC_OscConfig+0x4fc> + { + return HAL_TIMEOUT; + 8003030: 2303 movs r3, #3 + 8003032: e0ee b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_HSI48_IsReady() != 0U) + 8003034: f7ff facb bl 80025ce <LL_RCC_HSI48_IsReady> + 8003038: 4603 mov r3, r0 + 800303a: 2b00 cmp r3, #0 + 800303c: d1f1 bne.n 8003022 <HAL_RCC_OscConfig+0x4ea> +#endif /* RCC_HSI48_SUPPORT */ + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + + if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) + 800303e: 687b ldr r3, [r7, #4] + 8003040: 6adb ldr r3, [r3, #44] @ 0x2c + 8003042: 2b00 cmp r3, #0 + 8003044: f000 80e4 beq.w 8003210 <HAL_RCC_OscConfig+0x6d8> + { + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8003048: f7ff fc29 bl 800289e <LL_RCC_GetSysClkSource> + 800304c: 6138 str r0, [r7, #16] + const uint32_t temp_pllconfig = RCC->PLLCFGR; + 800304e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003052: 68db ldr r3, [r3, #12] + 8003054: 60fb str r3, [r7, #12] + + /* PLL On ? */ + if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) + 8003056: 687b ldr r3, [r7, #4] + 8003058: 6adb ldr r3, [r3, #44] @ 0x2c + 800305a: 2b02 cmp r3, #2 + 800305c: f040 80b4 bne.w 80031c8 <HAL_RCC_OscConfig+0x690> + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + + /* Do nothing if PLL configuration is unchanged */ + if ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8003060: 68fb ldr r3, [r7, #12] + 8003062: f003 0203 and.w r2, r3, #3 + 8003066: 687b ldr r3, [r7, #4] + 8003068: 6b1b ldr r3, [r3, #48] @ 0x30 + 800306a: 429a cmp r2, r3 + 800306c: d123 bne.n 80030b6 <HAL_RCC_OscConfig+0x57e> + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 800306e: 68fb ldr r3, [r7, #12] + 8003070: f003 0270 and.w r2, r3, #112 @ 0x70 + 8003074: 687b ldr r3, [r7, #4] + 8003076: 6b5b ldr r3, [r3, #52] @ 0x34 + if ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8003078: 429a cmp r2, r3 + 800307a: d11c bne.n 80030b6 <HAL_RCC_OscConfig+0x57e> + ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) || + 800307c: 68fb ldr r3, [r7, #12] + 800307e: 0a1b lsrs r3, r3, #8 + 8003080: f003 027f and.w r2, r3, #127 @ 0x7f + 8003084: 687b ldr r3, [r7, #4] + 8003086: 6b9b ldr r3, [r3, #56] @ 0x38 + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 8003088: 429a cmp r2, r3 + 800308a: d114 bne.n 80030b6 <HAL_RCC_OscConfig+0x57e> + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || + 800308c: 68fb ldr r3, [r7, #12] + 800308e: f403 1278 and.w r2, r3, #4063232 @ 0x3e0000 + 8003092: 687b ldr r3, [r7, #4] + 8003094: 6bdb ldr r3, [r3, #60] @ 0x3c + ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) || + 8003096: 429a cmp r2, r3 + 8003098: d10d bne.n 80030b6 <HAL_RCC_OscConfig+0x57e> + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || + 800309a: 68fb ldr r3, [r7, #12] + 800309c: f003 6260 and.w r2, r3, #234881024 @ 0xe000000 + 80030a0: 687b ldr r3, [r7, #4] + 80030a2: 6c1b ldr r3, [r3, #64] @ 0x40 + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || + 80030a4: 429a cmp r2, r3 + 80030a6: d106 bne.n 80030b6 <HAL_RCC_OscConfig+0x57e> + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) + 80030a8: 68fb ldr r3, [r7, #12] + 80030aa: f003 4260 and.w r2, r3, #3758096384 @ 0xe0000000 + 80030ae: 687b ldr r3, [r7, #4] + 80030b0: 6c5b ldr r3, [r3, #68] @ 0x44 + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || + 80030b2: 429a cmp r2, r3 + 80030b4: d05d beq.n 8003172 <HAL_RCC_OscConfig+0x63a> + { + /* Check if the PLL is used as system clock or not */ + if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 80030b6: 693b ldr r3, [r7, #16] + 80030b8: 2b0c cmp r3, #12 + 80030ba: d058 beq.n 800316e <HAL_RCC_OscConfig+0x636> + { +#if defined(SAI1) + /* Check if main PLL can be updated */ + /* Not possible if the source is shared by other enabled PLLSAIx */ + if (READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U) + 80030bc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80030c0: 681b ldr r3, [r3, #0] + 80030c2: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 + 80030c6: 2b00 cmp r3, #0 + 80030c8: d001 beq.n 80030ce <HAL_RCC_OscConfig+0x596> + + { + return HAL_ERROR; + 80030ca: 2301 movs r3, #1 + 80030cc: e0a1 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + } + else +#endif /* SAI1 */ + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 80030ce: f7ff fc84 bl 80029da <LL_RCC_PLL_Disable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80030d2: f7fe fc67 bl 80019a4 <HAL_GetTick> + 80030d6: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 80030d8: e008 b.n 80030ec <HAL_RCC_OscConfig+0x5b4> + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 80030da: f7fe fc63 bl 80019a4 <HAL_GetTick> + 80030de: 4602 mov r2, r0 + 80030e0: 6a7b ldr r3, [r7, #36] @ 0x24 + 80030e2: 1ad3 subs r3, r2, r3 + 80030e4: 2b02 cmp r3, #2 + 80030e6: d901 bls.n 80030ec <HAL_RCC_OscConfig+0x5b4> + { + return HAL_TIMEOUT; + 80030e8: 2303 movs r3, #3 + 80030ea: e092 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 80030ec: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80030f0: 681b ldr r3, [r3, #0] + 80030f2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80030f6: 2b00 cmp r3, #0 + 80030f8: d1ef bne.n 80030da <HAL_RCC_OscConfig+0x5a2> + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 80030fa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80030fe: 68da ldr r2, [r3, #12] + 8003100: 4b30 ldr r3, [pc, #192] @ (80031c4 <HAL_RCC_OscConfig+0x68c>) + 8003102: 4013 ands r3, r2 + 8003104: 687a ldr r2, [r7, #4] + 8003106: 6b11 ldr r1, [r2, #48] @ 0x30 + 8003108: 687a ldr r2, [r7, #4] + 800310a: 6b52 ldr r2, [r2, #52] @ 0x34 + 800310c: 4311 orrs r1, r2 + 800310e: 687a ldr r2, [r7, #4] + 8003110: 6b92 ldr r2, [r2, #56] @ 0x38 + 8003112: 0212 lsls r2, r2, #8 + 8003114: 4311 orrs r1, r2 + 8003116: 687a ldr r2, [r7, #4] + 8003118: 6bd2 ldr r2, [r2, #60] @ 0x3c + 800311a: 4311 orrs r1, r2 + 800311c: 687a ldr r2, [r7, #4] + 800311e: 6c12 ldr r2, [r2, #64] @ 0x40 + 8003120: 4311 orrs r1, r2 + 8003122: 687a ldr r2, [r7, #4] + 8003124: 6c52 ldr r2, [r2, #68] @ 0x44 + 8003126: 430a orrs r2, r1 + 8003128: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800312c: 4313 orrs r3, r2 + 800312e: 60cb str r3, [r1, #12] + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8003130: f7ff fc44 bl 80029bc <LL_RCC_PLL_Enable> + + /* Enable PLL System Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); + 8003134: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003138: 68db ldr r3, [r3, #12] + 800313a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 800313e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8003142: 60d3 str r3, [r2, #12] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003144: f7fe fc2e bl 80019a4 <HAL_GetTick> + 8003148: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 800314a: e008 b.n 800315e <HAL_RCC_OscConfig+0x626> + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 800314c: f7fe fc2a bl 80019a4 <HAL_GetTick> + 8003150: 4602 mov r2, r0 + 8003152: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003154: 1ad3 subs r3, r2, r3 + 8003156: 2b02 cmp r3, #2 + 8003158: d901 bls.n 800315e <HAL_RCC_OscConfig+0x626> + { + return HAL_TIMEOUT; + 800315a: 2303 movs r3, #3 + 800315c: e059 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 800315e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003162: 681b ldr r3, [r3, #0] + 8003164: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8003168: 2b00 cmp r3, #0 + 800316a: d0ef beq.n 800314c <HAL_RCC_OscConfig+0x614> + if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 800316c: e050 b.n 8003210 <HAL_RCC_OscConfig+0x6d8> + } + } + else + { + /* PLL is already used as System core clock */ + return HAL_ERROR; + 800316e: 2301 movs r3, #1 + 8003170: e04f b.n 8003212 <HAL_RCC_OscConfig+0x6da> + } + else + { + /* PLL configuration is unchanged */ + /* Re-enable PLL if it was disabled (ie. low power mode) */ + if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 8003172: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003176: 681b ldr r3, [r3, #0] + 8003178: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 800317c: 2b00 cmp r3, #0 + 800317e: d147 bne.n 8003210 <HAL_RCC_OscConfig+0x6d8> + { + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8003180: f7ff fc1c bl 80029bc <LL_RCC_PLL_Enable> + + /* Enable PLL System Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); + 8003184: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003188: 68db ldr r3, [r3, #12] + 800318a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 800318e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8003192: 60d3 str r3, [r2, #12] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003194: f7fe fc06 bl 80019a4 <HAL_GetTick> + 8003198: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 800319a: e008 b.n 80031ae <HAL_RCC_OscConfig+0x676> + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 800319c: f7fe fc02 bl 80019a4 <HAL_GetTick> + 80031a0: 4602 mov r2, r0 + 80031a2: 6a7b ldr r3, [r7, #36] @ 0x24 + 80031a4: 1ad3 subs r3, r2, r3 + 80031a6: 2b02 cmp r3, #2 + 80031a8: d901 bls.n 80031ae <HAL_RCC_OscConfig+0x676> + { + return HAL_TIMEOUT; + 80031aa: 2303 movs r3, #3 + 80031ac: e031 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 80031ae: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80031b2: 681b ldr r3, [r3, #0] + 80031b4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80031b8: 2b00 cmp r3, #0 + 80031ba: d0ef beq.n 800319c <HAL_RCC_OscConfig+0x664> + 80031bc: e028 b.n 8003210 <HAL_RCC_OscConfig+0x6d8> + 80031be: bf00 nop + 80031c0: 58000400 .word 0x58000400 + 80031c4: 11c1808c .word 0x11c1808c + } + } + else + { + /* Check that PLL is not used as system clock or not */ + if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 80031c8: 693b ldr r3, [r7, #16] + 80031ca: 2b0c cmp r3, #12 + 80031cc: d01e beq.n 800320c <HAL_RCC_OscConfig+0x6d4> + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 80031ce: f7ff fc04 bl 80029da <LL_RCC_PLL_Disable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80031d2: f7fe fbe7 bl 80019a4 <HAL_GetTick> + 80031d6: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 80031d8: e008 b.n 80031ec <HAL_RCC_OscConfig+0x6b4> + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 80031da: f7fe fbe3 bl 80019a4 <HAL_GetTick> + 80031de: 4602 mov r2, r0 + 80031e0: 6a7b ldr r3, [r7, #36] @ 0x24 + 80031e2: 1ad3 subs r3, r2, r3 + 80031e4: 2b02 cmp r3, #2 + 80031e6: d901 bls.n 80031ec <HAL_RCC_OscConfig+0x6b4> + { + return HAL_TIMEOUT; + 80031e8: 2303 movs r3, #3 + 80031ea: e012 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 80031ec: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80031f0: 681b ldr r3, [r3, #0] + 80031f2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80031f6: 2b00 cmp r3, #0 + 80031f8: d1ef bne.n 80031da <HAL_RCC_OscConfig+0x6a2> + } + } + + /* Disable the PLL source and outputs to save power when PLL is off */ +#if defined(SAI1) && defined(USB) + CLEAR_BIT(RCC->PLLCFGR, (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN)); + 80031fa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80031fe: 68da ldr r2, [r3, #12] + 8003200: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003204: 4b05 ldr r3, [pc, #20] @ (800321c <HAL_RCC_OscConfig+0x6e4>) + 8003206: 4013 ands r3, r2 + 8003208: 60cb str r3, [r1, #12] + 800320a: e001 b.n 8003210 <HAL_RCC_OscConfig+0x6d8> +#endif /* SAI1 && USB */ + } + else + { + /* PLL is already used as System core clock */ + return HAL_ERROR; + 800320c: 2301 movs r3, #1 + 800320e: e000 b.n 8003212 <HAL_RCC_OscConfig+0x6da> + } + } + } + return HAL_OK; + 8003210: 2300 movs r3, #0 +} + 8003212: 4618 mov r0, r3 + 8003214: 3734 adds r7, #52 @ 0x34 + 8003216: 46bd mov sp, r7 + 8003218: bd90 pop {r4, r7, pc} + 800321a: bf00 nop + 800321c: eefefffc .word 0xeefefffc + +08003220 <HAL_RCC_ClockConfig>: + * HPRE[3:0] bits to ensure that HCLK1 not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 8003220: b580 push {r7, lr} + 8003222: b084 sub sp, #16 + 8003224: af00 add r7, sp, #0 + 8003226: 6078 str r0, [r7, #4] + 8003228: 6039 str r1, [r7, #0] + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + 800322a: 687b ldr r3, [r7, #4] + 800322c: 2b00 cmp r3, #0 + 800322e: d101 bne.n 8003234 <HAL_RCC_ClockConfig+0x14> + { + return HAL_ERROR; + 8003230: 2301 movs r3, #1 + 8003232: e12d b.n 8003490 <HAL_RCC_ClockConfig+0x270> + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the FLASH clock + (HCLK4) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + 8003234: 4b98 ldr r3, [pc, #608] @ (8003498 <HAL_RCC_ClockConfig+0x278>) + 8003236: 681b ldr r3, [r3, #0] + 8003238: f003 0307 and.w r3, r3, #7 + 800323c: 683a ldr r2, [r7, #0] + 800323e: 429a cmp r2, r3 + 8003240: d91b bls.n 800327a <HAL_RCC_ClockConfig+0x5a> + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8003242: 4b95 ldr r3, [pc, #596] @ (8003498 <HAL_RCC_ClockConfig+0x278>) + 8003244: 681b ldr r3, [r3, #0] + 8003246: f023 0207 bic.w r2, r3, #7 + 800324a: 4993 ldr r1, [pc, #588] @ (8003498 <HAL_RCC_ClockConfig+0x278>) + 800324c: 683b ldr r3, [r7, #0] + 800324e: 4313 orrs r3, r2 + 8003250: 600b str r3, [r1, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003252: f7fe fba7 bl 80019a4 <HAL_GetTick> + 8003256: 60f8 str r0, [r7, #12] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 8003258: e008 b.n 800326c <HAL_RCC_ClockConfig+0x4c> + { + if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) + 800325a: f7fe fba3 bl 80019a4 <HAL_GetTick> + 800325e: 4602 mov r2, r0 + 8003260: 68fb ldr r3, [r7, #12] + 8003262: 1ad3 subs r3, r2, r3 + 8003264: 2b02 cmp r3, #2 + 8003266: d901 bls.n 800326c <HAL_RCC_ClockConfig+0x4c> + { + return HAL_TIMEOUT; + 8003268: 2303 movs r3, #3 + 800326a: e111 b.n 8003490 <HAL_RCC_ClockConfig+0x270> + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 800326c: 4b8a ldr r3, [pc, #552] @ (8003498 <HAL_RCC_ClockConfig+0x278>) + 800326e: 681b ldr r3, [r3, #0] + 8003270: f003 0307 and.w r3, r3, #7 + 8003274: 683a ldr r2, [r7, #0] + 8003276: 429a cmp r2, r3 + 8003278: d1ef bne.n 800325a <HAL_RCC_ClockConfig+0x3a> + } + } + } + + /*-------------------------- HCLK1 Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 800327a: 687b ldr r3, [r7, #4] + 800327c: 681b ldr r3, [r3, #0] + 800327e: f003 0302 and.w r3, r3, #2 + 8003282: 2b00 cmp r3, #0 + 8003284: d016 beq.n 80032b4 <HAL_RCC_ClockConfig+0x94> + { + assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLKDivider)); + LL_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLKDivider); + 8003286: 687b ldr r3, [r7, #4] + 8003288: 689b ldr r3, [r3, #8] + 800328a: 4618 mov r0, r3 + 800328c: f7ff fb13 bl 80028b6 <LL_RCC_SetAHBPrescaler> + + /* HCLK1 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 8003290: f7fe fb88 bl 80019a4 <HAL_GetTick> + 8003294: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_HPRE() == 0U) + 8003296: e008 b.n 80032aa <HAL_RCC_ClockConfig+0x8a> + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 8003298: f7fe fb84 bl 80019a4 <HAL_GetTick> + 800329c: 4602 mov r2, r0 + 800329e: 68fb ldr r3, [r7, #12] + 80032a0: 1ad3 subs r3, r2, r3 + 80032a2: 2b02 cmp r3, #2 + 80032a4: d901 bls.n 80032aa <HAL_RCC_ClockConfig+0x8a> + { + return HAL_TIMEOUT; + 80032a6: 2303 movs r3, #3 + 80032a8: e0f2 b.n 8003490 <HAL_RCC_ClockConfig+0x270> + while (LL_RCC_IsActiveFlag_HPRE() == 0U) + 80032aa: f7ff fbe8 bl 8002a7e <LL_RCC_IsActiveFlag_HPRE> + 80032ae: 4603 mov r3, r0 + 80032b0: 2b00 cmp r3, #0 + 80032b2: d0f1 beq.n 8003298 <HAL_RCC_ClockConfig+0x78> + } + } + } + + /*-------------------------- HCLK2 Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK2) == RCC_CLOCKTYPE_HCLK2) + 80032b4: 687b ldr r3, [r7, #4] + 80032b6: 681b ldr r3, [r3, #0] + 80032b8: f003 0320 and.w r3, r3, #32 + 80032bc: 2b00 cmp r3, #0 + 80032be: d016 beq.n 80032ee <HAL_RCC_ClockConfig+0xce> + { + assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK2Divider)); + LL_C2_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLK2Divider); + 80032c0: 687b ldr r3, [r7, #4] + 80032c2: 695b ldr r3, [r3, #20] + 80032c4: 4618 mov r0, r3 + 80032c6: f7ff fb0a bl 80028de <LL_C2_RCC_SetAHBPrescaler> + + /* HCLK2 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 80032ca: f7fe fb6b bl 80019a4 <HAL_GetTick> + 80032ce: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_C2HPRE() == 0U) + 80032d0: e008 b.n 80032e4 <HAL_RCC_ClockConfig+0xc4> + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 80032d2: f7fe fb67 bl 80019a4 <HAL_GetTick> + 80032d6: 4602 mov r2, r0 + 80032d8: 68fb ldr r3, [r7, #12] + 80032da: 1ad3 subs r3, r2, r3 + 80032dc: 2b02 cmp r3, #2 + 80032de: d901 bls.n 80032e4 <HAL_RCC_ClockConfig+0xc4> + { + return HAL_TIMEOUT; + 80032e0: 2303 movs r3, #3 + 80032e2: e0d5 b.n 8003490 <HAL_RCC_ClockConfig+0x270> + while (LL_RCC_IsActiveFlag_C2HPRE() == 0U) + 80032e4: f7ff fbdd bl 8002aa2 <LL_RCC_IsActiveFlag_C2HPRE> + 80032e8: 4603 mov r3, r0 + 80032ea: 2b00 cmp r3, #0 + 80032ec: d0f1 beq.n 80032d2 <HAL_RCC_ClockConfig+0xb2> + } + } + } + /*-------------------------- HCLK4 Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK4) == RCC_CLOCKTYPE_HCLK4) + 80032ee: 687b ldr r3, [r7, #4] + 80032f0: 681b ldr r3, [r3, #0] + 80032f2: f003 0340 and.w r3, r3, #64 @ 0x40 + 80032f6: 2b00 cmp r3, #0 + 80032f8: d016 beq.n 8003328 <HAL_RCC_ClockConfig+0x108> + { + assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK4Divider)); + LL_RCC_SetAHB4Prescaler(RCC_ClkInitStruct->AHBCLK4Divider); + 80032fa: 687b ldr r3, [r7, #4] + 80032fc: 699b ldr r3, [r3, #24] + 80032fe: 4618 mov r0, r3 + 8003300: f7ff fb03 bl 800290a <LL_RCC_SetAHB4Prescaler> + + /* AHB shared prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 8003304: f7fe fb4e bl 80019a4 <HAL_GetTick> + 8003308: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U) + 800330a: e008 b.n 800331e <HAL_RCC_ClockConfig+0xfe> + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 800330c: f7fe fb4a bl 80019a4 <HAL_GetTick> + 8003310: 4602 mov r2, r0 + 8003312: 68fb ldr r3, [r7, #12] + 8003314: 1ad3 subs r3, r2, r3 + 8003316: 2b02 cmp r3, #2 + 8003318: d901 bls.n 800331e <HAL_RCC_ClockConfig+0xfe> + { + return HAL_TIMEOUT; + 800331a: 2303 movs r3, #3 + 800331c: e0b8 b.n 8003490 <HAL_RCC_ClockConfig+0x270> + while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U) + 800331e: f7ff fbd3 bl 8002ac8 <LL_RCC_IsActiveFlag_SHDHPRE> + 8003322: 4603 mov r3, r0 + 8003324: 2b00 cmp r3, #0 + 8003326: d0f1 beq.n 800330c <HAL_RCC_ClockConfig+0xec> + } + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8003328: 687b ldr r3, [r7, #4] + 800332a: 681b ldr r3, [r3, #0] + 800332c: f003 0304 and.w r3, r3, #4 + 8003330: 2b00 cmp r3, #0 + 8003332: d016 beq.n 8003362 <HAL_RCC_ClockConfig+0x142> + { + assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB1CLKDivider)); + LL_RCC_SetAPB1Prescaler(RCC_ClkInitStruct->APB1CLKDivider); + 8003334: 687b ldr r3, [r7, #4] + 8003336: 68db ldr r3, [r3, #12] + 8003338: 4618 mov r0, r3 + 800333a: f7ff fafd bl 8002938 <LL_RCC_SetAPB1Prescaler> + + /* APB1 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 800333e: f7fe fb31 bl 80019a4 <HAL_GetTick> + 8003342: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_PPRE1() == 0U) + 8003344: e008 b.n 8003358 <HAL_RCC_ClockConfig+0x138> + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 8003346: f7fe fb2d bl 80019a4 <HAL_GetTick> + 800334a: 4602 mov r2, r0 + 800334c: 68fb ldr r3, [r7, #12] + 800334e: 1ad3 subs r3, r2, r3 + 8003350: 2b02 cmp r3, #2 + 8003352: d901 bls.n 8003358 <HAL_RCC_ClockConfig+0x138> + { + return HAL_TIMEOUT; + 8003354: 2303 movs r3, #3 + 8003356: e09b b.n 8003490 <HAL_RCC_ClockConfig+0x270> + while (LL_RCC_IsActiveFlag_PPRE1() == 0U) + 8003358: f7ff fbc9 bl 8002aee <LL_RCC_IsActiveFlag_PPRE1> + 800335c: 4603 mov r3, r0 + 800335e: 2b00 cmp r3, #0 + 8003360: d0f1 beq.n 8003346 <HAL_RCC_ClockConfig+0x126> + } + } + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8003362: 687b ldr r3, [r7, #4] + 8003364: 681b ldr r3, [r3, #0] + 8003366: f003 0308 and.w r3, r3, #8 + 800336a: 2b00 cmp r3, #0 + 800336c: d017 beq.n 800339e <HAL_RCC_ClockConfig+0x17e> + { + assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB2CLKDivider)); + LL_RCC_SetAPB2Prescaler((RCC_ClkInitStruct->APB2CLKDivider) << 3U); + 800336e: 687b ldr r3, [r7, #4] + 8003370: 691b ldr r3, [r3, #16] + 8003372: 00db lsls r3, r3, #3 + 8003374: 4618 mov r0, r3 + 8003376: f7ff faf3 bl 8002960 <LL_RCC_SetAPB2Prescaler> + + /* APB2 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 800337a: f7fe fb13 bl 80019a4 <HAL_GetTick> + 800337e: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_PPRE2() == 0U) + 8003380: e008 b.n 8003394 <HAL_RCC_ClockConfig+0x174> + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 8003382: f7fe fb0f bl 80019a4 <HAL_GetTick> + 8003386: 4602 mov r2, r0 + 8003388: 68fb ldr r3, [r7, #12] + 800338a: 1ad3 subs r3, r2, r3 + 800338c: 2b02 cmp r3, #2 + 800338e: d901 bls.n 8003394 <HAL_RCC_ClockConfig+0x174> + { + return HAL_TIMEOUT; + 8003390: 2303 movs r3, #3 + 8003392: e07d b.n 8003490 <HAL_RCC_ClockConfig+0x270> + while (LL_RCC_IsActiveFlag_PPRE2() == 0U) + 8003394: f7ff fbbd bl 8002b12 <LL_RCC_IsActiveFlag_PPRE2> + 8003398: 4603 mov r3, r0 + 800339a: 2b00 cmp r3, #0 + 800339c: d0f1 beq.n 8003382 <HAL_RCC_ClockConfig+0x162> + } + } + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 800339e: 687b ldr r3, [r7, #4] + 80033a0: 681b ldr r3, [r3, #0] + 80033a2: f003 0301 and.w r3, r3, #1 + 80033a6: 2b00 cmp r3, #0 + 80033a8: d043 beq.n 8003432 <HAL_RCC_ClockConfig+0x212> + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 80033aa: 687b ldr r3, [r7, #4] + 80033ac: 685b ldr r3, [r3, #4] + 80033ae: 2b02 cmp r3, #2 + 80033b0: d106 bne.n 80033c0 <HAL_RCC_ClockConfig+0x1a0> + { + /* Check the HSE ready flag */ + if (LL_RCC_HSE_IsReady() == 0U) + 80033b2: f7ff f893 bl 80024dc <LL_RCC_HSE_IsReady> + 80033b6: 4603 mov r3, r0 + 80033b8: 2b00 cmp r3, #0 + 80033ba: d11e bne.n 80033fa <HAL_RCC_ClockConfig+0x1da> + { + return HAL_ERROR; + 80033bc: 2301 movs r3, #1 + 80033be: e067 b.n 8003490 <HAL_RCC_ClockConfig+0x270> + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 80033c0: 687b ldr r3, [r7, #4] + 80033c2: 685b ldr r3, [r3, #4] + 80033c4: 2b03 cmp r3, #3 + 80033c6: d106 bne.n 80033d6 <HAL_RCC_ClockConfig+0x1b6> + { + /* Check the PLL ready flag */ + if (LL_RCC_PLL_IsReady() == 0U) + 80033c8: f7ff fb16 bl 80029f8 <LL_RCC_PLL_IsReady> + 80033cc: 4603 mov r3, r0 + 80033ce: 2b00 cmp r3, #0 + 80033d0: d113 bne.n 80033fa <HAL_RCC_ClockConfig+0x1da> + { + return HAL_ERROR; + 80033d2: 2301 movs r3, #1 + 80033d4: e05c b.n 8003490 <HAL_RCC_ClockConfig+0x270> + } + } + /* MSI is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) + 80033d6: 687b ldr r3, [r7, #4] + 80033d8: 685b ldr r3, [r3, #4] + 80033da: 2b00 cmp r3, #0 + 80033dc: d106 bne.n 80033ec <HAL_RCC_ClockConfig+0x1cc> + { + /* Check the MSI ready flag */ + if (LL_RCC_MSI_IsReady() == 0U) + 80033de: f7ff f9fb bl 80027d8 <LL_RCC_MSI_IsReady> + 80033e2: 4603 mov r3, r0 + 80033e4: 2b00 cmp r3, #0 + 80033e6: d108 bne.n 80033fa <HAL_RCC_ClockConfig+0x1da> + { + return HAL_ERROR; + 80033e8: 2301 movs r3, #1 + 80033ea: e051 b.n 8003490 <HAL_RCC_ClockConfig+0x270> + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (LL_RCC_HSI_IsReady() == 0U) + 80033ec: f7ff f8a6 bl 800253c <LL_RCC_HSI_IsReady> + 80033f0: 4603 mov r3, r0 + 80033f2: 2b00 cmp r3, #0 + 80033f4: d101 bne.n 80033fa <HAL_RCC_ClockConfig+0x1da> + { + return HAL_ERROR; + 80033f6: 2301 movs r3, #1 + 80033f8: e04a b.n 8003490 <HAL_RCC_ClockConfig+0x270> + } + + } + + /* apply system clock switch */ + LL_RCC_SetSysClkSource(RCC_ClkInitStruct->SYSCLKSource); + 80033fa: 687b ldr r3, [r7, #4] + 80033fc: 685b ldr r3, [r3, #4] + 80033fe: 4618 mov r0, r3 + 8003400: f7ff fa39 bl 8002876 <LL_RCC_SetSysClkSource> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003404: f7fe face bl 80019a4 <HAL_GetTick> + 8003408: 60f8 str r0, [r7, #12] + + /* check system clock source switch status */ + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 800340a: e00a b.n 8003422 <HAL_RCC_ClockConfig+0x202> + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 800340c: f7fe faca bl 80019a4 <HAL_GetTick> + 8003410: 4602 mov r2, r0 + 8003412: 68fb ldr r3, [r7, #12] + 8003414: 1ad3 subs r3, r2, r3 + 8003416: f241 3288 movw r2, #5000 @ 0x1388 + 800341a: 4293 cmp r3, r2 + 800341c: d901 bls.n 8003422 <HAL_RCC_ClockConfig+0x202> + { + return HAL_TIMEOUT; + 800341e: 2303 movs r3, #3 + 8003420: e036 b.n 8003490 <HAL_RCC_ClockConfig+0x270> + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8003422: f7ff fa3c bl 800289e <LL_RCC_GetSysClkSource> + 8003426: 4602 mov r2, r0 + 8003428: 687b ldr r3, [r7, #4] + 800342a: 685b ldr r3, [r3, #4] + 800342c: 009b lsls r3, r3, #2 + 800342e: 429a cmp r2, r3 + 8003430: d1ec bne.n 800340c <HAL_RCC_ClockConfig+0x1ec> + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + 8003432: 4b19 ldr r3, [pc, #100] @ (8003498 <HAL_RCC_ClockConfig+0x278>) + 8003434: 681b ldr r3, [r3, #0] + 8003436: f003 0307 and.w r3, r3, #7 + 800343a: 683a ldr r2, [r7, #0] + 800343c: 429a cmp r2, r3 + 800343e: d21b bcs.n 8003478 <HAL_RCC_ClockConfig+0x258> + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8003440: 4b15 ldr r3, [pc, #84] @ (8003498 <HAL_RCC_ClockConfig+0x278>) + 8003442: 681b ldr r3, [r3, #0] + 8003444: f023 0207 bic.w r2, r3, #7 + 8003448: 4913 ldr r1, [pc, #76] @ (8003498 <HAL_RCC_ClockConfig+0x278>) + 800344a: 683b ldr r3, [r7, #0] + 800344c: 4313 orrs r3, r2 + 800344e: 600b str r3, [r1, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003450: f7fe faa8 bl 80019a4 <HAL_GetTick> + 8003454: 60f8 str r0, [r7, #12] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 8003456: e008 b.n 800346a <HAL_RCC_ClockConfig+0x24a> + { + if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) + 8003458: f7fe faa4 bl 80019a4 <HAL_GetTick> + 800345c: 4602 mov r2, r0 + 800345e: 68fb ldr r3, [r7, #12] + 8003460: 1ad3 subs r3, r2, r3 + 8003462: 2b02 cmp r3, #2 + 8003464: d901 bls.n 800346a <HAL_RCC_ClockConfig+0x24a> + { + return HAL_TIMEOUT; + 8003466: 2303 movs r3, #3 + 8003468: e012 b.n 8003490 <HAL_RCC_ClockConfig+0x270> + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 800346a: 4b0b ldr r3, [pc, #44] @ (8003498 <HAL_RCC_ClockConfig+0x278>) + 800346c: 681b ldr r3, [r3, #0] + 800346e: f003 0307 and.w r3, r3, #7 + 8003472: 683a ldr r2, [r7, #0] + 8003474: 429a cmp r2, r3 + 8003476: d1ef bne.n 8003458 <HAL_RCC_ClockConfig+0x238> + } + + /*---------------------------------------------------------------------------*/ + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetHCLKFreq(); + 8003478: f000 f87e bl 8003578 <HAL_RCC_GetHCLKFreq> + 800347c: 4603 mov r3, r0 + 800347e: 4a07 ldr r2, [pc, #28] @ (800349c <HAL_RCC_ClockConfig+0x27c>) + 8003480: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + return HAL_InitTick(HAL_GetTickPrio()); + 8003482: f7fe fa9b bl 80019bc <HAL_GetTickPrio> + 8003486: 4603 mov r3, r0 + 8003488: 4618 mov r0, r3 + 800348a: f7fe fa3d bl 8001908 <HAL_InitTick> + 800348e: 4603 mov r3, r0 +} + 8003490: 4618 mov r0, r3 + 8003492: 3710 adds r7, #16 + 8003494: 46bd mov sp, r7 + 8003496: bd80 pop {r7, pc} + 8003498: 58004000 .word 0x58004000 + 800349c: 20000008 .word 0x20000008 + +080034a0 <HAL_RCC_GetSysClockFreq>: + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 80034a0: b590 push {r4, r7, lr} + 80034a2: b085 sub sp, #20 + 80034a4: af00 add r7, sp, #0 + uint32_t pllsource; + uint32_t sysclockfreq; + uint32_t pllinputfreq; + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 80034a6: f7ff f9fa bl 800289e <LL_RCC_GetSysClkSource> + 80034aa: 6078 str r0, [r7, #4] + + if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_MSI) + 80034ac: 687b ldr r3, [r7, #4] + 80034ae: 2b00 cmp r3, #0 + 80034b0: d10a bne.n 80034c8 <HAL_RCC_GetSysClockFreq+0x28> + { + /* Retrieve MSI frequency range in HZ*/ + /* MSI used as system clock source */ + sysclockfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); + 80034b2: f7ff f9b6 bl 8002822 <LL_RCC_MSI_GetRange> + 80034b6: 4603 mov r3, r0 + 80034b8: 091b lsrs r3, r3, #4 + 80034ba: f003 030f and.w r3, r3, #15 + 80034be: 4a2b ldr r2, [pc, #172] @ (800356c <HAL_RCC_GetSysClockFreq+0xcc>) + 80034c0: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80034c4: 60fb str r3, [r7, #12] + 80034c6: e04b b.n 8003560 <HAL_RCC_GetSysClockFreq+0xc0> + } + else if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) + 80034c8: 687b ldr r3, [r7, #4] + 80034ca: 2b04 cmp r3, #4 + 80034cc: d102 bne.n 80034d4 <HAL_RCC_GetSysClockFreq+0x34> + { + /* HSI used as system clock source */ + sysclockfreq = HSI_VALUE; + 80034ce: 4b28 ldr r3, [pc, #160] @ (8003570 <HAL_RCC_GetSysClockFreq+0xd0>) + 80034d0: 60fb str r3, [r7, #12] + 80034d2: e045 b.n 8003560 <HAL_RCC_GetSysClockFreq+0xc0> + } + else if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE) + 80034d4: 687b ldr r3, [r7, #4] + 80034d6: 2b08 cmp r3, #8 + 80034d8: d10a bne.n 80034f0 <HAL_RCC_GetSysClockFreq+0x50> + { + /* HSE used as system clock source */ + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + 80034da: f7fe ffcf bl 800247c <LL_RCC_HSE_IsEnabledDiv2> + 80034de: 4603 mov r3, r0 + 80034e0: 2b01 cmp r3, #1 + 80034e2: d102 bne.n 80034ea <HAL_RCC_GetSysClockFreq+0x4a> + { + sysclockfreq = HSE_VALUE / 2U; + 80034e4: 4b22 ldr r3, [pc, #136] @ (8003570 <HAL_RCC_GetSysClockFreq+0xd0>) + 80034e6: 60fb str r3, [r7, #12] + 80034e8: e03a b.n 8003560 <HAL_RCC_GetSysClockFreq+0xc0> + } + else + { + sysclockfreq = HSE_VALUE; + 80034ea: 4b22 ldr r3, [pc, #136] @ (8003574 <HAL_RCC_GetSysClockFreq+0xd4>) + 80034ec: 60fb str r3, [r7, #12] + 80034ee: e037 b.n 8003560 <HAL_RCC_GetSysClockFreq+0xc0> + } + } + else + { + /* PLL used as system clock source */ + pllsource = LL_RCC_PLL_GetMainSource(); + 80034f0: f7ff fab9 bl 8002a66 <LL_RCC_PLL_GetMainSource> + 80034f4: 6038 str r0, [r7, #0] + switch (pllsource) + 80034f6: 683b ldr r3, [r7, #0] + 80034f8: 2b02 cmp r3, #2 + 80034fa: d003 beq.n 8003504 <HAL_RCC_GetSysClockFreq+0x64> + 80034fc: 683b ldr r3, [r7, #0] + 80034fe: 2b03 cmp r3, #3 + 8003500: d003 beq.n 800350a <HAL_RCC_GetSysClockFreq+0x6a> + 8003502: e00d b.n 8003520 <HAL_RCC_GetSysClockFreq+0x80> + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pllinputfreq = HSI_VALUE; + 8003504: 4b1a ldr r3, [pc, #104] @ (8003570 <HAL_RCC_GetSysClockFreq+0xd0>) + 8003506: 60bb str r3, [r7, #8] + break; + 8003508: e015 b.n 8003536 <HAL_RCC_GetSysClockFreq+0x96> + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + 800350a: f7fe ffb7 bl 800247c <LL_RCC_HSE_IsEnabledDiv2> + 800350e: 4603 mov r3, r0 + 8003510: 2b01 cmp r3, #1 + 8003512: d102 bne.n 800351a <HAL_RCC_GetSysClockFreq+0x7a> + { + pllinputfreq = HSE_VALUE / 2U; + 8003514: 4b16 ldr r3, [pc, #88] @ (8003570 <HAL_RCC_GetSysClockFreq+0xd0>) + 8003516: 60bb str r3, [r7, #8] + } + else + { + pllinputfreq = HSE_VALUE; + } + break; + 8003518: e00d b.n 8003536 <HAL_RCC_GetSysClockFreq+0x96> + pllinputfreq = HSE_VALUE; + 800351a: 4b16 ldr r3, [pc, #88] @ (8003574 <HAL_RCC_GetSysClockFreq+0xd4>) + 800351c: 60bb str r3, [r7, #8] + break; + 800351e: e00a b.n 8003536 <HAL_RCC_GetSysClockFreq+0x96> + case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ + default: + pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); + 8003520: f7ff f97f bl 8002822 <LL_RCC_MSI_GetRange> + 8003524: 4603 mov r3, r0 + 8003526: 091b lsrs r3, r3, #4 + 8003528: f003 030f and.w r3, r3, #15 + 800352c: 4a0f ldr r2, [pc, #60] @ (800356c <HAL_RCC_GetSysClockFreq+0xcc>) + 800352e: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8003532: 60bb str r3, [r7, #8] + break; + 8003534: bf00 nop + } + sysclockfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetN(), + 8003536: f7ff fa71 bl 8002a1c <LL_RCC_PLL_GetN> + 800353a: 4602 mov r2, r0 + 800353c: 68bb ldr r3, [r7, #8] + 800353e: fb03 f402 mul.w r4, r3, r2 + 8003542: f7ff fa84 bl 8002a4e <LL_RCC_PLL_GetDivider> + 8003546: 4603 mov r3, r0 + 8003548: 091b lsrs r3, r3, #4 + 800354a: 3301 adds r3, #1 + 800354c: fbb4 f4f3 udiv r4, r4, r3 + 8003550: f7ff fa71 bl 8002a36 <LL_RCC_PLL_GetR> + 8003554: 4603 mov r3, r0 + 8003556: 0f5b lsrs r3, r3, #29 + 8003558: 3301 adds r3, #1 + 800355a: fbb4 f3f3 udiv r3, r4, r3 + 800355e: 60fb str r3, [r7, #12] + LL_RCC_PLL_GetR()); + } + + return sysclockfreq; + 8003560: 68fb ldr r3, [r7, #12] +} + 8003562: 4618 mov r0, r3 + 8003564: 3714 adds r7, #20 + 8003566: 46bd mov sp, r7 + 8003568: bd90 pop {r4, r7, pc} + 800356a: bf00 nop + 800356c: 08007db0 .word 0x08007db0 + 8003570: 00f42400 .word 0x00f42400 + 8003574: 01e84800 .word 0x01e84800 + +08003578 <HAL_RCC_GetHCLKFreq>: +/** + * @brief Return the HCLK frequency. + * @retval HCLK frequency in Hz + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + 8003578: b598 push {r3, r4, r7, lr} + 800357a: af00 add r7, sp, #0 + /* Get SysClock and Compute HCLK1 frequency ---------------------------*/ + return ((uint32_t)(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()))); + 800357c: f7ff ff90 bl 80034a0 <HAL_RCC_GetSysClockFreq> + 8003580: 4604 mov r4, r0 + 8003582: f7ff fa01 bl 8002988 <LL_RCC_GetAHBPrescaler> + 8003586: 4603 mov r3, r0 + 8003588: 091b lsrs r3, r3, #4 + 800358a: f003 030f and.w r3, r3, #15 + 800358e: 4a03 ldr r2, [pc, #12] @ (800359c <HAL_RCC_GetHCLKFreq+0x24>) + 8003590: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8003594: fbb4 f3f3 udiv r3, r4, r3 +} + 8003598: 4618 mov r0, r3 + 800359a: bd98 pop {r3, r4, r7, pc} + 800359c: 08007d70 .word 0x08007d70 + +080035a0 <RCC_SetFlashLatencyFromMSIRange>: + voltage range. + * @param MSI_Range MSI range value from @ref RCC_MSIRANGE_0 to @ref RCC_MSIRANGE_11 + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSI_Range) +{ + 80035a0: b590 push {r4, r7, lr} + 80035a2: b085 sub sp, #20 + 80035a4: af00 add r7, sp, #0 + 80035a6: 6078 str r0, [r7, #4] + + /* Check the parameters */ + assert_param(IS_RCC_MSI_CLOCK_RANGE(MSI_Range)); + + /* MSI frequency range in Hz */ + if (MSI_Range > RCC_MSIRANGE_11) + 80035a8: 687b ldr r3, [r7, #4] + 80035aa: 2bb0 cmp r3, #176 @ 0xb0 + 80035ac: d903 bls.n 80035b6 <RCC_SetFlashLatencyFromMSIRange+0x16> + { + msifreq = __LL_RCC_CALC_MSI_FREQ(RCC_MSIRANGE_11); + 80035ae: 4b15 ldr r3, [pc, #84] @ (8003604 <RCC_SetFlashLatencyFromMSIRange+0x64>) + 80035b0: 6adb ldr r3, [r3, #44] @ 0x2c + 80035b2: 60fb str r3, [r7, #12] + 80035b4: e007 b.n 80035c6 <RCC_SetFlashLatencyFromMSIRange+0x26> + } + else + { + msifreq = __LL_RCC_CALC_MSI_FREQ(MSI_Range); + 80035b6: 687b ldr r3, [r7, #4] + 80035b8: 091b lsrs r3, r3, #4 + 80035ba: f003 030f and.w r3, r3, #15 + 80035be: 4a11 ldr r2, [pc, #68] @ (8003604 <RCC_SetFlashLatencyFromMSIRange+0x64>) + 80035c0: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80035c4: 60fb str r3, [r7, #12] + } + + flash_clksrcfreq = __LL_RCC_CALC_HCLK4_FREQ(msifreq, LL_RCC_GetAHB4Prescaler()); + 80035c6: f7ff f9eb bl 80029a0 <LL_RCC_GetAHB4Prescaler> + 80035ca: 4603 mov r3, r0 + 80035cc: 091b lsrs r3, r3, #4 + 80035ce: f003 030f and.w r3, r3, #15 + 80035d2: 4a0d ldr r2, [pc, #52] @ (8003608 <RCC_SetFlashLatencyFromMSIRange+0x68>) + 80035d4: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80035d8: 68fa ldr r2, [r7, #12] + 80035da: fbb2 f3f3 udiv r3, r2, r3 + 80035de: 60bb str r3, [r7, #8] + +#if defined(PWR_CR1_VOS) + return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), HAL_PWREx_GetVoltageRange()); + 80035e0: 68bb ldr r3, [r7, #8] + 80035e2: 4a0a ldr r2, [pc, #40] @ (800360c <RCC_SetFlashLatencyFromMSIRange+0x6c>) + 80035e4: fba2 2303 umull r2, r3, r2, r3 + 80035e8: 0c9c lsrs r4, r3, #18 + 80035ea: f7fe ff0d bl 8002408 <HAL_PWREx_GetVoltageRange> + 80035ee: 4603 mov r3, r0 + 80035f0: 4619 mov r1, r3 + 80035f2: 4620 mov r0, r4 + 80035f4: f000 f80c bl 8003610 <RCC_SetFlashLatency> + 80035f8: 4603 mov r3, r0 +#else + return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), PWR_REGULATOR_VOLTAGE_SCALE1); +#endif /* PWR_CR1_VOS */ +} + 80035fa: 4618 mov r0, r3 + 80035fc: 3714 adds r7, #20 + 80035fe: 46bd mov sp, r7 + 8003600: bd90 pop {r4, r7, pc} + 8003602: bf00 nop + 8003604: 08007db0 .word 0x08007db0 + 8003608: 08007d70 .word 0x08007d70 + 800360c: 431bde83 .word 0x431bde83 + +08003610 <RCC_SetFlashLatency>: + * @param Flash_ClkSrcFreq Flash Clock Source (in MHz) + * @param VCORE_Voltage Current Vcore voltage (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2) + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t VCORE_Voltage) +{ + 8003610: b590 push {r4, r7, lr} + 8003612: b093 sub sp, #76 @ 0x4c + 8003614: af00 add r7, sp, #0 + 8003616: 6078 str r0, [r7, #4] + 8003618: 6039 str r1, [r7, #0] + /* Flash Clock source (HCLK4) range in MHz with a VCORE is range1 */ + const uint32_t FLASH_CLK_SRC_RANGE_VOS1[] = {18UL, 36UL, 54UL, 64UL}; + 800361a: 4b37 ldr r3, [pc, #220] @ (80036f8 <RCC_SetFlashLatency+0xe8>) + 800361c: f107 0428 add.w r4, r7, #40 @ 0x28 + 8003620: cb0f ldmia r3, {r0, r1, r2, r3} + 8003622: e884 000f stmia.w r4, {r0, r1, r2, r3} +#if defined(PWR_CR1_VOS) + /* Flash Clock source (HCLK4) range in MHz with a VCORE is range2 */ + const uint32_t FLASH_CLK_SRC_RANGE_VOS2[] = {6UL, 12UL, 16UL}; + 8003626: 4a35 ldr r2, [pc, #212] @ (80036fc <RCC_SetFlashLatency+0xec>) + 8003628: f107 031c add.w r3, r7, #28 + 800362c: ca07 ldmia r2, {r0, r1, r2} + 800362e: e883 0007 stmia.w r3, {r0, r1, r2} +#endif /* PWR_CR1_VOS */ + /* Flash Latency range */ + const uint32_t FLASH_LATENCY_RANGE[] = {FLASH_LATENCY_0, FLASH_LATENCY_1, FLASH_LATENCY_2, FLASH_LATENCY_3}; + 8003632: 4b33 ldr r3, [pc, #204] @ (8003700 <RCC_SetFlashLatency+0xf0>) + 8003634: f107 040c add.w r4, r7, #12 + 8003638: cb0f ldmia r3, {r0, r1, r2, r3} + 800363a: e884 000f stmia.w r4, {r0, r1, r2, r3} + uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ + 800363e: 2300 movs r3, #0 + 8003640: 647b str r3, [r7, #68] @ 0x44 + uint32_t tickstart; + +#if defined(PWR_CR1_VOS) + if (VCORE_Voltage == PWR_REGULATOR_VOLTAGE_SCALE1) + 8003642: 683b ldr r3, [r7, #0] + 8003644: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 8003648: d11a bne.n 8003680 <RCC_SetFlashLatency+0x70> + { + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) + 800364a: 2300 movs r3, #0 + 800364c: 643b str r3, [r7, #64] @ 0x40 + 800364e: e013 b.n 8003678 <RCC_SetFlashLatency+0x68> + { + if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS1[index]) + 8003650: 6c3b ldr r3, [r7, #64] @ 0x40 + 8003652: 009b lsls r3, r3, #2 + 8003654: 3348 adds r3, #72 @ 0x48 + 8003656: 443b add r3, r7 + 8003658: f853 3c20 ldr.w r3, [r3, #-32] + 800365c: 687a ldr r2, [r7, #4] + 800365e: 429a cmp r2, r3 + 8003660: d807 bhi.n 8003672 <RCC_SetFlashLatency+0x62> + { + latency = FLASH_LATENCY_RANGE[index]; + 8003662: 6c3b ldr r3, [r7, #64] @ 0x40 + 8003664: 009b lsls r3, r3, #2 + 8003666: 3348 adds r3, #72 @ 0x48 + 8003668: 443b add r3, r7 + 800366a: f853 3c3c ldr.w r3, [r3, #-60] + 800366e: 647b str r3, [r7, #68] @ 0x44 + break; + 8003670: e020 b.n 80036b4 <RCC_SetFlashLatency+0xa4> + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) + 8003672: 6c3b ldr r3, [r7, #64] @ 0x40 + 8003674: 3301 adds r3, #1 + 8003676: 643b str r3, [r7, #64] @ 0x40 + 8003678: 6c3b ldr r3, [r7, #64] @ 0x40 + 800367a: 2b03 cmp r3, #3 + 800367c: d9e8 bls.n 8003650 <RCC_SetFlashLatency+0x40> + 800367e: e019 b.n 80036b4 <RCC_SetFlashLatency+0xa4> + } + } + } + else /* PWR_REGULATOR_VOLTAGE_SCALE2 */ + { + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++) + 8003680: 2300 movs r3, #0 + 8003682: 63fb str r3, [r7, #60] @ 0x3c + 8003684: e013 b.n 80036ae <RCC_SetFlashLatency+0x9e> + { + if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS2[index]) + 8003686: 6bfb ldr r3, [r7, #60] @ 0x3c + 8003688: 009b lsls r3, r3, #2 + 800368a: 3348 adds r3, #72 @ 0x48 + 800368c: 443b add r3, r7 + 800368e: f853 3c2c ldr.w r3, [r3, #-44] + 8003692: 687a ldr r2, [r7, #4] + 8003694: 429a cmp r2, r3 + 8003696: d807 bhi.n 80036a8 <RCC_SetFlashLatency+0x98> + { + latency = FLASH_LATENCY_RANGE[index]; + 8003698: 6bfb ldr r3, [r7, #60] @ 0x3c + 800369a: 009b lsls r3, r3, #2 + 800369c: 3348 adds r3, #72 @ 0x48 + 800369e: 443b add r3, r7 + 80036a0: f853 3c3c ldr.w r3, [r3, #-60] + 80036a4: 647b str r3, [r7, #68] @ 0x44 + break; + 80036a6: e005 b.n 80036b4 <RCC_SetFlashLatency+0xa4> + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++) + 80036a8: 6bfb ldr r3, [r7, #60] @ 0x3c + 80036aa: 3301 adds r3, #1 + 80036ac: 63fb str r3, [r7, #60] @ 0x3c + 80036ae: 6bfb ldr r3, [r7, #60] @ 0x3c + 80036b0: 2b02 cmp r3, #2 + 80036b2: d9e8 bls.n 8003686 <RCC_SetFlashLatency+0x76> + break; + } + } +#endif /* PWR_CR1_VOS */ + + __HAL_FLASH_SET_LATENCY(latency); + 80036b4: 4b13 ldr r3, [pc, #76] @ (8003704 <RCC_SetFlashLatency+0xf4>) + 80036b6: 681b ldr r3, [r3, #0] + 80036b8: f023 0207 bic.w r2, r3, #7 + 80036bc: 4911 ldr r1, [pc, #68] @ (8003704 <RCC_SetFlashLatency+0xf4>) + 80036be: 6c7b ldr r3, [r7, #68] @ 0x44 + 80036c0: 4313 orrs r3, r2 + 80036c2: 600b str r3, [r1, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80036c4: f7fe f96e bl 80019a4 <HAL_GetTick> + 80036c8: 63b8 str r0, [r7, #56] @ 0x38 + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + while (__HAL_FLASH_GET_LATENCY() != latency) + 80036ca: e008 b.n 80036de <RCC_SetFlashLatency+0xce> + { + if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) + 80036cc: f7fe f96a bl 80019a4 <HAL_GetTick> + 80036d0: 4602 mov r2, r0 + 80036d2: 6bbb ldr r3, [r7, #56] @ 0x38 + 80036d4: 1ad3 subs r3, r2, r3 + 80036d6: 2b02 cmp r3, #2 + 80036d8: d901 bls.n 80036de <RCC_SetFlashLatency+0xce> + { + return HAL_TIMEOUT; + 80036da: 2303 movs r3, #3 + 80036dc: e007 b.n 80036ee <RCC_SetFlashLatency+0xde> + while (__HAL_FLASH_GET_LATENCY() != latency) + 80036de: 4b09 ldr r3, [pc, #36] @ (8003704 <RCC_SetFlashLatency+0xf4>) + 80036e0: 681b ldr r3, [r3, #0] + 80036e2: f003 0307 and.w r3, r3, #7 + 80036e6: 6c7a ldr r2, [r7, #68] @ 0x44 + 80036e8: 429a cmp r2, r3 + 80036ea: d1ef bne.n 80036cc <RCC_SetFlashLatency+0xbc> + } + } + return HAL_OK; + 80036ec: 2300 movs r3, #0 +} + 80036ee: 4618 mov r0, r3 + 80036f0: 374c adds r7, #76 @ 0x4c + 80036f2: 46bd mov sp, r7 + 80036f4: bd90 pop {r4, r7, pc} + 80036f6: bf00 nop + 80036f8: 08007bd0 .word 0x08007bd0 + 80036fc: 08007be0 .word 0x08007be0 + 8003700: 08007bec .word 0x08007bec + 8003704: 58004000 .word 0x58004000 + +08003708 <LL_RCC_LSE_IsEnabled>: +{ + 8003708: b480 push {r7} + 800370a: af00 add r7, sp, #0 + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == (RCC_BDCR_LSEON)) ? 1UL : 0UL); + 800370c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003710: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003714: f003 0301 and.w r3, r3, #1 + 8003718: 2b01 cmp r3, #1 + 800371a: d101 bne.n 8003720 <LL_RCC_LSE_IsEnabled+0x18> + 800371c: 2301 movs r3, #1 + 800371e: e000 b.n 8003722 <LL_RCC_LSE_IsEnabled+0x1a> + 8003720: 2300 movs r3, #0 +} + 8003722: 4618 mov r0, r3 + 8003724: 46bd mov sp, r7 + 8003726: f85d 7b04 ldr.w r7, [sp], #4 + 800372a: 4770 bx lr + +0800372c <LL_RCC_LSE_IsReady>: +{ + 800372c: b480 push {r7} + 800372e: af00 add r7, sp, #0 + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); + 8003730: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003734: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003738: f003 0302 and.w r3, r3, #2 + 800373c: 2b02 cmp r3, #2 + 800373e: d101 bne.n 8003744 <LL_RCC_LSE_IsReady+0x18> + 8003740: 2301 movs r3, #1 + 8003742: e000 b.n 8003746 <LL_RCC_LSE_IsReady+0x1a> + 8003744: 2300 movs r3, #0 +} + 8003746: 4618 mov r0, r3 + 8003748: 46bd mov sp, r7 + 800374a: f85d 7b04 ldr.w r7, [sp], #4 + 800374e: 4770 bx lr + +08003750 <LL_RCC_SetRFWKPClockSource>: +{ + 8003750: b480 push {r7} + 8003752: b083 sub sp, #12 + 8003754: af00 add r7, sp, #0 + 8003756: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CSR, RCC_CSR_RFWKPSEL, Source); + 8003758: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800375c: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8003760: f423 4240 bic.w r2, r3, #49152 @ 0xc000 + 8003764: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003768: 687b ldr r3, [r7, #4] + 800376a: 4313 orrs r3, r2 + 800376c: f8c1 3094 str.w r3, [r1, #148] @ 0x94 +} + 8003770: bf00 nop + 8003772: 370c adds r7, #12 + 8003774: 46bd mov sp, r7 + 8003776: f85d 7b04 ldr.w r7, [sp], #4 + 800377a: 4770 bx lr + +0800377c <LL_RCC_SetSMPSClockSource>: +{ + 800377c: b480 push {r7} + 800377e: b083 sub sp, #12 + 8003780: af00 add r7, sp, #0 + 8003782: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->SMPSCR, RCC_SMPSCR_SMPSSEL, SMPSSource); + 8003784: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003788: 6a5b ldr r3, [r3, #36] @ 0x24 + 800378a: f023 0203 bic.w r2, r3, #3 + 800378e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003792: 687b ldr r3, [r7, #4] + 8003794: 4313 orrs r3, r2 + 8003796: 624b str r3, [r1, #36] @ 0x24 +} + 8003798: bf00 nop + 800379a: 370c adds r7, #12 + 800379c: 46bd mov sp, r7 + 800379e: f85d 7b04 ldr.w r7, [sp], #4 + 80037a2: 4770 bx lr + +080037a4 <LL_RCC_SetSMPSPrescaler>: +{ + 80037a4: b480 push {r7} + 80037a6: b083 sub sp, #12 + 80037a8: af00 add r7, sp, #0 + 80037aa: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->SMPSCR, RCC_SMPSCR_SMPSDIV, Prescaler); + 80037ac: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80037b0: 6a5b ldr r3, [r3, #36] @ 0x24 + 80037b2: f023 0230 bic.w r2, r3, #48 @ 0x30 + 80037b6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80037ba: 687b ldr r3, [r7, #4] + 80037bc: 4313 orrs r3, r2 + 80037be: 624b str r3, [r1, #36] @ 0x24 +} + 80037c0: bf00 nop + 80037c2: 370c adds r7, #12 + 80037c4: 46bd mov sp, r7 + 80037c6: f85d 7b04 ldr.w r7, [sp], #4 + 80037ca: 4770 bx lr + +080037cc <LL_RCC_SetUSARTClockSource>: +{ + 80037cc: b480 push {r7} + 80037ce: b083 sub sp, #12 + 80037d0: af00 add r7, sp, #0 + 80037d2: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, USARTxSource); + 80037d4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80037d8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 80037dc: f023 0203 bic.w r2, r3, #3 + 80037e0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80037e4: 687b ldr r3, [r7, #4] + 80037e6: 4313 orrs r3, r2 + 80037e8: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 80037ec: bf00 nop + 80037ee: 370c adds r7, #12 + 80037f0: 46bd mov sp, r7 + 80037f2: f85d 7b04 ldr.w r7, [sp], #4 + 80037f6: 4770 bx lr + +080037f8 <LL_RCC_SetLPUARTClockSource>: +{ + 80037f8: b480 push {r7} + 80037fa: b083 sub sp, #12 + 80037fc: af00 add r7, sp, #0 + 80037fe: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource); + 8003800: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003804: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8003808: f423 6240 bic.w r2, r3, #3072 @ 0xc00 + 800380c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003810: 687b ldr r3, [r7, #4] + 8003812: 4313 orrs r3, r2 + 8003814: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003818: bf00 nop + 800381a: 370c adds r7, #12 + 800381c: 46bd mov sp, r7 + 800381e: f85d 7b04 ldr.w r7, [sp], #4 + 8003822: 4770 bx lr + +08003824 <LL_RCC_SetI2CClockSource>: +{ + 8003824: b480 push {r7} + 8003826: b083 sub sp, #12 + 8003828: af00 add r7, sp, #0 + 800382a: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000U), ((I2CxSource << 4) & 0x000FF000U)); + 800382c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003830: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 + 8003834: 687b ldr r3, [r7, #4] + 8003836: 091b lsrs r3, r3, #4 + 8003838: f403 237f and.w r3, r3, #1044480 @ 0xff000 + 800383c: 43db mvns r3, r3 + 800383e: 401a ands r2, r3 + 8003840: 687b ldr r3, [r7, #4] + 8003842: 011b lsls r3, r3, #4 + 8003844: f403 237f and.w r3, r3, #1044480 @ 0xff000 + 8003848: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800384c: 4313 orrs r3, r2 + 800384e: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003852: bf00 nop + 8003854: 370c adds r7, #12 + 8003856: 46bd mov sp, r7 + 8003858: f85d 7b04 ldr.w r7, [sp], #4 + 800385c: 4770 bx lr + +0800385e <LL_RCC_SetLPTIMClockSource>: +{ + 800385e: b480 push {r7} + 8003860: b083 sub sp, #12 + 8003862: af00 add r7, sp, #0 + 8003864: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16)); + 8003866: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800386a: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 + 800386e: 687b ldr r3, [r7, #4] + 8003870: 0c1b lsrs r3, r3, #16 + 8003872: 041b lsls r3, r3, #16 + 8003874: 43db mvns r3, r3 + 8003876: 401a ands r2, r3 + 8003878: 687b ldr r3, [r7, #4] + 800387a: 041b lsls r3, r3, #16 + 800387c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003880: 4313 orrs r3, r2 + 8003882: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003886: bf00 nop + 8003888: 370c adds r7, #12 + 800388a: 46bd mov sp, r7 + 800388c: f85d 7b04 ldr.w r7, [sp], #4 + 8003890: 4770 bx lr + +08003892 <LL_RCC_SetSAIClockSource>: +{ + 8003892: b480 push {r7} + 8003894: b083 sub sp, #12 + 8003896: af00 add r7, sp, #0 + 8003898: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource); + 800389a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800389e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 80038a2: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 + 80038a6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80038aa: 687b ldr r3, [r7, #4] + 80038ac: 4313 orrs r3, r2 + 80038ae: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 80038b2: bf00 nop + 80038b4: 370c adds r7, #12 + 80038b6: 46bd mov sp, r7 + 80038b8: f85d 7b04 ldr.w r7, [sp], #4 + 80038bc: 4770 bx lr + +080038be <LL_RCC_SetRNGClockSource>: +{ + 80038be: b480 push {r7} + 80038c0: b083 sub sp, #12 + 80038c2: af00 add r7, sp, #0 + 80038c4: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource); + 80038c6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80038ca: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 80038ce: f023 4240 bic.w r2, r3, #3221225472 @ 0xc0000000 + 80038d2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80038d6: 687b ldr r3, [r7, #4] + 80038d8: 4313 orrs r3, r2 + 80038da: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 80038de: bf00 nop + 80038e0: 370c adds r7, #12 + 80038e2: 46bd mov sp, r7 + 80038e4: f85d 7b04 ldr.w r7, [sp], #4 + 80038e8: 4770 bx lr + +080038ea <LL_RCC_SetCLK48ClockSource>: +{ + 80038ea: b480 push {r7} + 80038ec: b083 sub sp, #12 + 80038ee: af00 add r7, sp, #0 + 80038f0: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, CLK48xSource); + 80038f2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80038f6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 80038fa: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000 + 80038fe: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003902: 687b ldr r3, [r7, #4] + 8003904: 4313 orrs r3, r2 + 8003906: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 800390a: bf00 nop + 800390c: 370c adds r7, #12 + 800390e: 46bd mov sp, r7 + 8003910: f85d 7b04 ldr.w r7, [sp], #4 + 8003914: 4770 bx lr + +08003916 <LL_RCC_SetUSBClockSource>: +{ + 8003916: b580 push {r7, lr} + 8003918: b082 sub sp, #8 + 800391a: af00 add r7, sp, #0 + 800391c: 6078 str r0, [r7, #4] + LL_RCC_SetCLK48ClockSource(USBxSource); + 800391e: 6878 ldr r0, [r7, #4] + 8003920: f7ff ffe3 bl 80038ea <LL_RCC_SetCLK48ClockSource> +} + 8003924: bf00 nop + 8003926: 3708 adds r7, #8 + 8003928: 46bd mov sp, r7 + 800392a: bd80 pop {r7, pc} + +0800392c <LL_RCC_SetADCClockSource>: +{ + 800392c: b480 push {r7} + 800392e: b083 sub sp, #12 + 8003930: af00 add r7, sp, #0 + 8003932: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); + 8003934: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003938: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 800393c: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000 + 8003940: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003944: 687b ldr r3, [r7, #4] + 8003946: 4313 orrs r3, r2 + 8003948: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 800394c: bf00 nop + 800394e: 370c adds r7, #12 + 8003950: 46bd mov sp, r7 + 8003952: f85d 7b04 ldr.w r7, [sp], #4 + 8003956: 4770 bx lr + +08003958 <LL_RCC_SetRTCClockSource>: +{ + 8003958: b480 push {r7} + 800395a: b083 sub sp, #12 + 800395c: af00 add r7, sp, #0 + 800395e: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); + 8003960: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003964: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003968: f423 7240 bic.w r2, r3, #768 @ 0x300 + 800396c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003970: 687b ldr r3, [r7, #4] + 8003972: 4313 orrs r3, r2 + 8003974: f8c1 3090 str.w r3, [r1, #144] @ 0x90 +} + 8003978: bf00 nop + 800397a: 370c adds r7, #12 + 800397c: 46bd mov sp, r7 + 800397e: f85d 7b04 ldr.w r7, [sp], #4 + 8003982: 4770 bx lr + +08003984 <LL_RCC_GetRTCClockSource>: +{ + 8003984: b480 push {r7} + 8003986: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); + 8003988: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800398c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003990: f403 7340 and.w r3, r3, #768 @ 0x300 +} + 8003994: 4618 mov r0, r3 + 8003996: 46bd mov sp, r7 + 8003998: f85d 7b04 ldr.w r7, [sp], #4 + 800399c: 4770 bx lr + +0800399e <LL_RCC_ForceBackupDomainReset>: +{ + 800399e: b480 push {r7} + 80039a0: af00 add r7, sp, #0 + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); + 80039a2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80039a6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80039aa: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80039ae: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 80039b2: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 80039b6: bf00 nop + 80039b8: 46bd mov sp, r7 + 80039ba: f85d 7b04 ldr.w r7, [sp], #4 + 80039be: 4770 bx lr + +080039c0 <LL_RCC_ReleaseBackupDomainReset>: +{ + 80039c0: b480 push {r7} + 80039c2: af00 add r7, sp, #0 + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); + 80039c4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80039c8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80039cc: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80039d0: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 80039d4: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 80039d8: bf00 nop + 80039da: 46bd mov sp, r7 + 80039dc: f85d 7b04 ldr.w r7, [sp], #4 + 80039e0: 4770 bx lr + +080039e2 <LL_RCC_PLLSAI1_Enable>: +{ + 80039e2: b480 push {r7} + 80039e4: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON); + 80039e6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80039ea: 681b ldr r3, [r3, #0] + 80039ec: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80039f0: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 + 80039f4: 6013 str r3, [r2, #0] +} + 80039f6: bf00 nop + 80039f8: 46bd mov sp, r7 + 80039fa: f85d 7b04 ldr.w r7, [sp], #4 + 80039fe: 4770 bx lr + +08003a00 <LL_RCC_PLLSAI1_Disable>: +{ + 8003a00: b480 push {r7} + 8003a02: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON); + 8003a04: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003a08: 681b ldr r3, [r3, #0] + 8003a0a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003a0e: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 + 8003a12: 6013 str r3, [r2, #0] +} + 8003a14: bf00 nop + 8003a16: 46bd mov sp, r7 + 8003a18: f85d 7b04 ldr.w r7, [sp], #4 + 8003a1c: 4770 bx lr + +08003a1e <LL_RCC_PLLSAI1_IsReady>: +{ + 8003a1e: b480 push {r7} + 8003a20: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) ? 1UL : 0UL); + 8003a22: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003a26: 681b ldr r3, [r3, #0] + 8003a28: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 + 8003a2c: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 + 8003a30: d101 bne.n 8003a36 <LL_RCC_PLLSAI1_IsReady+0x18> + 8003a32: 2301 movs r3, #1 + 8003a34: e000 b.n 8003a38 <LL_RCC_PLLSAI1_IsReady+0x1a> + 8003a36: 2300 movs r3, #0 +} + 8003a38: 4618 mov r0, r3 + 8003a3a: 46bd mov sp, r7 + 8003a3c: f85d 7b04 ldr.w r7, [sp], #4 + 8003a40: 4770 bx lr + +08003a42 <HAL_RCCEx_PeriphCLKConfig>: + * the RTC clock source: in this case the access to Backup domain is enabled. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + 8003a42: b580 push {r7, lr} + 8003a44: b088 sub sp, #32 + 8003a46: af00 add r7, sp, #0 + 8003a48: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + 8003a4a: 2300 movs r3, #0 + 8003a4c: 77fb strb r3, [r7, #31] + HAL_StatusTypeDef status = HAL_OK; /* Final status */ + 8003a4e: 2300 movs r3, #0 + 8003a50: 77bb strb r3, [r7, #30] + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + +#if defined(SAI1) + /*-------------------------- SAI1 clock source configuration ---------------------*/ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)) + 8003a52: 687b ldr r3, [r7, #4] + 8003a54: 681b ldr r3, [r3, #0] + 8003a56: f003 0340 and.w r3, r3, #64 @ 0x40 + 8003a5a: 2b00 cmp r3, #0 + 8003a5c: d034 beq.n 8003ac8 <HAL_RCCEx_PeriphCLKConfig+0x86> + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection)); + + switch (PeriphClkInit->Sai1ClockSelection) + 8003a5e: 687b ldr r3, [r7, #4] + 8003a60: 6b1b ldr r3, [r3, #48] @ 0x30 + 8003a62: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000 + 8003a66: d021 beq.n 8003aac <HAL_RCCEx_PeriphCLKConfig+0x6a> + 8003a68: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000 + 8003a6c: d81b bhi.n 8003aa6 <HAL_RCCEx_PeriphCLKConfig+0x64> + 8003a6e: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 + 8003a72: d01d beq.n 8003ab0 <HAL_RCCEx_PeriphCLKConfig+0x6e> + 8003a74: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 + 8003a78: d815 bhi.n 8003aa6 <HAL_RCCEx_PeriphCLKConfig+0x64> + 8003a7a: 2b00 cmp r3, #0 + 8003a7c: d00b beq.n 8003a96 <HAL_RCCEx_PeriphCLKConfig+0x54> + 8003a7e: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 + 8003a82: d110 bne.n 8003aa6 <HAL_RCCEx_PeriphCLKConfig+0x64> + { + case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1 */ + /* Enable SAI1 Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI1CLK); + 8003a84: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003a88: 68db ldr r3, [r3, #12] + 8003a8a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003a8e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8003a92: 60d3 str r3, [r2, #12] + + /* SAI1 clock source config set later after clock selection check */ + break; + 8003a94: e00d b.n 8003ab2 <HAL_RCCEx_PeriphCLKConfig+0x70> + + case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1 */ + /* PLLSAI1 parameters N & P configuration and clock output (PLLSAI1ClockOut) */ + ret = RCCEx_PLLSAI1_ConfigNP(&(PeriphClkInit->PLLSAI1)); + 8003a96: 687b ldr r3, [r7, #4] + 8003a98: 3304 adds r3, #4 + 8003a9a: 4618 mov r0, r3 + 8003a9c: f000 f947 bl 8003d2e <RCCEx_PLLSAI1_ConfigNP> + 8003aa0: 4603 mov r3, r0 + 8003aa2: 77fb strb r3, [r7, #31] + /* SAI1 clock source config set later after clock selection check */ + break; + 8003aa4: e005 b.n 8003ab2 <HAL_RCCEx_PeriphCLKConfig+0x70> + case RCC_SAI1CLKSOURCE_HSI: + + break; + + default: + ret = HAL_ERROR; + 8003aa6: 2301 movs r3, #1 + 8003aa8: 77fb strb r3, [r7, #31] + break; + 8003aaa: e002 b.n 8003ab2 <HAL_RCCEx_PeriphCLKConfig+0x70> + break; + 8003aac: bf00 nop + 8003aae: e000 b.n 8003ab2 <HAL_RCCEx_PeriphCLKConfig+0x70> + break; + 8003ab0: bf00 nop + } + + if (ret == HAL_OK) + 8003ab2: 7ffb ldrb r3, [r7, #31] + 8003ab4: 2b00 cmp r3, #0 + 8003ab6: d105 bne.n 8003ac4 <HAL_RCCEx_PeriphCLKConfig+0x82> + { + /* Set the source of SAI1 clock*/ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + 8003ab8: 687b ldr r3, [r7, #4] + 8003aba: 6b1b ldr r3, [r3, #48] @ 0x30 + 8003abc: 4618 mov r0, r3 + 8003abe: f7ff fee8 bl 8003892 <LL_RCC_SetSAIClockSource> + 8003ac2: e001 b.n 8003ac8 <HAL_RCCEx_PeriphCLKConfig+0x86> + } + else + { + /* set overall return value */ + status = ret; + 8003ac4: 7ffb ldrb r3, [r7, #31] + 8003ac6: 77bb strb r3, [r7, #30] + } + } +#endif /* SAI1 */ + + /*-------------------------- RTC clock source configuration ----------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + 8003ac8: 687b ldr r3, [r7, #4] + 8003aca: 681b ldr r3, [r3, #0] + 8003acc: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8003ad0: 2b00 cmp r3, #0 + 8003ad2: d046 beq.n 8003b62 <HAL_RCCEx_PeriphCLKConfig+0x120> + { + uint32_t rtcclocksource = LL_RCC_GetRTCClockSource(); + 8003ad4: f7ff ff56 bl 8003984 <LL_RCC_GetRTCClockSource> + 8003ad8: 61b8 str r0, [r7, #24] + + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Configure the clock source only if a different source is expected */ + if (rtcclocksource != PeriphClkInit->RTCClockSelection) + 8003ada: 687b ldr r3, [r7, #4] + 8003adc: 6c1b ldr r3, [r3, #64] @ 0x40 + 8003ade: 69ba ldr r2, [r7, #24] + 8003ae0: 429a cmp r2, r3 + 8003ae2: d03c beq.n 8003b5e <HAL_RCCEx_PeriphCLKConfig+0x11c> + { + /* Enable write access to Backup domain */ + HAL_PWR_EnableBkUpAccess(); + 8003ae4: f7fe fc80 bl 80023e8 <HAL_PWR_EnableBkUpAccess> + + /* If a clock source is not yet selected */ + if (rtcclocksource == RCC_RTCCLKSOURCE_NONE) + 8003ae8: 69bb ldr r3, [r7, #24] + 8003aea: 2b00 cmp r3, #0 + 8003aec: d105 bne.n 8003afa <HAL_RCCEx_PeriphCLKConfig+0xb8> + { + /* Directly set the configuration of the clock source selection */ + LL_RCC_SetRTCClockSource(PeriphClkInit->RTCClockSelection); + 8003aee: 687b ldr r3, [r7, #4] + 8003af0: 6c1b ldr r3, [r3, #64] @ 0x40 + 8003af2: 4618 mov r0, r3 + 8003af4: f7ff ff30 bl 8003958 <LL_RCC_SetRTCClockSource> + 8003af8: e02e b.n 8003b58 <HAL_RCCEx_PeriphCLKConfig+0x116> + } + else /* A clock source is already selected */ + { + /* Store the content of BDCR register before the reset of Backup Domain */ + uint32_t bdcr = LL_RCC_ReadReg(BDCR); + 8003afa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003afe: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003b02: 617b str r3, [r7, #20] + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + LL_RCC_ForceBackupDomainReset(); + 8003b04: f7ff ff4b bl 800399e <LL_RCC_ForceBackupDomainReset> + LL_RCC_ReleaseBackupDomainReset(); + 8003b08: f7ff ff5a bl 80039c0 <LL_RCC_ReleaseBackupDomainReset> + + /* Set the value of the clock source selection */ + MODIFY_REG(bdcr, RCC_BDCR_RTCSEL, PeriphClkInit->RTCClockSelection); + 8003b0c: 697b ldr r3, [r7, #20] + 8003b0e: f423 7240 bic.w r2, r3, #768 @ 0x300 + 8003b12: 687b ldr r3, [r7, #4] + 8003b14: 6c1b ldr r3, [r3, #64] @ 0x40 + 8003b16: 4313 orrs r3, r2 + 8003b18: 617b str r3, [r7, #20] + + /* Restore the content of BDCR register */ + LL_RCC_WriteReg(BDCR, bdcr); + 8003b1a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003b1e: 697b ldr r3, [r7, #20] + 8003b20: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (LL_RCC_LSE_IsEnabled() == 1U) + 8003b24: f7ff fdf0 bl 8003708 <LL_RCC_LSE_IsEnabled> + 8003b28: 4603 mov r3, r0 + 8003b2a: 2b01 cmp r3, #1 + 8003b2c: d114 bne.n 8003b58 <HAL_RCCEx_PeriphCLKConfig+0x116> + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003b2e: f7fd ff39 bl 80019a4 <HAL_GetTick> + 8003b32: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while (LL_RCC_LSE_IsReady() != 1U) + 8003b34: e00b b.n 8003b4e <HAL_RCCEx_PeriphCLKConfig+0x10c> + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8003b36: f7fd ff35 bl 80019a4 <HAL_GetTick> + 8003b3a: 4602 mov r2, r0 + 8003b3c: 693b ldr r3, [r7, #16] + 8003b3e: 1ad3 subs r3, r2, r3 + 8003b40: f241 3288 movw r2, #5000 @ 0x1388 + 8003b44: 4293 cmp r3, r2 + 8003b46: d902 bls.n 8003b4e <HAL_RCCEx_PeriphCLKConfig+0x10c> + { + ret = HAL_TIMEOUT; + 8003b48: 2303 movs r3, #3 + 8003b4a: 77fb strb r3, [r7, #31] + break; + 8003b4c: e004 b.n 8003b58 <HAL_RCCEx_PeriphCLKConfig+0x116> + while (LL_RCC_LSE_IsReady() != 1U) + 8003b4e: f7ff fded bl 800372c <LL_RCC_LSE_IsReady> + 8003b52: 4603 mov r3, r0 + 8003b54: 2b01 cmp r3, #1 + 8003b56: d1ee bne.n 8003b36 <HAL_RCCEx_PeriphCLKConfig+0xf4> + } + } + } + + /* set overall return value */ + status = ret; + 8003b58: 7ffb ldrb r3, [r7, #31] + 8003b5a: 77bb strb r3, [r7, #30] + 8003b5c: e001 b.n 8003b62 <HAL_RCCEx_PeriphCLKConfig+0x120> + } + else + { + /* set overall return value */ + status = ret; + 8003b5e: 7ffb ldrb r3, [r7, #31] + 8003b60: 77bb strb r3, [r7, #30] + } + + } + + /*-------------------------- USART1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + 8003b62: 687b ldr r3, [r7, #4] + 8003b64: 681b ldr r3, [r3, #0] + 8003b66: f003 0301 and.w r3, r3, #1 + 8003b6a: 2b00 cmp r3, #0 + 8003b6c: d004 beq.n 8003b78 <HAL_RCCEx_PeriphCLKConfig+0x136> + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + 8003b6e: 687b ldr r3, [r7, #4] + 8003b70: 699b ldr r3, [r3, #24] + 8003b72: 4618 mov r0, r3 + 8003b74: f7ff fe2a bl 80037cc <LL_RCC_SetUSARTClockSource> + } + +#if defined(LPUART1) + /*-------------------------- LPUART1 clock source configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + 8003b78: 687b ldr r3, [r7, #4] + 8003b7a: 681b ldr r3, [r3, #0] + 8003b7c: f003 0302 and.w r3, r3, #2 + 8003b80: 2b00 cmp r3, #0 + 8003b82: d004 beq.n 8003b8e <HAL_RCCEx_PeriphCLKConfig+0x14c> + { + /* Check the parameters */ + assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); + + /* Configure the LPUAR1 clock source */ + __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + 8003b84: 687b ldr r3, [r7, #4] + 8003b86: 69db ldr r3, [r3, #28] + 8003b88: 4618 mov r0, r3 + 8003b8a: f7ff fe35 bl 80037f8 <LL_RCC_SetLPUARTClockSource> + } +#endif /* LPUART1 */ + + /*-------------------------- LPTIM1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) + 8003b8e: 687b ldr r3, [r7, #4] + 8003b90: 681b ldr r3, [r3, #0] + 8003b92: f003 0310 and.w r3, r3, #16 + 8003b96: 2b00 cmp r3, #0 + 8003b98: d004 beq.n 8003ba4 <HAL_RCCEx_PeriphCLKConfig+0x162> + { + assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + 8003b9a: 687b ldr r3, [r7, #4] + 8003b9c: 6a9b ldr r3, [r3, #40] @ 0x28 + 8003b9e: 4618 mov r0, r3 + 8003ba0: f7ff fe5d bl 800385e <LL_RCC_SetLPTIMClockSource> + } + + /*-------------------------- LPTIM2 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) + 8003ba4: 687b ldr r3, [r7, #4] + 8003ba6: 681b ldr r3, [r3, #0] + 8003ba8: f003 0320 and.w r3, r3, #32 + 8003bac: 2b00 cmp r3, #0 + 8003bae: d004 beq.n 8003bba <HAL_RCCEx_PeriphCLKConfig+0x178> + { + assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection)); + __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); + 8003bb0: 687b ldr r3, [r7, #4] + 8003bb2: 6adb ldr r3, [r3, #44] @ 0x2c + 8003bb4: 4618 mov r0, r3 + 8003bb6: f7ff fe52 bl 800385e <LL_RCC_SetLPTIMClockSource> + } + + /*-------------------------- I2C1 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 8003bba: 687b ldr r3, [r7, #4] + 8003bbc: 681b ldr r3, [r3, #0] + 8003bbe: f003 0304 and.w r3, r3, #4 + 8003bc2: 2b00 cmp r3, #0 + 8003bc4: d004 beq.n 8003bd0 <HAL_RCCEx_PeriphCLKConfig+0x18e> + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 8003bc6: 687b ldr r3, [r7, #4] + 8003bc8: 6a1b ldr r3, [r3, #32] + 8003bca: 4618 mov r0, r3 + 8003bcc: f7ff fe2a bl 8003824 <LL_RCC_SetI2CClockSource> + } + +#if defined(I2C3) + /*-------------------------- I2C3 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + 8003bd0: 687b ldr r3, [r7, #4] + 8003bd2: 681b ldr r3, [r3, #0] + 8003bd4: f003 0308 and.w r3, r3, #8 + 8003bd8: 2b00 cmp r3, #0 + 8003bda: d004 beq.n 8003be6 <HAL_RCCEx_PeriphCLKConfig+0x1a4> + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + 8003bdc: 687b ldr r3, [r7, #4] + 8003bde: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003be0: 4618 mov r0, r3 + 8003be2: f7ff fe1f bl 8003824 <LL_RCC_SetI2CClockSource> + } +#endif /* I2C3 */ + +#if defined(USB) + /*-------------------------- USB clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) + 8003be6: 687b ldr r3, [r7, #4] + 8003be8: 681b ldr r3, [r3, #0] + 8003bea: f403 7380 and.w r3, r3, #256 @ 0x100 + 8003bee: 2b00 cmp r3, #0 + 8003bf0: d022 beq.n 8003c38 <HAL_RCCEx_PeriphCLKConfig+0x1f6> + { + assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + 8003bf2: 687b ldr r3, [r7, #4] + 8003bf4: 6b5b ldr r3, [r3, #52] @ 0x34 + 8003bf6: 4618 mov r0, r3 + 8003bf8: f7ff fe8d bl 8003916 <LL_RCC_SetUSBClockSource> + + if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) + 8003bfc: 687b ldr r3, [r7, #4] + 8003bfe: 6b5b ldr r3, [r3, #52] @ 0x34 + 8003c00: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 + 8003c04: d107 bne.n 8003c16 <HAL_RCCEx_PeriphCLKConfig+0x1d4> + { + /* Enable PLLQ output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_USBCLK); + 8003c06: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003c0a: 68db ldr r3, [r3, #12] + 8003c0c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003c10: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 + 8003c14: 60d3 str r3, [r2, #12] + } +#if defined(SAI1) + if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1) + 8003c16: 687b ldr r3, [r7, #4] + 8003c18: 6b5b ldr r3, [r3, #52] @ 0x34 + 8003c1a: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 + 8003c1e: d10b bne.n 8003c38 <HAL_RCCEx_PeriphCLKConfig+0x1f6> + { + /* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */ + ret = RCCEx_PLLSAI1_ConfigNQ(&(PeriphClkInit->PLLSAI1)); + 8003c20: 687b ldr r3, [r7, #4] + 8003c22: 3304 adds r3, #4 + 8003c24: 4618 mov r0, r3 + 8003c26: f000 f8dd bl 8003de4 <RCCEx_PLLSAI1_ConfigNQ> + 8003c2a: 4603 mov r3, r0 + 8003c2c: 77fb strb r3, [r7, #31] + + if (ret != HAL_OK) + 8003c2e: 7ffb ldrb r3, [r7, #31] + 8003c30: 2b00 cmp r3, #0 + 8003c32: d001 beq.n 8003c38 <HAL_RCCEx_PeriphCLKConfig+0x1f6> + { + /* set overall return value */ + status = ret; + 8003c34: 7ffb ldrb r3, [r7, #31] + 8003c36: 77bb strb r3, [r7, #30] +#endif /* SAI1 */ + } +#endif /* USB */ + + /*-------------------------- RNG clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) + 8003c38: 687b ldr r3, [r7, #4] + 8003c3a: 681b ldr r3, [r3, #0] + 8003c3c: f403 7300 and.w r3, r3, #512 @ 0x200 + 8003c40: 2b00 cmp r3, #0 + 8003c42: d02b beq.n 8003c9c <HAL_RCCEx_PeriphCLKConfig+0x25a> + { + /* Check the parameters */ + assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); + + /* Configure the RNG clock source */ + __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); + 8003c44: 687b ldr r3, [r7, #4] + 8003c46: 6b9b ldr r3, [r3, #56] @ 0x38 + 8003c48: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8003c4c: d008 beq.n 8003c60 <HAL_RCCEx_PeriphCLKConfig+0x21e> + 8003c4e: 687b ldr r3, [r7, #4] + 8003c50: 6b9b ldr r3, [r3, #56] @ 0x38 + 8003c52: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 + 8003c56: d003 beq.n 8003c60 <HAL_RCCEx_PeriphCLKConfig+0x21e> + 8003c58: 687b ldr r3, [r7, #4] + 8003c5a: 6b9b ldr r3, [r3, #56] @ 0x38 + 8003c5c: 2b00 cmp r3, #0 + 8003c5e: d105 bne.n 8003c6c <HAL_RCCEx_PeriphCLKConfig+0x22a> + 8003c60: 687b ldr r3, [r7, #4] + 8003c62: 6b9b ldr r3, [r3, #56] @ 0x38 + 8003c64: 4618 mov r0, r3 + 8003c66: f7ff fe2a bl 80038be <LL_RCC_SetRNGClockSource> + 8003c6a: e00a b.n 8003c82 <HAL_RCCEx_PeriphCLKConfig+0x240> + 8003c6c: 687b ldr r3, [r7, #4] + 8003c6e: 6b9b ldr r3, [r3, #56] @ 0x38 + 8003c70: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8003c74: 60fb str r3, [r7, #12] + 8003c76: 2000 movs r0, #0 + 8003c78: f7ff fe21 bl 80038be <LL_RCC_SetRNGClockSource> + 8003c7c: 68f8 ldr r0, [r7, #12] + 8003c7e: f7ff fe34 bl 80038ea <LL_RCC_SetCLK48ClockSource> + + if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) + 8003c82: 687b ldr r3, [r7, #4] + 8003c84: 6b9b ldr r3, [r3, #56] @ 0x38 + 8003c86: f1b3 5fc0 cmp.w r3, #402653184 @ 0x18000000 + 8003c8a: d107 bne.n 8003c9c <HAL_RCCEx_PeriphCLKConfig+0x25a> + { + /* Enable PLLQ output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_RNGCLK); + 8003c8c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003c90: 68db ldr r3, [r3, #12] + 8003c92: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003c96: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 + 8003c9a: 60d3 str r3, [r2, #12] + } + } + + /*-------------------------- ADC clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + 8003c9c: 687b ldr r3, [r7, #4] + 8003c9e: 681b ldr r3, [r3, #0] + 8003ca0: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8003ca4: 2b00 cmp r3, #0 + 8003ca6: d022 beq.n 8003cee <HAL_RCCEx_PeriphCLKConfig+0x2ac> + { + /* Check the parameters */ + assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); + + /* Configure the ADC interface clock source */ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + 8003ca8: 687b ldr r3, [r7, #4] + 8003caa: 6bdb ldr r3, [r3, #60] @ 0x3c + 8003cac: 4618 mov r0, r3 + 8003cae: f7ff fe3d bl 800392c <LL_RCC_SetADCClockSource> + + if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLL) + 8003cb2: 687b ldr r3, [r7, #4] + 8003cb4: 6bdb ldr r3, [r3, #60] @ 0x3c + 8003cb6: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 + 8003cba: d107 bne.n 8003ccc <HAL_RCCEx_PeriphCLKConfig+0x28a> + { + /* Enable RCC_PLL_RNGCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); + 8003cbc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003cc0: 68db ldr r3, [r3, #12] + 8003cc2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003cc6: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8003cca: 60d3 str r3, [r2, #12] + } + +#if defined(SAI1) + if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) + 8003ccc: 687b ldr r3, [r7, #4] + 8003cce: 6bdb ldr r3, [r3, #60] @ 0x3c + 8003cd0: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 + 8003cd4: d10b bne.n 8003cee <HAL_RCCEx_PeriphCLKConfig+0x2ac> + { + /* PLLSAI1 parameters N & R configuration and clock output (PLLSAI1ClockOut) */ + ret = RCCEx_PLLSAI1_ConfigNR(&(PeriphClkInit->PLLSAI1)); + 8003cd6: 687b ldr r3, [r7, #4] + 8003cd8: 3304 adds r3, #4 + 8003cda: 4618 mov r0, r3 + 8003cdc: f000 f8dd bl 8003e9a <RCCEx_PLLSAI1_ConfigNR> + 8003ce0: 4603 mov r3, r0 + 8003ce2: 77fb strb r3, [r7, #31] + + if (ret != HAL_OK) + 8003ce4: 7ffb ldrb r3, [r7, #31] + 8003ce6: 2b00 cmp r3, #0 + 8003ce8: d001 beq.n 8003cee <HAL_RCCEx_PeriphCLKConfig+0x2ac> + { + /* set overall return value */ + status = ret; + 8003cea: 7ffb ldrb r3, [r7, #31] + 8003cec: 77bb strb r3, [r7, #30] + } +#endif /* SAI1 */ + } + + /*-------------------------- RFWKP clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP) + 8003cee: 687b ldr r3, [r7, #4] + 8003cf0: 681b ldr r3, [r3, #0] + 8003cf2: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 8003cf6: 2b00 cmp r3, #0 + 8003cf8: d004 beq.n 8003d04 <HAL_RCCEx_PeriphCLKConfig+0x2c2> + { + /* Check the parameters */ + assert_param(IS_RCC_RFWKPCLKSOURCE(PeriphClkInit->RFWakeUpClockSelection)); + + /* Configure the RFWKP interface clock source */ + __HAL_RCC_RFWAKEUP_CONFIG(PeriphClkInit->RFWakeUpClockSelection); + 8003cfa: 687b ldr r3, [r7, #4] + 8003cfc: 6c5b ldr r3, [r3, #68] @ 0x44 + 8003cfe: 4618 mov r0, r3 + 8003d00: f7ff fd26 bl 8003750 <LL_RCC_SetRFWKPClockSource> + + } + +#if defined(RCC_SMPS_SUPPORT) + /*-------------------------- SMPS clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS) + 8003d04: 687b ldr r3, [r7, #4] + 8003d06: 681b ldr r3, [r3, #0] + 8003d08: f403 5300 and.w r3, r3, #8192 @ 0x2000 + 8003d0c: 2b00 cmp r3, #0 + 8003d0e: d009 beq.n 8003d24 <HAL_RCCEx_PeriphCLKConfig+0x2e2> + /* Check the parameters */ + assert_param(IS_RCC_SMPSCLKDIV(PeriphClkInit->SmpsDivSelection)); + assert_param(IS_RCC_SMPSCLKSOURCE(PeriphClkInit->SmpsClockSelection)); + + /* Configure the SMPS interface clock division factor */ + __HAL_RCC_SMPS_DIV_CONFIG(PeriphClkInit->SmpsDivSelection); + 8003d10: 687b ldr r3, [r7, #4] + 8003d12: 6cdb ldr r3, [r3, #76] @ 0x4c + 8003d14: 4618 mov r0, r3 + 8003d16: f7ff fd45 bl 80037a4 <LL_RCC_SetSMPSPrescaler> + + /* Configure the SMPS interface clock source */ + __HAL_RCC_SMPS_CONFIG(PeriphClkInit->SmpsClockSelection); + 8003d1a: 687b ldr r3, [r7, #4] + 8003d1c: 6c9b ldr r3, [r3, #72] @ 0x48 + 8003d1e: 4618 mov r0, r3 + 8003d20: f7ff fd2c bl 800377c <LL_RCC_SetSMPSClockSource> + } +#endif /* RCC_SMPS_SUPPORT */ + + return status; + 8003d24: 7fbb ldrb r3, [r7, #30] +} + 8003d26: 4618 mov r0, r3 + 8003d28: 3720 adds r7, #32 + 8003d2a: 46bd mov sp, r7 + 8003d2c: bd80 pop {r7, pc} + +08003d2e <RCCEx_PLLSAI1_ConfigNP>: + * @note PLLSAI1 is temporary disable to apply new parameters + * + * @retval HAL status + */ +static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNP(RCC_PLLSAI1InitTypeDef *PLLSAI1) +{ + 8003d2e: b580 push {r7, lr} + 8003d30: b084 sub sp, #16 + 8003d32: af00 add r7, sp, #0 + 8003d34: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + 8003d36: 2300 movs r3, #0 + 8003d38: 73fb strb r3, [r7, #15] + assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN)); + assert_param(IS_RCC_PLLP_VALUE(PLLSAI1->PLLP)); + assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut)); + + /* Disable the PLLSAI1 */ + __HAL_RCC_PLLSAI1_DISABLE(); + 8003d3a: f7ff fe61 bl 8003a00 <LL_RCC_PLLSAI1_Disable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003d3e: f7fd fe31 bl 80019a4 <HAL_GetTick> + 8003d42: 60b8 str r0, [r7, #8] + + /* Wait till PLLSAI1 is ready to be updated */ + while (LL_RCC_PLLSAI1_IsReady() != 0U) + 8003d44: e009 b.n 8003d5a <RCCEx_PLLSAI1_ConfigNP+0x2c> + { + if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) + 8003d46: f7fd fe2d bl 80019a4 <HAL_GetTick> + 8003d4a: 4602 mov r2, r0 + 8003d4c: 68bb ldr r3, [r7, #8] + 8003d4e: 1ad3 subs r3, r2, r3 + 8003d50: 2b02 cmp r3, #2 + 8003d52: d902 bls.n 8003d5a <RCCEx_PLLSAI1_ConfigNP+0x2c> + { + status = HAL_TIMEOUT; + 8003d54: 2303 movs r3, #3 + 8003d56: 73fb strb r3, [r7, #15] + break; + 8003d58: e004 b.n 8003d64 <RCCEx_PLLSAI1_ConfigNP+0x36> + while (LL_RCC_PLLSAI1_IsReady() != 0U) + 8003d5a: f7ff fe60 bl 8003a1e <LL_RCC_PLLSAI1_IsReady> + 8003d5e: 4603 mov r3, r0 + 8003d60: 2b00 cmp r3, #0 + 8003d62: d1f0 bne.n 8003d46 <RCCEx_PLLSAI1_ConfigNP+0x18> + } + } + + if (status == HAL_OK) + 8003d64: 7bfb ldrb r3, [r7, #15] + 8003d66: 2b00 cmp r3, #0 + 8003d68: d137 bne.n 8003dda <RCCEx_PLLSAI1_ConfigNP+0xac> + { + /* Configure the PLLSAI1 Multiplication factor N */ + __HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN); + 8003d6a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003d6e: 691b ldr r3, [r3, #16] + 8003d70: f423 42fe bic.w r2, r3, #32512 @ 0x7f00 + 8003d74: 687b ldr r3, [r7, #4] + 8003d76: 681b ldr r3, [r3, #0] + 8003d78: 021b lsls r3, r3, #8 + 8003d7a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003d7e: 4313 orrs r3, r2 + 8003d80: 610b str r3, [r1, #16] + + /* Configure the PLLSAI1 Division factor P */ + __HAL_RCC_PLLSAI1_DIVP_CONFIG(PLLSAI1->PLLP); + 8003d82: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003d86: 691b ldr r3, [r3, #16] + 8003d88: f423 1278 bic.w r2, r3, #4063232 @ 0x3e0000 + 8003d8c: 687b ldr r3, [r7, #4] + 8003d8e: 685b ldr r3, [r3, #4] + 8003d90: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003d94: 4313 orrs r3, r2 + 8003d96: 610b str r3, [r1, #16] + + /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ + __HAL_RCC_PLLSAI1_ENABLE(); + 8003d98: f7ff fe23 bl 80039e2 <LL_RCC_PLLSAI1_Enable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003d9c: f7fd fe02 bl 80019a4 <HAL_GetTick> + 8003da0: 60b8 str r0, [r7, #8] + + /* Wait till PLLSAI1 is ready */ + while (LL_RCC_PLLSAI1_IsReady() != 1U) + 8003da2: e009 b.n 8003db8 <RCCEx_PLLSAI1_ConfigNP+0x8a> + { + if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) + 8003da4: f7fd fdfe bl 80019a4 <HAL_GetTick> + 8003da8: 4602 mov r2, r0 + 8003daa: 68bb ldr r3, [r7, #8] + 8003dac: 1ad3 subs r3, r2, r3 + 8003dae: 2b02 cmp r3, #2 + 8003db0: d902 bls.n 8003db8 <RCCEx_PLLSAI1_ConfigNP+0x8a> + { + status = HAL_TIMEOUT; + 8003db2: 2303 movs r3, #3 + 8003db4: 73fb strb r3, [r7, #15] + break; + 8003db6: e004 b.n 8003dc2 <RCCEx_PLLSAI1_ConfigNP+0x94> + while (LL_RCC_PLLSAI1_IsReady() != 1U) + 8003db8: f7ff fe31 bl 8003a1e <LL_RCC_PLLSAI1_IsReady> + 8003dbc: 4603 mov r3, r0 + 8003dbe: 2b01 cmp r3, #1 + 8003dc0: d1f0 bne.n 8003da4 <RCCEx_PLLSAI1_ConfigNP+0x76> + } + } + + if (status == HAL_OK) + 8003dc2: 7bfb ldrb r3, [r7, #15] + 8003dc4: 2b00 cmp r3, #0 + 8003dc6: d108 bne.n 8003dda <RCCEx_PLLSAI1_ConfigNP+0xac> + { + /* Configure the PLLSAI1 Clock output(s) */ + __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut); + 8003dc8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003dcc: 691a ldr r2, [r3, #16] + 8003dce: 687b ldr r3, [r7, #4] + 8003dd0: 691b ldr r3, [r3, #16] + 8003dd2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003dd6: 4313 orrs r3, r2 + 8003dd8: 610b str r3, [r1, #16] + } + } + + return status; + 8003dda: 7bfb ldrb r3, [r7, #15] +} + 8003ddc: 4618 mov r0, r3 + 8003dde: 3710 adds r7, #16 + 8003de0: 46bd mov sp, r7 + 8003de2: bd80 pop {r7, pc} + +08003de4 <RCCEx_PLLSAI1_ConfigNQ>: + * @note PLLSAI1 is temporary disable to apply new parameters + * + * @retval HAL status + */ +static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNQ(RCC_PLLSAI1InitTypeDef *PLLSAI1) +{ + 8003de4: b580 push {r7, lr} + 8003de6: b084 sub sp, #16 + 8003de8: af00 add r7, sp, #0 + 8003dea: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + 8003dec: 2300 movs r3, #0 + 8003dee: 73fb strb r3, [r7, #15] + assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN)); + assert_param(IS_RCC_PLLQ_VALUE(PLLSAI1->PLLQ)); + assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut)); + + /* Disable the PLLSAI1 */ + __HAL_RCC_PLLSAI1_DISABLE(); + 8003df0: f7ff fe06 bl 8003a00 <LL_RCC_PLLSAI1_Disable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003df4: f7fd fdd6 bl 80019a4 <HAL_GetTick> + 8003df8: 60b8 str r0, [r7, #8] + + /* Wait till PLLSAI1 is ready to be updated */ + while (LL_RCC_PLLSAI1_IsReady() != 0U) + 8003dfa: e009 b.n 8003e10 <RCCEx_PLLSAI1_ConfigNQ+0x2c> + { + if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) + 8003dfc: f7fd fdd2 bl 80019a4 <HAL_GetTick> + 8003e00: 4602 mov r2, r0 + 8003e02: 68bb ldr r3, [r7, #8] + 8003e04: 1ad3 subs r3, r2, r3 + 8003e06: 2b02 cmp r3, #2 + 8003e08: d902 bls.n 8003e10 <RCCEx_PLLSAI1_ConfigNQ+0x2c> + { + status = HAL_TIMEOUT; + 8003e0a: 2303 movs r3, #3 + 8003e0c: 73fb strb r3, [r7, #15] + break; + 8003e0e: e004 b.n 8003e1a <RCCEx_PLLSAI1_ConfigNQ+0x36> + while (LL_RCC_PLLSAI1_IsReady() != 0U) + 8003e10: f7ff fe05 bl 8003a1e <LL_RCC_PLLSAI1_IsReady> + 8003e14: 4603 mov r3, r0 + 8003e16: 2b00 cmp r3, #0 + 8003e18: d1f0 bne.n 8003dfc <RCCEx_PLLSAI1_ConfigNQ+0x18> + } + } + + if (status == HAL_OK) + 8003e1a: 7bfb ldrb r3, [r7, #15] + 8003e1c: 2b00 cmp r3, #0 + 8003e1e: d137 bne.n 8003e90 <RCCEx_PLLSAI1_ConfigNQ+0xac> + { + /* Configure the PLLSAI1 Multiplication factor N */ + __HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN); + 8003e20: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003e24: 691b ldr r3, [r3, #16] + 8003e26: f423 42fe bic.w r2, r3, #32512 @ 0x7f00 + 8003e2a: 687b ldr r3, [r7, #4] + 8003e2c: 681b ldr r3, [r3, #0] + 8003e2e: 021b lsls r3, r3, #8 + 8003e30: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003e34: 4313 orrs r3, r2 + 8003e36: 610b str r3, [r1, #16] + /* Configure the PLLSAI1 Division factor Q */ + __HAL_RCC_PLLSAI1_DIVQ_CONFIG(PLLSAI1->PLLQ); + 8003e38: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003e3c: 691b ldr r3, [r3, #16] + 8003e3e: f023 6260 bic.w r2, r3, #234881024 @ 0xe000000 + 8003e42: 687b ldr r3, [r7, #4] + 8003e44: 689b ldr r3, [r3, #8] + 8003e46: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003e4a: 4313 orrs r3, r2 + 8003e4c: 610b str r3, [r1, #16] + + /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ + __HAL_RCC_PLLSAI1_ENABLE(); + 8003e4e: f7ff fdc8 bl 80039e2 <LL_RCC_PLLSAI1_Enable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003e52: f7fd fda7 bl 80019a4 <HAL_GetTick> + 8003e56: 60b8 str r0, [r7, #8] + + /* Wait till PLLSAI1 is ready */ + while (LL_RCC_PLLSAI1_IsReady() != 1U) + 8003e58: e009 b.n 8003e6e <RCCEx_PLLSAI1_ConfigNQ+0x8a> + { + if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) + 8003e5a: f7fd fda3 bl 80019a4 <HAL_GetTick> + 8003e5e: 4602 mov r2, r0 + 8003e60: 68bb ldr r3, [r7, #8] + 8003e62: 1ad3 subs r3, r2, r3 + 8003e64: 2b02 cmp r3, #2 + 8003e66: d902 bls.n 8003e6e <RCCEx_PLLSAI1_ConfigNQ+0x8a> + { + status = HAL_TIMEOUT; + 8003e68: 2303 movs r3, #3 + 8003e6a: 73fb strb r3, [r7, #15] + break; + 8003e6c: e004 b.n 8003e78 <RCCEx_PLLSAI1_ConfigNQ+0x94> + while (LL_RCC_PLLSAI1_IsReady() != 1U) + 8003e6e: f7ff fdd6 bl 8003a1e <LL_RCC_PLLSAI1_IsReady> + 8003e72: 4603 mov r3, r0 + 8003e74: 2b01 cmp r3, #1 + 8003e76: d1f0 bne.n 8003e5a <RCCEx_PLLSAI1_ConfigNQ+0x76> + } + } + + if (status == HAL_OK) + 8003e78: 7bfb ldrb r3, [r7, #15] + 8003e7a: 2b00 cmp r3, #0 + 8003e7c: d108 bne.n 8003e90 <RCCEx_PLLSAI1_ConfigNQ+0xac> + { + /* Configure the PLLSAI1 Clock output(s) */ + __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut); + 8003e7e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003e82: 691a ldr r2, [r3, #16] + 8003e84: 687b ldr r3, [r7, #4] + 8003e86: 691b ldr r3, [r3, #16] + 8003e88: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003e8c: 4313 orrs r3, r2 + 8003e8e: 610b str r3, [r1, #16] + } + } + + return status; + 8003e90: 7bfb ldrb r3, [r7, #15] +} + 8003e92: 4618 mov r0, r3 + 8003e94: 3710 adds r7, #16 + 8003e96: 46bd mov sp, r7 + 8003e98: bd80 pop {r7, pc} + +08003e9a <RCCEx_PLLSAI1_ConfigNR>: + * @note PLLSAI1 is temporary disable to apply new parameters + * + * @retval HAL status + */ +static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNR(RCC_PLLSAI1InitTypeDef *PLLSAI1) +{ + 8003e9a: b580 push {r7, lr} + 8003e9c: b084 sub sp, #16 + 8003e9e: af00 add r7, sp, #0 + 8003ea0: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + 8003ea2: 2300 movs r3, #0 + 8003ea4: 73fb strb r3, [r7, #15] + assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN)); + assert_param(IS_RCC_PLLR_VALUE(PLLSAI1->PLLR)); + assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut)); + + /* Disable the PLLSAI1 */ + __HAL_RCC_PLLSAI1_DISABLE(); + 8003ea6: f7ff fdab bl 8003a00 <LL_RCC_PLLSAI1_Disable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003eaa: f7fd fd7b bl 80019a4 <HAL_GetTick> + 8003eae: 60b8 str r0, [r7, #8] + + /* Wait till PLLSAI1 is ready to be updated */ + while (LL_RCC_PLLSAI1_IsReady() != 0U) + 8003eb0: e009 b.n 8003ec6 <RCCEx_PLLSAI1_ConfigNR+0x2c> + { + if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) + 8003eb2: f7fd fd77 bl 80019a4 <HAL_GetTick> + 8003eb6: 4602 mov r2, r0 + 8003eb8: 68bb ldr r3, [r7, #8] + 8003eba: 1ad3 subs r3, r2, r3 + 8003ebc: 2b02 cmp r3, #2 + 8003ebe: d902 bls.n 8003ec6 <RCCEx_PLLSAI1_ConfigNR+0x2c> + { + status = HAL_TIMEOUT; + 8003ec0: 2303 movs r3, #3 + 8003ec2: 73fb strb r3, [r7, #15] + break; + 8003ec4: e004 b.n 8003ed0 <RCCEx_PLLSAI1_ConfigNR+0x36> + while (LL_RCC_PLLSAI1_IsReady() != 0U) + 8003ec6: f7ff fdaa bl 8003a1e <LL_RCC_PLLSAI1_IsReady> + 8003eca: 4603 mov r3, r0 + 8003ecc: 2b00 cmp r3, #0 + 8003ece: d1f0 bne.n 8003eb2 <RCCEx_PLLSAI1_ConfigNR+0x18> + } + } + + if (status == HAL_OK) + 8003ed0: 7bfb ldrb r3, [r7, #15] + 8003ed2: 2b00 cmp r3, #0 + 8003ed4: d137 bne.n 8003f46 <RCCEx_PLLSAI1_ConfigNR+0xac> + { + /* Configure the PLLSAI1 Multiplication factor N */ + __HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN); + 8003ed6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003eda: 691b ldr r3, [r3, #16] + 8003edc: f423 42fe bic.w r2, r3, #32512 @ 0x7f00 + 8003ee0: 687b ldr r3, [r7, #4] + 8003ee2: 681b ldr r3, [r3, #0] + 8003ee4: 021b lsls r3, r3, #8 + 8003ee6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003eea: 4313 orrs r3, r2 + 8003eec: 610b str r3, [r1, #16] + /* Configure the PLLSAI1 Division factor R */ + __HAL_RCC_PLLSAI1_DIVR_CONFIG(PLLSAI1->PLLR); + 8003eee: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003ef2: 691b ldr r3, [r3, #16] + 8003ef4: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 + 8003ef8: 687b ldr r3, [r7, #4] + 8003efa: 68db ldr r3, [r3, #12] + 8003efc: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003f00: 4313 orrs r3, r2 + 8003f02: 610b str r3, [r1, #16] + + /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ + __HAL_RCC_PLLSAI1_ENABLE(); + 8003f04: f7ff fd6d bl 80039e2 <LL_RCC_PLLSAI1_Enable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003f08: f7fd fd4c bl 80019a4 <HAL_GetTick> + 8003f0c: 60b8 str r0, [r7, #8] + + /* Wait till PLLSAI1 is ready */ + while (LL_RCC_PLLSAI1_IsReady() != 1U) + 8003f0e: e009 b.n 8003f24 <RCCEx_PLLSAI1_ConfigNR+0x8a> + { + if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) + 8003f10: f7fd fd48 bl 80019a4 <HAL_GetTick> + 8003f14: 4602 mov r2, r0 + 8003f16: 68bb ldr r3, [r7, #8] + 8003f18: 1ad3 subs r3, r2, r3 + 8003f1a: 2b02 cmp r3, #2 + 8003f1c: d902 bls.n 8003f24 <RCCEx_PLLSAI1_ConfigNR+0x8a> + { + status = HAL_TIMEOUT; + 8003f1e: 2303 movs r3, #3 + 8003f20: 73fb strb r3, [r7, #15] + break; + 8003f22: e004 b.n 8003f2e <RCCEx_PLLSAI1_ConfigNR+0x94> + while (LL_RCC_PLLSAI1_IsReady() != 1U) + 8003f24: f7ff fd7b bl 8003a1e <LL_RCC_PLLSAI1_IsReady> + 8003f28: 4603 mov r3, r0 + 8003f2a: 2b01 cmp r3, #1 + 8003f2c: d1f0 bne.n 8003f10 <RCCEx_PLLSAI1_ConfigNR+0x76> + } + } + + if (status == HAL_OK) + 8003f2e: 7bfb ldrb r3, [r7, #15] + 8003f30: 2b00 cmp r3, #0 + 8003f32: d108 bne.n 8003f46 <RCCEx_PLLSAI1_ConfigNR+0xac> + { + /* Configure the PLLSAI1 Clock output(s) */ + __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut); + 8003f34: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003f38: 691a ldr r2, [r3, #16] + 8003f3a: 687b ldr r3, [r7, #4] + 8003f3c: 691b ldr r3, [r3, #16] + 8003f3e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003f42: 4313 orrs r3, r2 + 8003f44: 610b str r3, [r1, #16] + } + } + + return status; + 8003f46: 7bfb ldrb r3, [r7, #15] +} + 8003f48: 4618 mov r0, r3 + 8003f4a: 3710 adds r7, #16 + 8003f4c: 46bd mov sp, r7 + 8003f4e: bd80 pop {r7, pc} + +08003f50 <HAL_RTC_Init>: + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) +{ + 8003f50: b580 push {r7, lr} + 8003f52: b084 sub sp, #16 + 8003f54: af00 add r7, sp, #0 + 8003f56: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status; + + /* Check RTC handler validity */ + if (hrtc == NULL) + 8003f58: 687b ldr r3, [r7, #4] + 8003f5a: 2b00 cmp r3, #0 + 8003f5c: d101 bne.n 8003f62 <HAL_RTC_Init+0x12> + { + return HAL_ERROR; + 8003f5e: 2301 movs r3, #1 + 8003f60: e07a b.n 8004058 <HAL_RTC_Init+0x108> + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + } +#else /* USE_HAL_RTC_REGISTER_CALLBACKS */ + if (hrtc->State == HAL_RTC_STATE_RESET) + 8003f62: 687b ldr r3, [r7, #4] + 8003f64: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 + 8003f68: b2db uxtb r3, r3 + 8003f6a: 2b00 cmp r3, #0 + 8003f6c: d106 bne.n 8003f7c <HAL_RTC_Init+0x2c> + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + 8003f6e: 687b ldr r3, [r7, #4] + 8003f70: 2200 movs r2, #0 + 8003f72: f883 2020 strb.w r2, [r3, #32] + + /* Initialize RTC MSP */ + HAL_RTC_MspInit(hrtc); + 8003f76: 6878 ldr r0, [r7, #4] + 8003f78: f7fd fbac bl 80016d4 <HAL_RTC_MspInit> + } +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + 8003f7c: 687b ldr r3, [r7, #4] + 8003f7e: 2202 movs r2, #2 + 8003f80: f883 2021 strb.w r2, [r3, #33] @ 0x21 + + /* Check whether the calendar needs to be initialized */ + if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) + 8003f84: 687b ldr r3, [r7, #4] + 8003f86: 681b ldr r3, [r3, #0] + 8003f88: 68db ldr r3, [r3, #12] + 8003f8a: f003 0310 and.w r3, r3, #16 + 8003f8e: 2b10 cmp r3, #16 + 8003f90: d058 beq.n 8004044 <HAL_RTC_Init+0xf4> + { + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8003f92: 687b ldr r3, [r7, #4] + 8003f94: 681b ldr r3, [r3, #0] + 8003f96: 22ca movs r2, #202 @ 0xca + 8003f98: 625a str r2, [r3, #36] @ 0x24 + 8003f9a: 687b ldr r3, [r7, #4] + 8003f9c: 681b ldr r3, [r3, #0] + 8003f9e: 2253 movs r2, #83 @ 0x53 + 8003fa0: 625a str r2, [r3, #36] @ 0x24 + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + 8003fa2: 6878 ldr r0, [r7, #4] + 8003fa4: f000 f9aa bl 80042fc <RTC_EnterInitMode> + 8003fa8: 4603 mov r3, r0 + 8003faa: 73fb strb r3, [r7, #15] + + if (status == HAL_OK) + 8003fac: 7bfb ldrb r3, [r7, #15] + 8003fae: 2b00 cmp r3, #0 + 8003fb0: d12c bne.n 800400c <HAL_RTC_Init+0xbc> + { + /* Clear RTC_CR FMT, OSEL and POL Bits */ + hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); + 8003fb2: 687b ldr r3, [r7, #4] + 8003fb4: 681b ldr r3, [r3, #0] + 8003fb6: 689b ldr r3, [r3, #8] + 8003fb8: 687a ldr r2, [r7, #4] + 8003fba: 6812 ldr r2, [r2, #0] + 8003fbc: f423 03e0 bic.w r3, r3, #7340032 @ 0x700000 + 8003fc0: f023 0340 bic.w r3, r3, #64 @ 0x40 + 8003fc4: 6093 str r3, [r2, #8] + /* Set RTC_CR register */ + hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); + 8003fc6: 687b ldr r3, [r7, #4] + 8003fc8: 681b ldr r3, [r3, #0] + 8003fca: 6899 ldr r1, [r3, #8] + 8003fcc: 687b ldr r3, [r7, #4] + 8003fce: 685a ldr r2, [r3, #4] + 8003fd0: 687b ldr r3, [r7, #4] + 8003fd2: 691b ldr r3, [r3, #16] + 8003fd4: 431a orrs r2, r3 + 8003fd6: 687b ldr r3, [r7, #4] + 8003fd8: 699b ldr r3, [r3, #24] + 8003fda: 431a orrs r2, r3 + 8003fdc: 687b ldr r3, [r7, #4] + 8003fde: 681b ldr r3, [r3, #0] + 8003fe0: 430a orrs r2, r1 + 8003fe2: 609a str r2, [r3, #8] + + /* Configure the RTC PRER */ + hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); + 8003fe4: 687b ldr r3, [r7, #4] + 8003fe6: 681b ldr r3, [r3, #0] + 8003fe8: 687a ldr r2, [r7, #4] + 8003fea: 68d2 ldr r2, [r2, #12] + 8003fec: 611a str r2, [r3, #16] + hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos); + 8003fee: 687b ldr r3, [r7, #4] + 8003ff0: 681b ldr r3, [r3, #0] + 8003ff2: 6919 ldr r1, [r3, #16] + 8003ff4: 687b ldr r3, [r7, #4] + 8003ff6: 689b ldr r3, [r3, #8] + 8003ff8: 041a lsls r2, r3, #16 + 8003ffa: 687b ldr r3, [r7, #4] + 8003ffc: 681b ldr r3, [r3, #0] + 8003ffe: 430a orrs r2, r1 + 8004000: 611a str r2, [r3, #16] + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + 8004002: 6878 ldr r0, [r7, #4] + 8004004: f000 f9b2 bl 800436c <RTC_ExitInitMode> + 8004008: 4603 mov r3, r0 + 800400a: 73fb strb r3, [r7, #15] + } + + if (status == HAL_OK) + 800400c: 7bfb ldrb r3, [r7, #15] + 800400e: 2b00 cmp r3, #0 + 8004010: d113 bne.n 800403a <HAL_RTC_Init+0xea> + { +#if defined(RTC_OR_ALARMOUTTYPE) + hrtc->Instance->OR &= (uint32_t)~(RTC_OUTPUT_TYPE_PUSHPULL | RTC_OUTPUT_REMAP_POS1); + 8004012: 687b ldr r3, [r7, #4] + 8004014: 681b ldr r3, [r3, #0] + 8004016: 6cda ldr r2, [r3, #76] @ 0x4c + 8004018: 687b ldr r3, [r7, #4] + 800401a: 681b ldr r3, [r3, #0] + 800401c: f022 0203 bic.w r2, r2, #3 + 8004020: 64da str r2, [r3, #76] @ 0x4c + hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + 8004022: 687b ldr r3, [r7, #4] + 8004024: 681b ldr r3, [r3, #0] + 8004026: 6cd9 ldr r1, [r3, #76] @ 0x4c + 8004028: 687b ldr r3, [r7, #4] + 800402a: 69da ldr r2, [r3, #28] + 800402c: 687b ldr r3, [r7, #4] + 800402e: 695b ldr r3, [r3, #20] + 8004030: 431a orrs r2, r3 + 8004032: 687b ldr r3, [r7, #4] + 8004034: 681b ldr r3, [r3, #0] + 8004036: 430a orrs r2, r1 + 8004038: 64da str r2, [r3, #76] @ 0x4c + hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutRemap); +#endif /* RTC_OR_ALARMOUTTYPE */ + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 800403a: 687b ldr r3, [r7, #4] + 800403c: 681b ldr r3, [r3, #0] + 800403e: 22ff movs r2, #255 @ 0xff + 8004040: 625a str r2, [r3, #36] @ 0x24 + 8004042: e001 b.n 8004048 <HAL_RTC_Init+0xf8> + } + else + { + /* The calendar is already initialized */ + status = HAL_OK; + 8004044: 2300 movs r3, #0 + 8004046: 73fb strb r3, [r7, #15] + } + + if (status == HAL_OK) + 8004048: 7bfb ldrb r3, [r7, #15] + 800404a: 2b00 cmp r3, #0 + 800404c: d103 bne.n 8004056 <HAL_RTC_Init+0x106> + { + hrtc->State = HAL_RTC_STATE_READY; + 800404e: 687b ldr r3, [r7, #4] + 8004050: 2201 movs r2, #1 + 8004052: f883 2021 strb.w r2, [r3, #33] @ 0x21 + } + + return status; + 8004056: 7bfb ldrb r3, [r7, #15] +} + 8004058: 4618 mov r0, r3 + 800405a: 3710 adds r7, #16 + 800405c: 46bd mov sp, r7 + 800405e: bd80 pop {r7, pc} + +08004060 <HAL_RTC_SetTime>: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + 8004060: b590 push {r4, r7, lr} + 8004062: b087 sub sp, #28 + 8004064: af00 add r7, sp, #0 + 8004066: 60f8 str r0, [r7, #12] + 8004068: 60b9 str r1, [r7, #8] + 800406a: 607a str r2, [r7, #4] + uint32_t tmpreg = 0U; + 800406c: 2300 movs r3, #0 + 800406e: 617b str r3, [r7, #20] + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); + assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + 8004070: 68fb ldr r3, [r7, #12] + 8004072: f893 3020 ldrb.w r3, [r3, #32] + 8004076: 2b01 cmp r3, #1 + 8004078: d101 bne.n 800407e <HAL_RTC_SetTime+0x1e> + 800407a: 2302 movs r3, #2 + 800407c: e08b b.n 8004196 <HAL_RTC_SetTime+0x136> + 800407e: 68fb ldr r3, [r7, #12] + 8004080: 2201 movs r2, #1 + 8004082: f883 2020 strb.w r2, [r3, #32] + + hrtc->State = HAL_RTC_STATE_BUSY; + 8004086: 68fb ldr r3, [r7, #12] + 8004088: 2202 movs r2, #2 + 800408a: f883 2021 strb.w r2, [r3, #33] @ 0x21 + + if (Format == RTC_FORMAT_BIN) + 800408e: 687b ldr r3, [r7, #4] + 8004090: 2b00 cmp r3, #0 + 8004092: d126 bne.n 80040e2 <HAL_RTC_SetTime+0x82> + { + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) + 8004094: 68fb ldr r3, [r7, #12] + 8004096: 681b ldr r3, [r3, #0] + 8004098: 689b ldr r3, [r3, #8] + 800409a: f003 0340 and.w r3, r3, #64 @ 0x40 + 800409e: 2b00 cmp r3, #0 + 80040a0: d102 bne.n 80040a8 <HAL_RTC_SetTime+0x48> + assert_param(IS_RTC_HOUR12(sTime->Hours)); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00U; + 80040a2: 68bb ldr r3, [r7, #8] + 80040a4: 2200 movs r2, #0 + 80040a6: 70da strb r2, [r3, #3] + assert_param(IS_RTC_HOUR24(sTime->Hours)); + } + assert_param(IS_RTC_MINUTES(sTime->Minutes)); + assert_param(IS_RTC_SECONDS(sTime->Seconds)); + + tmpreg = (uint32_t)(( (uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ + 80040a8: 68bb ldr r3, [r7, #8] + 80040aa: 781b ldrb r3, [r3, #0] + 80040ac: 4618 mov r0, r3 + 80040ae: f000 f983 bl 80043b8 <RTC_ByteToBcd2> + 80040b2: 4603 mov r3, r0 + 80040b4: 041c lsls r4, r3, #16 + ( (uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + 80040b6: 68bb ldr r3, [r7, #8] + 80040b8: 785b ldrb r3, [r3, #1] + 80040ba: 4618 mov r0, r3 + 80040bc: f000 f97c bl 80043b8 <RTC_ByteToBcd2> + 80040c0: 4603 mov r3, r0 + 80040c2: 021b lsls r3, r3, #8 + tmpreg = (uint32_t)(( (uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ + 80040c4: 431c orrs r4, r3 + ( (uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ + 80040c6: 68bb ldr r3, [r7, #8] + 80040c8: 789b ldrb r3, [r3, #2] + 80040ca: 4618 mov r0, r3 + 80040cc: f000 f974 bl 80043b8 <RTC_ByteToBcd2> + 80040d0: 4603 mov r3, r0 + ( (uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + 80040d2: ea44 0203 orr.w r2, r4, r3 + (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos)); + 80040d6: 68bb ldr r3, [r7, #8] + 80040d8: 78db ldrb r3, [r3, #3] + 80040da: 059b lsls r3, r3, #22 + tmpreg = (uint32_t)(( (uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ + 80040dc: 4313 orrs r3, r2 + 80040de: 617b str r3, [r7, #20] + 80040e0: e018 b.n 8004114 <HAL_RTC_SetTime+0xb4> + } + else + { + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) + 80040e2: 68fb ldr r3, [r7, #12] + 80040e4: 681b ldr r3, [r3, #0] + 80040e6: 689b ldr r3, [r3, #8] + 80040e8: f003 0340 and.w r3, r3, #64 @ 0x40 + 80040ec: 2b00 cmp r3, #0 + 80040ee: d102 bne.n 80040f6 <HAL_RTC_SetTime+0x96> + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours))); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00U; + 80040f0: 68bb ldr r3, [r7, #8] + 80040f2: 2200 movs r2, #0 + 80040f4: 70da strb r2, [r3, #3] + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); + tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ + 80040f6: 68bb ldr r3, [r7, #8] + 80040f8: 781b ldrb r3, [r3, #0] + 80040fa: 041a lsls r2, r3, #16 + ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + 80040fc: 68bb ldr r3, [r7, #8] + 80040fe: 785b ldrb r3, [r3, #1] + 8004100: 021b lsls r3, r3, #8 + tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ + 8004102: 4313 orrs r3, r2 + ((uint32_t) sTime->Seconds) | \ + 8004104: 68ba ldr r2, [r7, #8] + 8004106: 7892 ldrb r2, [r2, #2] + ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + 8004108: 431a orrs r2, r3 + ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos)); + 800410a: 68bb ldr r3, [r7, #8] + 800410c: 78db ldrb r3, [r3, #3] + 800410e: 059b lsls r3, r3, #22 + tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ + 8004110: 4313 orrs r3, r2 + 8004112: 617b str r3, [r7, #20] + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8004114: 68fb ldr r3, [r7, #12] + 8004116: 681b ldr r3, [r3, #0] + 8004118: 22ca movs r2, #202 @ 0xca + 800411a: 625a str r2, [r3, #36] @ 0x24 + 800411c: 68fb ldr r3, [r7, #12] + 800411e: 681b ldr r3, [r3, #0] + 8004120: 2253 movs r2, #83 @ 0x53 + 8004122: 625a str r2, [r3, #36] @ 0x24 + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + 8004124: 68f8 ldr r0, [r7, #12] + 8004126: f000 f8e9 bl 80042fc <RTC_EnterInitMode> + 800412a: 4603 mov r3, r0 + 800412c: 74fb strb r3, [r7, #19] + + if (status == HAL_OK) + 800412e: 7cfb ldrb r3, [r7, #19] + 8004130: 2b00 cmp r3, #0 + 8004132: d120 bne.n 8004176 <HAL_RTC_SetTime+0x116> + { + /* Set the RTC_TR register */ + hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); + 8004134: 68fb ldr r3, [r7, #12] + 8004136: 681a ldr r2, [r3, #0] + 8004138: 697b ldr r3, [r7, #20] + 800413a: f003 337f and.w r3, r3, #2139062143 @ 0x7f7f7f7f + 800413e: f023 43fe bic.w r3, r3, #2130706432 @ 0x7f000000 + 8004142: 6013 str r3, [r2, #0] + + /* Clear the bits to be configured (Deprecated. Use HAL_RTC_DST_xxx functions instead) */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP; + 8004144: 68fb ldr r3, [r7, #12] + 8004146: 681b ldr r3, [r3, #0] + 8004148: 689a ldr r2, [r3, #8] + 800414a: 68fb ldr r3, [r7, #12] + 800414c: 681b ldr r3, [r3, #0] + 800414e: f422 2280 bic.w r2, r2, #262144 @ 0x40000 + 8004152: 609a str r2, [r3, #8] + + /* Configure the RTC_CR register (Deprecated. Use HAL_RTC_DST_xxx functions instead) */ + hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); + 8004154: 68fb ldr r3, [r7, #12] + 8004156: 681b ldr r3, [r3, #0] + 8004158: 6899 ldr r1, [r3, #8] + 800415a: 68bb ldr r3, [r7, #8] + 800415c: 68da ldr r2, [r3, #12] + 800415e: 68bb ldr r3, [r7, #8] + 8004160: 691b ldr r3, [r3, #16] + 8004162: 431a orrs r2, r3 + 8004164: 68fb ldr r3, [r7, #12] + 8004166: 681b ldr r3, [r3, #0] + 8004168: 430a orrs r2, r1 + 800416a: 609a str r2, [r3, #8] + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + 800416c: 68f8 ldr r0, [r7, #12] + 800416e: f000 f8fd bl 800436c <RTC_ExitInitMode> + 8004172: 4603 mov r3, r0 + 8004174: 74fb strb r3, [r7, #19] + } + + if (status == HAL_OK) + 8004176: 7cfb ldrb r3, [r7, #19] + 8004178: 2b00 cmp r3, #0 + 800417a: d103 bne.n 8004184 <HAL_RTC_SetTime+0x124> + { + hrtc->State = HAL_RTC_STATE_READY; + 800417c: 68fb ldr r3, [r7, #12] + 800417e: 2201 movs r2, #1 + 8004180: f883 2021 strb.w r2, [r3, #33] @ 0x21 + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8004184: 68fb ldr r3, [r7, #12] + 8004186: 681b ldr r3, [r3, #0] + 8004188: 22ff movs r2, #255 @ 0xff + 800418a: 625a str r2, [r3, #36] @ 0x24 + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 800418c: 68fb ldr r3, [r7, #12] + 800418e: 2200 movs r2, #0 + 8004190: f883 2020 strb.w r2, [r3, #32] + + return status; + 8004194: 7cfb ldrb r3, [r7, #19] +} + 8004196: 4618 mov r0, r3 + 8004198: 371c adds r7, #28 + 800419a: 46bd mov sp, r7 + 800419c: bd90 pop {r4, r7, pc} + +0800419e <HAL_RTC_SetDate>: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + 800419e: b590 push {r4, r7, lr} + 80041a0: b087 sub sp, #28 + 80041a2: af00 add r7, sp, #0 + 80041a4: 60f8 str r0, [r7, #12] + 80041a6: 60b9 str r1, [r7, #8] + 80041a8: 607a str r2, [r7, #4] + uint32_t datetmpreg = 0U; + 80041aa: 2300 movs r3, #0 + 80041ac: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + 80041ae: 68fb ldr r3, [r7, #12] + 80041b0: f893 3020 ldrb.w r3, [r3, #32] + 80041b4: 2b01 cmp r3, #1 + 80041b6: d101 bne.n 80041bc <HAL_RTC_SetDate+0x1e> + 80041b8: 2302 movs r3, #2 + 80041ba: e075 b.n 80042a8 <HAL_RTC_SetDate+0x10a> + 80041bc: 68fb ldr r3, [r7, #12] + 80041be: 2201 movs r2, #1 + 80041c0: f883 2020 strb.w r2, [r3, #32] + + hrtc->State = HAL_RTC_STATE_BUSY; + 80041c4: 68fb ldr r3, [r7, #12] + 80041c6: 2202 movs r2, #2 + 80041c8: f883 2021 strb.w r2, [r3, #33] @ 0x21 + + if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) + 80041cc: 687b ldr r3, [r7, #4] + 80041ce: 2b00 cmp r3, #0 + 80041d0: d10e bne.n 80041f0 <HAL_RTC_SetDate+0x52> + 80041d2: 68bb ldr r3, [r7, #8] + 80041d4: 785b ldrb r3, [r3, #1] + 80041d6: f003 0310 and.w r3, r3, #16 + 80041da: 2b00 cmp r3, #0 + 80041dc: d008 beq.n 80041f0 <HAL_RTC_SetDate+0x52> + { + sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); + 80041de: 68bb ldr r3, [r7, #8] + 80041e0: 785b ldrb r3, [r3, #1] + 80041e2: f023 0310 bic.w r3, r3, #16 + 80041e6: b2db uxtb r3, r3 + 80041e8: 330a adds r3, #10 + 80041ea: b2da uxtb r2, r3 + 80041ec: 68bb ldr r3, [r7, #8] + 80041ee: 705a strb r2, [r3, #1] + } + + assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); + + if (Format == RTC_FORMAT_BIN) + 80041f0: 687b ldr r3, [r7, #4] + 80041f2: 2b00 cmp r3, #0 + 80041f4: d11c bne.n 8004230 <HAL_RTC_SetDate+0x92> + { + assert_param(IS_RTC_YEAR(sDate->Year)); + assert_param(IS_RTC_MONTH(sDate->Month)); + assert_param(IS_RTC_DATE(sDate->Date)); + + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ + 80041f6: 68bb ldr r3, [r7, #8] + 80041f8: 78db ldrb r3, [r3, #3] + 80041fa: 4618 mov r0, r3 + 80041fc: f000 f8dc bl 80043b8 <RTC_ByteToBcd2> + 8004200: 4603 mov r3, r0 + 8004202: 041c lsls r4, r3, #16 + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \ + 8004204: 68bb ldr r3, [r7, #8] + 8004206: 785b ldrb r3, [r3, #1] + 8004208: 4618 mov r0, r3 + 800420a: f000 f8d5 bl 80043b8 <RTC_ByteToBcd2> + 800420e: 4603 mov r3, r0 + 8004210: 021b lsls r3, r3, #8 + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ + 8004212: 431c orrs r4, r3 + ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ + 8004214: 68bb ldr r3, [r7, #8] + 8004216: 789b ldrb r3, [r3, #2] + 8004218: 4618 mov r0, r3 + 800421a: f000 f8cd bl 80043b8 <RTC_ByteToBcd2> + 800421e: 4603 mov r3, r0 + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \ + 8004220: ea44 0203 orr.w r2, r4, r3 + ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos)); + 8004224: 68bb ldr r3, [r7, #8] + 8004226: 781b ldrb r3, [r3, #0] + 8004228: 035b lsls r3, r3, #13 + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ + 800422a: 4313 orrs r3, r2 + 800422c: 617b str r3, [r7, #20] + 800422e: e00e b.n 800424e <HAL_RTC_SetDate+0xb0> + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); + assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); + assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); + + datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ + 8004230: 68bb ldr r3, [r7, #8] + 8004232: 78db ldrb r3, [r3, #3] + 8004234: 041a lsls r2, r3, #16 + (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \ + 8004236: 68bb ldr r3, [r7, #8] + 8004238: 785b ldrb r3, [r3, #1] + 800423a: 021b lsls r3, r3, #8 + datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ + 800423c: 4313 orrs r3, r2 + ((uint32_t) sDate->Date) | \ + 800423e: 68ba ldr r2, [r7, #8] + 8004240: 7892 ldrb r2, [r2, #2] + (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \ + 8004242: 431a orrs r2, r3 + (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos)); + 8004244: 68bb ldr r3, [r7, #8] + 8004246: 781b ldrb r3, [r3, #0] + 8004248: 035b lsls r3, r3, #13 + datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ + 800424a: 4313 orrs r3, r2 + 800424c: 617b str r3, [r7, #20] + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 800424e: 68fb ldr r3, [r7, #12] + 8004250: 681b ldr r3, [r3, #0] + 8004252: 22ca movs r2, #202 @ 0xca + 8004254: 625a str r2, [r3, #36] @ 0x24 + 8004256: 68fb ldr r3, [r7, #12] + 8004258: 681b ldr r3, [r3, #0] + 800425a: 2253 movs r2, #83 @ 0x53 + 800425c: 625a str r2, [r3, #36] @ 0x24 + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + 800425e: 68f8 ldr r0, [r7, #12] + 8004260: f000 f84c bl 80042fc <RTC_EnterInitMode> + 8004264: 4603 mov r3, r0 + 8004266: 74fb strb r3, [r7, #19] + + if (status == HAL_OK) + 8004268: 7cfb ldrb r3, [r7, #19] + 800426a: 2b00 cmp r3, #0 + 800426c: d10c bne.n 8004288 <HAL_RTC_SetDate+0xea> + { + /* Set the RTC_DR register */ + hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); + 800426e: 68fb ldr r3, [r7, #12] + 8004270: 681a ldr r2, [r3, #0] + 8004272: 697b ldr r3, [r7, #20] + 8004274: f023 437f bic.w r3, r3, #4278190080 @ 0xff000000 + 8004278: f023 03c0 bic.w r3, r3, #192 @ 0xc0 + 800427c: 6053 str r3, [r2, #4] + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + 800427e: 68f8 ldr r0, [r7, #12] + 8004280: f000 f874 bl 800436c <RTC_ExitInitMode> + 8004284: 4603 mov r3, r0 + 8004286: 74fb strb r3, [r7, #19] + } + + if (status == HAL_OK) + 8004288: 7cfb ldrb r3, [r7, #19] + 800428a: 2b00 cmp r3, #0 + 800428c: d103 bne.n 8004296 <HAL_RTC_SetDate+0xf8> + { + hrtc->State = HAL_RTC_STATE_READY; + 800428e: 68fb ldr r3, [r7, #12] + 8004290: 2201 movs r2, #1 + 8004292: f883 2021 strb.w r2, [r3, #33] @ 0x21 + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8004296: 68fb ldr r3, [r7, #12] + 8004298: 681b ldr r3, [r3, #0] + 800429a: 22ff movs r2, #255 @ 0xff + 800429c: 625a str r2, [r3, #36] @ 0x24 + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 800429e: 68fb ldr r3, [r7, #12] + 80042a0: 2200 movs r2, #0 + 80042a2: f883 2020 strb.w r2, [r3, #32] + + return status; + 80042a6: 7cfb ldrb r3, [r7, #19] +} + 80042a8: 4618 mov r0, r3 + 80042aa: 371c adds r7, #28 + 80042ac: 46bd mov sp, r7 + 80042ae: bd90 pop {r4, r7, pc} + +080042b0 <HAL_RTC_WaitForSynchro>: + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) +{ + 80042b0: b580 push {r7, lr} + 80042b2: b084 sub sp, #16 + 80042b4: af00 add r7, sp, #0 + 80042b6: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 80042b8: 2300 movs r3, #0 + 80042ba: 60fb str r3, [r7, #12] + + /* Clear RSF flag, keep reserved bits at reset values (setting other flags has no effect) */ + hrtc->Instance->ISR = ((uint32_t)(RTC_RSF_MASK & RTC_ISR_RESERVED_MASK)); + 80042bc: 687b ldr r3, [r7, #4] + 80042be: 681b ldr r3, [r3, #0] + 80042c0: 4a0d ldr r2, [pc, #52] @ (80042f8 <HAL_RTC_WaitForSynchro+0x48>) + 80042c2: 60da str r2, [r3, #12] + + /* Get tick */ + tickstart = HAL_GetTick(); + 80042c4: f7fd fb6e bl 80019a4 <HAL_GetTick> + 80042c8: 60f8 str r0, [r7, #12] + + /* Wait the registers to be synchronised */ + while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U) + 80042ca: e009 b.n 80042e0 <HAL_RTC_WaitForSynchro+0x30> + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 80042cc: f7fd fb6a bl 80019a4 <HAL_GetTick> + 80042d0: 4602 mov r2, r0 + 80042d2: 68fb ldr r3, [r7, #12] + 80042d4: 1ad3 subs r3, r2, r3 + 80042d6: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 80042da: d901 bls.n 80042e0 <HAL_RTC_WaitForSynchro+0x30> + { + return HAL_TIMEOUT; + 80042dc: 2303 movs r3, #3 + 80042de: e007 b.n 80042f0 <HAL_RTC_WaitForSynchro+0x40> + while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U) + 80042e0: 687b ldr r3, [r7, #4] + 80042e2: 681b ldr r3, [r3, #0] + 80042e4: 68db ldr r3, [r3, #12] + 80042e6: f003 0320 and.w r3, r3, #32 + 80042ea: 2b00 cmp r3, #0 + 80042ec: d0ee beq.n 80042cc <HAL_RTC_WaitForSynchro+0x1c> + } + } + + return HAL_OK; + 80042ee: 2300 movs r3, #0 +} + 80042f0: 4618 mov r0, r3 + 80042f2: 3710 adds r7, #16 + 80042f4: 46bd mov sp, r7 + 80042f6: bd80 pop {r7, pc} + 80042f8: 0001ff5f .word 0x0001ff5f + +080042fc <RTC_EnterInitMode>: + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) +{ + 80042fc: b580 push {r7, lr} + 80042fe: b084 sub sp, #16 + 8004300: af00 add r7, sp, #0 + 8004302: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 8004304: 2300 movs r3, #0 + 8004306: 60bb str r3, [r7, #8] + HAL_StatusTypeDef status = HAL_OK; + 8004308: 2300 movs r3, #0 + 800430a: 73fb strb r3, [r7, #15] + + /* Check that Initialization mode is not already set */ + if (READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) + 800430c: 687b ldr r3, [r7, #4] + 800430e: 681b ldr r3, [r3, #0] + 8004310: 68db ldr r3, [r3, #12] + 8004312: f003 0340 and.w r3, r3, #64 @ 0x40 + 8004316: 2b00 cmp r3, #0 + 8004318: d123 bne.n 8004362 <RTC_EnterInitMode+0x66> + { + /* Set INIT bit to enter Initialization mode */ + SET_BIT(hrtc->Instance->ISR, RTC_ISR_INIT); + 800431a: 687b ldr r3, [r7, #4] + 800431c: 681b ldr r3, [r3, #0] + 800431e: 68da ldr r2, [r3, #12] + 8004320: 687b ldr r3, [r7, #4] + 8004322: 681b ldr r3, [r3, #0] + 8004324: f042 0280 orr.w r2, r2, #128 @ 0x80 + 8004328: 60da str r2, [r3, #12] + + /* Get tick */ + tickstart = HAL_GetTick(); + 800432a: f7fd fb3b bl 80019a4 <HAL_GetTick> + 800432e: 60b8 str r0, [r7, #8] + + /* Wait till RTC is in INIT state and if timeout is reached exit */ + while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_ERROR)) + 8004330: e00d b.n 800434e <RTC_EnterInitMode+0x52> + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 8004332: f7fd fb37 bl 80019a4 <HAL_GetTick> + 8004336: 4602 mov r2, r0 + 8004338: 68bb ldr r3, [r7, #8] + 800433a: 1ad3 subs r3, r2, r3 + 800433c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 8004340: d905 bls.n 800434e <RTC_EnterInitMode+0x52> + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + 8004342: 687b ldr r3, [r7, #4] + 8004344: 2204 movs r2, #4 + 8004346: f883 2021 strb.w r2, [r3, #33] @ 0x21 + status = HAL_ERROR; + 800434a: 2301 movs r3, #1 + 800434c: 73fb strb r3, [r7, #15] + while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_ERROR)) + 800434e: 687b ldr r3, [r7, #4] + 8004350: 681b ldr r3, [r3, #0] + 8004352: 68db ldr r3, [r3, #12] + 8004354: f003 0340 and.w r3, r3, #64 @ 0x40 + 8004358: 2b00 cmp r3, #0 + 800435a: d102 bne.n 8004362 <RTC_EnterInitMode+0x66> + 800435c: 7bfb ldrb r3, [r7, #15] + 800435e: 2b01 cmp r3, #1 + 8004360: d1e7 bne.n 8004332 <RTC_EnterInitMode+0x36> + } + } + } + + return status; + 8004362: 7bfb ldrb r3, [r7, #15] +} + 8004364: 4618 mov r0, r3 + 8004366: 3710 adds r7, #16 + 8004368: 46bd mov sp, r7 + 800436a: bd80 pop {r7, pc} + +0800436c <RTC_ExitInitMode>: + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) +{ + 800436c: b580 push {r7, lr} + 800436e: b084 sub sp, #16 + 8004370: af00 add r7, sp, #0 + 8004372: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8004374: 2300 movs r3, #0 + 8004376: 73fb strb r3, [r7, #15] + + /* Clear INIT bit to exit Initialization mode */ + CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT); + 8004378: 687b ldr r3, [r7, #4] + 800437a: 681b ldr r3, [r3, #0] + 800437c: 68da ldr r2, [r3, #12] + 800437e: 687b ldr r3, [r7, #4] + 8004380: 681b ldr r3, [r3, #0] + 8004382: f022 0280 bic.w r2, r2, #128 @ 0x80 + 8004386: 60da str r2, [r3, #12] + + /* If CR_BYPSHAD bit = 0, wait for synchro */ + if (READ_BIT(hrtc->Instance->CR, RTC_CR_BYPSHAD) == 0U) + 8004388: 687b ldr r3, [r7, #4] + 800438a: 681b ldr r3, [r3, #0] + 800438c: 689b ldr r3, [r3, #8] + 800438e: f003 0320 and.w r3, r3, #32 + 8004392: 2b00 cmp r3, #0 + 8004394: d10b bne.n 80043ae <RTC_ExitInitMode+0x42> + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + 8004396: 6878 ldr r0, [r7, #4] + 8004398: f7ff ff8a bl 80042b0 <HAL_RTC_WaitForSynchro> + 800439c: 4603 mov r3, r0 + 800439e: 2b00 cmp r3, #0 + 80043a0: d005 beq.n 80043ae <RTC_ExitInitMode+0x42> + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + 80043a2: 687b ldr r3, [r7, #4] + 80043a4: 2204 movs r2, #4 + 80043a6: f883 2021 strb.w r2, [r3, #33] @ 0x21 + status = HAL_ERROR; + 80043aa: 2301 movs r3, #1 + 80043ac: 73fb strb r3, [r7, #15] + } + } + + return status; + 80043ae: 7bfb ldrb r3, [r7, #15] +} + 80043b0: 4618 mov r0, r3 + 80043b2: 3710 adds r7, #16 + 80043b4: 46bd mov sp, r7 + 80043b6: bd80 pop {r7, pc} + +080043b8 <RTC_ByteToBcd2>: + * @brief Converts a 2-digit number from decimal to BCD format. + * @param number decimal-formatted number (from 0 to 99) to be converted + * @retval Converted byte + */ +uint8_t RTC_ByteToBcd2(uint8_t number) +{ + 80043b8: b480 push {r7} + 80043ba: b085 sub sp, #20 + 80043bc: af00 add r7, sp, #0 + 80043be: 4603 mov r3, r0 + 80043c0: 71fb strb r3, [r7, #7] + uint32_t bcdhigh = 0U; + 80043c2: 2300 movs r3, #0 + 80043c4: 60fb str r3, [r7, #12] + + while (number >= 10U) + 80043c6: e005 b.n 80043d4 <RTC_ByteToBcd2+0x1c> + { + bcdhigh++; + 80043c8: 68fb ldr r3, [r7, #12] + 80043ca: 3301 adds r3, #1 + 80043cc: 60fb str r3, [r7, #12] + number -= 10U; + 80043ce: 79fb ldrb r3, [r7, #7] + 80043d0: 3b0a subs r3, #10 + 80043d2: 71fb strb r3, [r7, #7] + while (number >= 10U) + 80043d4: 79fb ldrb r3, [r7, #7] + 80043d6: 2b09 cmp r3, #9 + 80043d8: d8f6 bhi.n 80043c8 <RTC_ByteToBcd2+0x10> + } + + return ((uint8_t)(bcdhigh << 4U) | number); + 80043da: 68fb ldr r3, [r7, #12] + 80043dc: b2db uxtb r3, r3 + 80043de: 011b lsls r3, r3, #4 + 80043e0: b2da uxtb r2, r3 + 80043e2: 79fb ldrb r3, [r7, #7] + 80043e4: 4313 orrs r3, r2 + 80043e6: b2db uxtb r3, r3 +} + 80043e8: 4618 mov r0, r3 + 80043ea: 3714 adds r7, #20 + 80043ec: 46bd mov sp, r7 + 80043ee: f85d 7b04 ldr.w r7, [sp], #4 + 80043f2: 4770 bx lr + +080043f4 <aci_gap_set_non_discoverable>: + */ + +#include "auto/ble_gap_aci.h" + +tBleStatus aci_gap_set_non_discoverable( void ) +{ + 80043f4: b580 push {r7, lr} + 80043f6: b088 sub sp, #32 + 80043f8: af00 add r7, sp, #0 + struct hci_request rq; + tBleStatus status = 0; + 80043fa: 2300 movs r3, #0 + 80043fc: 71fb strb r3, [r7, #7] + Osal_MemSet( &rq, 0, sizeof(rq) ); + 80043fe: f107 0308 add.w r3, r7, #8 + 8004402: 2218 movs r2, #24 + 8004404: 2100 movs r1, #0 + 8004406: 4618 mov r0, r3 + 8004408: f001 f8dd bl 80055c6 <Osal_MemSet> + rq.ogf = 0x3f; + 800440c: 233f movs r3, #63 @ 0x3f + 800440e: 813b strh r3, [r7, #8] + rq.ocf = 0x081; + 8004410: 2381 movs r3, #129 @ 0x81 + 8004412: 817b strh r3, [r7, #10] + rq.rparam = &status; + 8004414: 1dfb adds r3, r7, #7 + 8004416: 61bb str r3, [r7, #24] + rq.rlen = 1; + 8004418: 2301 movs r3, #1 + 800441a: 61fb str r3, [r7, #28] + if ( hci_send_req(&rq, FALSE) < 0 ) + 800441c: f107 0308 add.w r3, r7, #8 + 8004420: 2100 movs r1, #0 + 8004422: 4618 mov r0, r3 + 8004424: f001 fc5e bl 8005ce4 <hci_send_req> + 8004428: 4603 mov r3, r0 + 800442a: 2b00 cmp r3, #0 + 800442c: da01 bge.n 8004432 <aci_gap_set_non_discoverable+0x3e> + return BLE_STATUS_TIMEOUT; + 800442e: 23ff movs r3, #255 @ 0xff + 8004430: e000 b.n 8004434 <aci_gap_set_non_discoverable+0x40> + return status; + 8004432: 79fb ldrb r3, [r7, #7] +} + 8004434: 4618 mov r0, r3 + 8004436: 3720 adds r7, #32 + 8004438: 46bd mov sp, r7 + 800443a: bd80 pop {r7, pc} + +0800443c <aci_gap_set_discoverable>: + const uint8_t* Local_Name, + uint8_t Service_Uuid_length, + const uint8_t* Service_Uuid_List, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max ) +{ + 800443c: b5b0 push {r4, r5, r7, lr} + 800443e: b0ce sub sp, #312 @ 0x138 + 8004440: af00 add r7, sp, #0 + 8004442: 4605 mov r5, r0 + 8004444: 460c mov r4, r1 + 8004446: 4610 mov r0, r2 + 8004448: 4619 mov r1, r3 + 800444a: f507 739c add.w r3, r7, #312 @ 0x138 + 800444e: f2a3 1331 subw r3, r3, #305 @ 0x131 + 8004452: 462a mov r2, r5 + 8004454: 701a strb r2, [r3, #0] + 8004456: f507 739c add.w r3, r7, #312 @ 0x138 + 800445a: f5a3 739a sub.w r3, r3, #308 @ 0x134 + 800445e: 4622 mov r2, r4 + 8004460: 801a strh r2, [r3, #0] + 8004462: f507 739c add.w r3, r7, #312 @ 0x138 + 8004466: f5a3 739b sub.w r3, r3, #310 @ 0x136 + 800446a: 4602 mov r2, r0 + 800446c: 801a strh r2, [r3, #0] + 800446e: f507 739c add.w r3, r7, #312 @ 0x138 + 8004472: f5a3 7399 sub.w r3, r3, #306 @ 0x132 + 8004476: 460a mov r2, r1 + 8004478: 701a strb r2, [r3, #0] + struct hci_request rq; + uint8_t cmd_buffer[BLE_CMD_MAX_PARAM_LEN]; + aci_gap_set_discoverable_cp0 *cp0 = (aci_gap_set_discoverable_cp0*)(cmd_buffer); + 800447a: f107 0310 add.w r3, r7, #16 + 800447e: f8c7 3134 str.w r3, [r7, #308] @ 0x134 + aci_gap_set_discoverable_cp1 *cp1 = (aci_gap_set_discoverable_cp1*)(cmd_buffer + 1 + 2 + 2 + 1 + 1 + 1 + Local_Name_Length * (sizeof(uint8_t))); + 8004482: f897 314c ldrb.w r3, [r7, #332] @ 0x14c + 8004486: 3308 adds r3, #8 + 8004488: f107 0210 add.w r2, r7, #16 + 800448c: 4413 add r3, r2 + 800448e: f8c7 3130 str.w r3, [r7, #304] @ 0x130 + aci_gap_set_discoverable_cp2 *cp2 = (aci_gap_set_discoverable_cp2*)(cmd_buffer + 1 + 2 + 2 + 1 + 1 + 1 + Local_Name_Length * (sizeof(uint8_t)) + 1 + Service_Uuid_length * (sizeof(uint8_t))); + 8004492: f897 214c ldrb.w r2, [r7, #332] @ 0x14c + 8004496: f897 3154 ldrb.w r3, [r7, #340] @ 0x154 + 800449a: 4413 add r3, r2 + 800449c: 3309 adds r3, #9 + 800449e: f107 0210 add.w r2, r7, #16 + 80044a2: 4413 add r3, r2 + 80044a4: f8c7 312c str.w r3, [r7, #300] @ 0x12c + tBleStatus status = 0; + 80044a8: f507 739c add.w r3, r7, #312 @ 0x138 + 80044ac: f2a3 1329 subw r3, r3, #297 @ 0x129 + 80044b0: 2200 movs r2, #0 + 80044b2: 701a strb r2, [r3, #0] + int index_input = 0; + 80044b4: 2300 movs r3, #0 + 80044b6: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Advertising_Type = Advertising_Type; + 80044ba: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 + 80044be: f507 729c add.w r2, r7, #312 @ 0x138 + 80044c2: f2a2 1231 subw r2, r2, #305 @ 0x131 + 80044c6: 7812 ldrb r2, [r2, #0] + 80044c8: 701a strb r2, [r3, #0] + index_input += 1; + 80044ca: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 80044ce: 3301 adds r3, #1 + 80044d0: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Advertising_Interval_Min = Advertising_Interval_Min; + 80044d4: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 + 80044d8: f507 729c add.w r2, r7, #312 @ 0x138 + 80044dc: f5a2 729a sub.w r2, r2, #308 @ 0x134 + 80044e0: 8812 ldrh r2, [r2, #0] + 80044e2: f8a3 2001 strh.w r2, [r3, #1] + index_input += 2; + 80044e6: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 80044ea: 3302 adds r3, #2 + 80044ec: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Advertising_Interval_Max = Advertising_Interval_Max; + 80044f0: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 + 80044f4: f507 729c add.w r2, r7, #312 @ 0x138 + 80044f8: f5a2 729b sub.w r2, r2, #310 @ 0x136 + 80044fc: 8812 ldrh r2, [r2, #0] + 80044fe: f8a3 2003 strh.w r2, [r3, #3] + index_input += 2; + 8004502: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8004506: 3302 adds r3, #2 + 8004508: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Own_Address_Type = Own_Address_Type; + 800450c: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 + 8004510: f507 729c add.w r2, r7, #312 @ 0x138 + 8004514: f5a2 7299 sub.w r2, r2, #306 @ 0x132 + 8004518: 7812 ldrb r2, [r2, #0] + 800451a: 715a strb r2, [r3, #5] + index_input += 1; + 800451c: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8004520: 3301 adds r3, #1 + 8004522: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Advertising_Filter_Policy = Advertising_Filter_Policy; + 8004526: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 + 800452a: f897 2148 ldrb.w r2, [r7, #328] @ 0x148 + 800452e: 719a strb r2, [r3, #6] + index_input += 1; + 8004530: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8004534: 3301 adds r3, #1 + 8004536: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Local_Name_Length = Local_Name_Length; + 800453a: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 + 800453e: f897 214c ldrb.w r2, [r7, #332] @ 0x14c + 8004542: 71da strb r2, [r3, #7] + index_input += 1; + 8004544: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8004548: 3301 adds r3, #1 + 800454a: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + /* var_len_data input */ + { + Osal_MemCpy( (void*)&cp0->Local_Name, (const void*)Local_Name, Local_Name_Length ); + 800454e: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 + 8004552: 3308 adds r3, #8 + 8004554: f897 214c ldrb.w r2, [r7, #332] @ 0x14c + 8004558: f8d7 1150 ldr.w r1, [r7, #336] @ 0x150 + 800455c: 4618 mov r0, r3 + 800455e: f001 f822 bl 80055a6 <Osal_MemCpy> + index_input += Local_Name_Length; + 8004562: f897 314c ldrb.w r3, [r7, #332] @ 0x14c + 8004566: f8d7 2128 ldr.w r2, [r7, #296] @ 0x128 + 800456a: 4413 add r3, r2 + 800456c: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + { + cp1->Service_Uuid_length = Service_Uuid_length; + 8004570: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130 + 8004574: f897 2154 ldrb.w r2, [r7, #340] @ 0x154 + 8004578: 701a strb r2, [r3, #0] + } + index_input += 1; + 800457a: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 800457e: 3301 adds r3, #1 + 8004580: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + Osal_MemCpy( (void*)&cp1->Service_Uuid_List, (const void*)Service_Uuid_List, Service_Uuid_length ); + 8004584: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130 + 8004588: 3301 adds r3, #1 + 800458a: f897 2154 ldrb.w r2, [r7, #340] @ 0x154 + 800458e: f8d7 1158 ldr.w r1, [r7, #344] @ 0x158 + 8004592: 4618 mov r0, r3 + 8004594: f001 f807 bl 80055a6 <Osal_MemCpy> + index_input += Service_Uuid_length; + 8004598: f897 3154 ldrb.w r3, [r7, #340] @ 0x154 + 800459c: f8d7 2128 ldr.w r2, [r7, #296] @ 0x128 + 80045a0: 4413 add r3, r2 + 80045a2: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + { + cp2->Conn_Interval_Min = Conn_Interval_Min; + 80045a6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 80045aa: f8b7 215c ldrh.w r2, [r7, #348] @ 0x15c + 80045ae: 801a strh r2, [r3, #0] + } + index_input += 2; + 80045b0: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 80045b4: 3302 adds r3, #2 + 80045b6: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + { + cp2->Conn_Interval_Max = Conn_Interval_Max; + 80045ba: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 80045be: f8b7 2160 ldrh.w r2, [r7, #352] @ 0x160 + 80045c2: 805a strh r2, [r3, #2] + } + index_input += 2; + 80045c4: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 80045c8: 3302 adds r3, #2 + 80045ca: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + } + Osal_MemSet( &rq, 0, sizeof(rq) ); + 80045ce: f507 7388 add.w r3, r7, #272 @ 0x110 + 80045d2: 2218 movs r2, #24 + 80045d4: 2100 movs r1, #0 + 80045d6: 4618 mov r0, r3 + 80045d8: f000 fff5 bl 80055c6 <Osal_MemSet> + rq.ogf = 0x3f; + 80045dc: 233f movs r3, #63 @ 0x3f + 80045de: f8a7 3110 strh.w r3, [r7, #272] @ 0x110 + rq.ocf = 0x083; + 80045e2: 2383 movs r3, #131 @ 0x83 + 80045e4: f8a7 3112 strh.w r3, [r7, #274] @ 0x112 + rq.cparam = cmd_buffer; + 80045e8: f107 0310 add.w r3, r7, #16 + 80045ec: f8c7 3118 str.w r3, [r7, #280] @ 0x118 + rq.clen = index_input; + 80045f0: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 80045f4: f8c7 311c str.w r3, [r7, #284] @ 0x11c + rq.rparam = &status; + 80045f8: f107 030f add.w r3, r7, #15 + 80045fc: f8c7 3120 str.w r3, [r7, #288] @ 0x120 + rq.rlen = 1; + 8004600: 2301 movs r3, #1 + 8004602: f8c7 3124 str.w r3, [r7, #292] @ 0x124 + if ( hci_send_req(&rq, FALSE) < 0 ) + 8004606: f507 7388 add.w r3, r7, #272 @ 0x110 + 800460a: 2100 movs r1, #0 + 800460c: 4618 mov r0, r3 + 800460e: f001 fb69 bl 8005ce4 <hci_send_req> + 8004612: 4603 mov r3, r0 + 8004614: 2b00 cmp r3, #0 + 8004616: da01 bge.n 800461c <aci_gap_set_discoverable+0x1e0> + return BLE_STATUS_TIMEOUT; + 8004618: 23ff movs r3, #255 @ 0xff + 800461a: e004 b.n 8004626 <aci_gap_set_discoverable+0x1ea> + return status; + 800461c: f507 739c add.w r3, r7, #312 @ 0x138 + 8004620: f2a3 1329 subw r3, r3, #297 @ 0x129 + 8004624: 781b ldrb r3, [r3, #0] +} + 8004626: 4618 mov r0, r3 + 8004628: f507 779c add.w r7, r7, #312 @ 0x138 + 800462c: 46bd mov sp, r7 + 800462e: bdb0 pop {r4, r5, r7, pc} + +08004630 <aci_gap_set_io_capability>: + return BLE_STATUS_TIMEOUT; + return status; +} + +tBleStatus aci_gap_set_io_capability( uint8_t IO_Capability ) +{ + 8004630: b580 push {r7, lr} + 8004632: b0cc sub sp, #304 @ 0x130 + 8004634: af00 add r7, sp, #0 + 8004636: 4602 mov r2, r0 + 8004638: f507 7398 add.w r3, r7, #304 @ 0x130 + 800463c: f2a3 1329 subw r3, r3, #297 @ 0x129 + 8004640: 701a strb r2, [r3, #0] + struct hci_request rq; + uint8_t cmd_buffer[BLE_CMD_MAX_PARAM_LEN]; + aci_gap_set_io_capability_cp0 *cp0 = (aci_gap_set_io_capability_cp0*)(cmd_buffer); + 8004642: f107 0310 add.w r3, r7, #16 + 8004646: f8c7 312c str.w r3, [r7, #300] @ 0x12c + tBleStatus status = 0; + 800464a: f507 7398 add.w r3, r7, #304 @ 0x130 + 800464e: f2a3 1321 subw r3, r3, #289 @ 0x121 + 8004652: 2200 movs r2, #0 + 8004654: 701a strb r2, [r3, #0] + int index_input = 0; + 8004656: 2300 movs r3, #0 + 8004658: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->IO_Capability = IO_Capability; + 800465c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 8004660: f507 7298 add.w r2, r7, #304 @ 0x130 + 8004664: f2a2 1229 subw r2, r2, #297 @ 0x129 + 8004668: 7812 ldrb r2, [r2, #0] + 800466a: 701a strb r2, [r3, #0] + index_input += 1; + 800466c: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8004670: 3301 adds r3, #1 + 8004672: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + Osal_MemSet( &rq, 0, sizeof(rq) ); + 8004676: f507 7388 add.w r3, r7, #272 @ 0x110 + 800467a: 2218 movs r2, #24 + 800467c: 2100 movs r1, #0 + 800467e: 4618 mov r0, r3 + 8004680: f000 ffa1 bl 80055c6 <Osal_MemSet> + rq.ogf = 0x3f; + 8004684: 233f movs r3, #63 @ 0x3f + 8004686: f8a7 3110 strh.w r3, [r7, #272] @ 0x110 + rq.ocf = 0x085; + 800468a: 2385 movs r3, #133 @ 0x85 + 800468c: f8a7 3112 strh.w r3, [r7, #274] @ 0x112 + rq.cparam = cmd_buffer; + 8004690: f107 0310 add.w r3, r7, #16 + 8004694: f8c7 3118 str.w r3, [r7, #280] @ 0x118 + rq.clen = index_input; + 8004698: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 800469c: f8c7 311c str.w r3, [r7, #284] @ 0x11c + rq.rparam = &status; + 80046a0: f107 030f add.w r3, r7, #15 + 80046a4: f8c7 3120 str.w r3, [r7, #288] @ 0x120 + rq.rlen = 1; + 80046a8: 2301 movs r3, #1 + 80046aa: f8c7 3124 str.w r3, [r7, #292] @ 0x124 + if ( hci_send_req(&rq, FALSE) < 0 ) + 80046ae: f507 7388 add.w r3, r7, #272 @ 0x110 + 80046b2: 2100 movs r1, #0 + 80046b4: 4618 mov r0, r3 + 80046b6: f001 fb15 bl 8005ce4 <hci_send_req> + 80046ba: 4603 mov r3, r0 + 80046bc: 2b00 cmp r3, #0 + 80046be: da01 bge.n 80046c4 <aci_gap_set_io_capability+0x94> + return BLE_STATUS_TIMEOUT; + 80046c0: 23ff movs r3, #255 @ 0xff + 80046c2: e004 b.n 80046ce <aci_gap_set_io_capability+0x9e> + return status; + 80046c4: f507 7398 add.w r3, r7, #304 @ 0x130 + 80046c8: f2a3 1321 subw r3, r3, #289 @ 0x121 + 80046cc: 781b ldrb r3, [r3, #0] +} + 80046ce: 4618 mov r0, r3 + 80046d0: f507 7798 add.w r7, r7, #304 @ 0x130 + 80046d4: 46bd mov sp, r7 + 80046d6: bd80 pop {r7, pc} + +080046d8 <aci_gap_set_authentication_requirement>: + uint8_t Min_Encryption_Key_Size, + uint8_t Max_Encryption_Key_Size, + uint8_t Use_Fixed_Pin, + uint32_t Fixed_Pin, + uint8_t Identity_Address_Type ) +{ + 80046d8: b5b0 push {r4, r5, r7, lr} + 80046da: b0cc sub sp, #304 @ 0x130 + 80046dc: af00 add r7, sp, #0 + 80046de: 4605 mov r5, r0 + 80046e0: 460c mov r4, r1 + 80046e2: 4610 mov r0, r2 + 80046e4: 4619 mov r1, r3 + 80046e6: f507 7398 add.w r3, r7, #304 @ 0x130 + 80046ea: f2a3 1329 subw r3, r3, #297 @ 0x129 + 80046ee: 462a mov r2, r5 + 80046f0: 701a strb r2, [r3, #0] + 80046f2: f507 7398 add.w r3, r7, #304 @ 0x130 + 80046f6: f5a3 7395 sub.w r3, r3, #298 @ 0x12a + 80046fa: 4622 mov r2, r4 + 80046fc: 701a strb r2, [r3, #0] + 80046fe: f507 7398 add.w r3, r7, #304 @ 0x130 + 8004702: f2a3 132b subw r3, r3, #299 @ 0x12b + 8004706: 4602 mov r2, r0 + 8004708: 701a strb r2, [r3, #0] + 800470a: f507 7398 add.w r3, r7, #304 @ 0x130 + 800470e: f5a3 7396 sub.w r3, r3, #300 @ 0x12c + 8004712: 460a mov r2, r1 + 8004714: 701a strb r2, [r3, #0] + struct hci_request rq; + uint8_t cmd_buffer[BLE_CMD_MAX_PARAM_LEN]; + aci_gap_set_authentication_requirement_cp0 *cp0 = (aci_gap_set_authentication_requirement_cp0*)(cmd_buffer); + 8004716: f107 0310 add.w r3, r7, #16 + 800471a: f8c7 312c str.w r3, [r7, #300] @ 0x12c + tBleStatus status = 0; + 800471e: f507 7398 add.w r3, r7, #304 @ 0x130 + 8004722: f2a3 1321 subw r3, r3, #289 @ 0x121 + 8004726: 2200 movs r2, #0 + 8004728: 701a strb r2, [r3, #0] + int index_input = 0; + 800472a: 2300 movs r3, #0 + 800472c: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Bonding_Mode = Bonding_Mode; + 8004730: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 8004734: f507 7298 add.w r2, r7, #304 @ 0x130 + 8004738: f2a2 1229 subw r2, r2, #297 @ 0x129 + 800473c: 7812 ldrb r2, [r2, #0] + 800473e: 701a strb r2, [r3, #0] + index_input += 1; + 8004740: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8004744: 3301 adds r3, #1 + 8004746: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->MITM_Mode = MITM_Mode; + 800474a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 800474e: f507 7298 add.w r2, r7, #304 @ 0x130 + 8004752: f5a2 7295 sub.w r2, r2, #298 @ 0x12a + 8004756: 7812 ldrb r2, [r2, #0] + 8004758: 705a strb r2, [r3, #1] + index_input += 1; + 800475a: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 800475e: 3301 adds r3, #1 + 8004760: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->SC_Support = SC_Support; + 8004764: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 8004768: f507 7298 add.w r2, r7, #304 @ 0x130 + 800476c: f2a2 122b subw r2, r2, #299 @ 0x12b + 8004770: 7812 ldrb r2, [r2, #0] + 8004772: 709a strb r2, [r3, #2] + index_input += 1; + 8004774: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8004778: 3301 adds r3, #1 + 800477a: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->KeyPress_Notification_Support = KeyPress_Notification_Support; + 800477e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 8004782: f507 7298 add.w r2, r7, #304 @ 0x130 + 8004786: f5a2 7296 sub.w r2, r2, #300 @ 0x12c + 800478a: 7812 ldrb r2, [r2, #0] + 800478c: 70da strb r2, [r3, #3] + index_input += 1; + 800478e: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8004792: 3301 adds r3, #1 + 8004794: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Min_Encryption_Key_Size = Min_Encryption_Key_Size; + 8004798: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 800479c: f897 2140 ldrb.w r2, [r7, #320] @ 0x140 + 80047a0: 711a strb r2, [r3, #4] + index_input += 1; + 80047a2: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 80047a6: 3301 adds r3, #1 + 80047a8: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Max_Encryption_Key_Size = Max_Encryption_Key_Size; + 80047ac: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 80047b0: f897 2144 ldrb.w r2, [r7, #324] @ 0x144 + 80047b4: 715a strb r2, [r3, #5] + index_input += 1; + 80047b6: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 80047ba: 3301 adds r3, #1 + 80047bc: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Use_Fixed_Pin = Use_Fixed_Pin; + 80047c0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 80047c4: f897 2148 ldrb.w r2, [r7, #328] @ 0x148 + 80047c8: 719a strb r2, [r3, #6] + index_input += 1; + 80047ca: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 80047ce: 3301 adds r3, #1 + 80047d0: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Fixed_Pin = Fixed_Pin; + 80047d4: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 80047d8: f8d7 214c ldr.w r2, [r7, #332] @ 0x14c + 80047dc: f8c3 2007 str.w r2, [r3, #7] + index_input += 4; + 80047e0: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 80047e4: 3304 adds r3, #4 + 80047e6: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Identity_Address_Type = Identity_Address_Type; + 80047ea: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 80047ee: f897 2150 ldrb.w r2, [r7, #336] @ 0x150 + 80047f2: 72da strb r2, [r3, #11] + index_input += 1; + 80047f4: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 80047f8: 3301 adds r3, #1 + 80047fa: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + Osal_MemSet( &rq, 0, sizeof(rq) ); + 80047fe: f507 7388 add.w r3, r7, #272 @ 0x110 + 8004802: 2218 movs r2, #24 + 8004804: 2100 movs r1, #0 + 8004806: 4618 mov r0, r3 + 8004808: f000 fedd bl 80055c6 <Osal_MemSet> + rq.ogf = 0x3f; + 800480c: 233f movs r3, #63 @ 0x3f + 800480e: f8a7 3110 strh.w r3, [r7, #272] @ 0x110 + rq.ocf = 0x086; + 8004812: 2386 movs r3, #134 @ 0x86 + 8004814: f8a7 3112 strh.w r3, [r7, #274] @ 0x112 + rq.cparam = cmd_buffer; + 8004818: f107 0310 add.w r3, r7, #16 + 800481c: f8c7 3118 str.w r3, [r7, #280] @ 0x118 + rq.clen = index_input; + 8004820: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8004824: f8c7 311c str.w r3, [r7, #284] @ 0x11c + rq.rparam = &status; + 8004828: f107 030f add.w r3, r7, #15 + 800482c: f8c7 3120 str.w r3, [r7, #288] @ 0x120 + rq.rlen = 1; + 8004830: 2301 movs r3, #1 + 8004832: f8c7 3124 str.w r3, [r7, #292] @ 0x124 + if ( hci_send_req(&rq, FALSE) < 0 ) + 8004836: f507 7388 add.w r3, r7, #272 @ 0x110 + 800483a: 2100 movs r1, #0 + 800483c: 4618 mov r0, r3 + 800483e: f001 fa51 bl 8005ce4 <hci_send_req> + 8004842: 4603 mov r3, r0 + 8004844: 2b00 cmp r3, #0 + 8004846: da01 bge.n 800484c <aci_gap_set_authentication_requirement+0x174> + return BLE_STATUS_TIMEOUT; + 8004848: 23ff movs r3, #255 @ 0xff + 800484a: e004 b.n 8004856 <aci_gap_set_authentication_requirement+0x17e> + return status; + 800484c: f507 7398 add.w r3, r7, #304 @ 0x130 + 8004850: f2a3 1321 subw r3, r3, #289 @ 0x121 + 8004854: 781b ldrb r3, [r3, #0] +} + 8004856: 4618 mov r0, r3 + 8004858: f507 7798 add.w r7, r7, #304 @ 0x130 + 800485c: 46bd mov sp, r7 + 800485e: bdb0 pop {r4, r5, r7, pc} + +08004860 <aci_gap_init>: + uint8_t privacy_enabled, + uint8_t device_name_char_len, + uint16_t* Service_Handle, + uint16_t* Dev_Name_Char_Handle, + uint16_t* Appearance_Char_Handle ) +{ + 8004860: b590 push {r4, r7, lr} + 8004862: b0cd sub sp, #308 @ 0x134 + 8004864: af00 add r7, sp, #0 + 8004866: 4604 mov r4, r0 + 8004868: 4608 mov r0, r1 + 800486a: 4611 mov r1, r2 + 800486c: f507 7298 add.w r2, r7, #304 @ 0x130 + 8004870: f5a2 7298 sub.w r2, r2, #304 @ 0x130 + 8004874: 6013 str r3, [r2, #0] + 8004876: f507 7398 add.w r3, r7, #304 @ 0x130 + 800487a: f2a3 1329 subw r3, r3, #297 @ 0x129 + 800487e: 4622 mov r2, r4 + 8004880: 701a strb r2, [r3, #0] + 8004882: f507 7398 add.w r3, r7, #304 @ 0x130 + 8004886: f5a3 7395 sub.w r3, r3, #298 @ 0x12a + 800488a: 4602 mov r2, r0 + 800488c: 701a strb r2, [r3, #0] + 800488e: f507 7398 add.w r3, r7, #304 @ 0x130 + 8004892: f2a3 132b subw r3, r3, #299 @ 0x12b + 8004896: 460a mov r2, r1 + 8004898: 701a strb r2, [r3, #0] + struct hci_request rq; + uint8_t cmd_buffer[BLE_CMD_MAX_PARAM_LEN]; + aci_gap_init_cp0 *cp0 = (aci_gap_init_cp0*)(cmd_buffer); + 800489a: f107 0310 add.w r3, r7, #16 + 800489e: f8c7 312c str.w r3, [r7, #300] @ 0x12c + aci_gap_init_rp0 resp; + Osal_MemSet( &resp, 0, sizeof(resp) ); + 80048a2: f107 0308 add.w r3, r7, #8 + 80048a6: 2207 movs r2, #7 + 80048a8: 2100 movs r1, #0 + 80048aa: 4618 mov r0, r3 + 80048ac: f000 fe8b bl 80055c6 <Osal_MemSet> + int index_input = 0; + 80048b0: 2300 movs r3, #0 + 80048b2: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Role = Role; + 80048b6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 80048ba: f507 7298 add.w r2, r7, #304 @ 0x130 + 80048be: f2a2 1229 subw r2, r2, #297 @ 0x129 + 80048c2: 7812 ldrb r2, [r2, #0] + 80048c4: 701a strb r2, [r3, #0] + index_input += 1; + 80048c6: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 80048ca: 3301 adds r3, #1 + 80048cc: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->privacy_enabled = privacy_enabled; + 80048d0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 80048d4: f507 7298 add.w r2, r7, #304 @ 0x130 + 80048d8: f5a2 7295 sub.w r2, r2, #298 @ 0x12a + 80048dc: 7812 ldrb r2, [r2, #0] + 80048de: 705a strb r2, [r3, #1] + index_input += 1; + 80048e0: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 80048e4: 3301 adds r3, #1 + 80048e6: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->device_name_char_len = device_name_char_len; + 80048ea: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 80048ee: f507 7298 add.w r2, r7, #304 @ 0x130 + 80048f2: f2a2 122b subw r2, r2, #299 @ 0x12b + 80048f6: 7812 ldrb r2, [r2, #0] + 80048f8: 709a strb r2, [r3, #2] + index_input += 1; + 80048fa: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 80048fe: 3301 adds r3, #1 + 8004900: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + Osal_MemSet( &rq, 0, sizeof(rq) ); + 8004904: f507 7388 add.w r3, r7, #272 @ 0x110 + 8004908: 2218 movs r2, #24 + 800490a: 2100 movs r1, #0 + 800490c: 4618 mov r0, r3 + 800490e: f000 fe5a bl 80055c6 <Osal_MemSet> + rq.ogf = 0x3f; + 8004912: 233f movs r3, #63 @ 0x3f + 8004914: f8a7 3110 strh.w r3, [r7, #272] @ 0x110 + rq.ocf = 0x08a; + 8004918: 238a movs r3, #138 @ 0x8a + 800491a: f8a7 3112 strh.w r3, [r7, #274] @ 0x112 + rq.cparam = cmd_buffer; + 800491e: f107 0310 add.w r3, r7, #16 + 8004922: f8c7 3118 str.w r3, [r7, #280] @ 0x118 + rq.clen = index_input; + 8004926: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 800492a: f8c7 311c str.w r3, [r7, #284] @ 0x11c + rq.rparam = &resp; + 800492e: f107 0308 add.w r3, r7, #8 + 8004932: f8c7 3120 str.w r3, [r7, #288] @ 0x120 + rq.rlen = sizeof(resp); + 8004936: 2307 movs r3, #7 + 8004938: f8c7 3124 str.w r3, [r7, #292] @ 0x124 + if ( hci_send_req(&rq, FALSE) < 0 ) + 800493c: f507 7388 add.w r3, r7, #272 @ 0x110 + 8004940: 2100 movs r1, #0 + 8004942: 4618 mov r0, r3 + 8004944: f001 f9ce bl 8005ce4 <hci_send_req> + 8004948: 4603 mov r3, r0 + 800494a: 2b00 cmp r3, #0 + 800494c: da01 bge.n 8004952 <aci_gap_init+0xf2> + return BLE_STATUS_TIMEOUT; + 800494e: 23ff movs r3, #255 @ 0xff + 8004950: e02e b.n 80049b0 <aci_gap_init+0x150> + if ( resp.Status ) + 8004952: f507 7398 add.w r3, r7, #304 @ 0x130 + 8004956: f5a3 7394 sub.w r3, r3, #296 @ 0x128 + 800495a: 781b ldrb r3, [r3, #0] + 800495c: 2b00 cmp r3, #0 + 800495e: d005 beq.n 800496c <aci_gap_init+0x10c> + return resp.Status; + 8004960: f507 7398 add.w r3, r7, #304 @ 0x130 + 8004964: f5a3 7394 sub.w r3, r3, #296 @ 0x128 + 8004968: 781b ldrb r3, [r3, #0] + 800496a: e021 b.n 80049b0 <aci_gap_init+0x150> + *Service_Handle = resp.Service_Handle; + 800496c: f507 7398 add.w r3, r7, #304 @ 0x130 + 8004970: f5a3 7394 sub.w r3, r3, #296 @ 0x128 + 8004974: f8b3 3001 ldrh.w r3, [r3, #1] + 8004978: b29a uxth r2, r3 + 800497a: f507 7398 add.w r3, r7, #304 @ 0x130 + 800497e: f5a3 7398 sub.w r3, r3, #304 @ 0x130 + 8004982: 681b ldr r3, [r3, #0] + 8004984: 801a strh r2, [r3, #0] + *Dev_Name_Char_Handle = resp.Dev_Name_Char_Handle; + 8004986: f507 7398 add.w r3, r7, #304 @ 0x130 + 800498a: f5a3 7394 sub.w r3, r3, #296 @ 0x128 + 800498e: f8b3 3003 ldrh.w r3, [r3, #3] + 8004992: b29a uxth r2, r3 + 8004994: f8d7 3140 ldr.w r3, [r7, #320] @ 0x140 + 8004998: 801a strh r2, [r3, #0] + *Appearance_Char_Handle = resp.Appearance_Char_Handle; + 800499a: f507 7398 add.w r3, r7, #304 @ 0x130 + 800499e: f5a3 7394 sub.w r3, r3, #296 @ 0x128 + 80049a2: f8b3 3005 ldrh.w r3, [r3, #5] + 80049a6: b29a uxth r2, r3 + 80049a8: f8d7 3144 ldr.w r3, [r7, #324] @ 0x144 + 80049ac: 801a strh r2, [r3, #0] + return BLE_STATUS_SUCCESS; + 80049ae: 2300 movs r3, #0 +} + 80049b0: 4618 mov r0, r3 + 80049b2: f507 779a add.w r7, r7, #308 @ 0x134 + 80049b6: 46bd mov sp, r7 + 80049b8: bd90 pop {r4, r7, pc} + +080049ba <aci_gap_update_adv_data>: + return status; +} + +tBleStatus aci_gap_update_adv_data( uint8_t AdvDataLen, + const uint8_t* AdvData ) +{ + 80049ba: b580 push {r7, lr} + 80049bc: b0cc sub sp, #304 @ 0x130 + 80049be: af00 add r7, sp, #0 + 80049c0: 4602 mov r2, r0 + 80049c2: f507 7398 add.w r3, r7, #304 @ 0x130 + 80049c6: f5a3 7398 sub.w r3, r3, #304 @ 0x130 + 80049ca: 6019 str r1, [r3, #0] + 80049cc: f507 7398 add.w r3, r7, #304 @ 0x130 + 80049d0: f2a3 1329 subw r3, r3, #297 @ 0x129 + 80049d4: 701a strb r2, [r3, #0] + struct hci_request rq; + uint8_t cmd_buffer[BLE_CMD_MAX_PARAM_LEN]; + aci_gap_update_adv_data_cp0 *cp0 = (aci_gap_update_adv_data_cp0*)(cmd_buffer); + 80049d6: f107 0310 add.w r3, r7, #16 + 80049da: f8c7 312c str.w r3, [r7, #300] @ 0x12c + tBleStatus status = 0; + 80049de: f507 7398 add.w r3, r7, #304 @ 0x130 + 80049e2: f2a3 1321 subw r3, r3, #289 @ 0x121 + 80049e6: 2200 movs r2, #0 + 80049e8: 701a strb r2, [r3, #0] + int index_input = 0; + 80049ea: 2300 movs r3, #0 + 80049ec: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->AdvDataLen = AdvDataLen; + 80049f0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 80049f4: f507 7298 add.w r2, r7, #304 @ 0x130 + 80049f8: f2a2 1229 subw r2, r2, #297 @ 0x129 + 80049fc: 7812 ldrb r2, [r2, #0] + 80049fe: 701a strb r2, [r3, #0] + index_input += 1; + 8004a00: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8004a04: 3301 adds r3, #1 + 8004a06: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + Osal_MemCpy( (void*)&cp0->AdvData, (const void*)AdvData, AdvDataLen ); + 8004a0a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 8004a0e: 1c58 adds r0, r3, #1 + 8004a10: f507 7398 add.w r3, r7, #304 @ 0x130 + 8004a14: f2a3 1329 subw r3, r3, #297 @ 0x129 + 8004a18: 781a ldrb r2, [r3, #0] + 8004a1a: f507 7398 add.w r3, r7, #304 @ 0x130 + 8004a1e: f5a3 7398 sub.w r3, r3, #304 @ 0x130 + 8004a22: 6819 ldr r1, [r3, #0] + 8004a24: f000 fdbf bl 80055a6 <Osal_MemCpy> + index_input += AdvDataLen; + 8004a28: f507 7398 add.w r3, r7, #304 @ 0x130 + 8004a2c: f2a3 1329 subw r3, r3, #297 @ 0x129 + 8004a30: 781b ldrb r3, [r3, #0] + 8004a32: f8d7 2128 ldr.w r2, [r7, #296] @ 0x128 + 8004a36: 4413 add r3, r2 + 8004a38: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + Osal_MemSet( &rq, 0, sizeof(rq) ); + 8004a3c: f507 7388 add.w r3, r7, #272 @ 0x110 + 8004a40: 2218 movs r2, #24 + 8004a42: 2100 movs r1, #0 + 8004a44: 4618 mov r0, r3 + 8004a46: f000 fdbe bl 80055c6 <Osal_MemSet> + rq.ogf = 0x3f; + 8004a4a: 233f movs r3, #63 @ 0x3f + 8004a4c: f8a7 3110 strh.w r3, [r7, #272] @ 0x110 + rq.ocf = 0x08e; + 8004a50: 238e movs r3, #142 @ 0x8e + 8004a52: f8a7 3112 strh.w r3, [r7, #274] @ 0x112 + rq.cparam = cmd_buffer; + 8004a56: f107 0310 add.w r3, r7, #16 + 8004a5a: f8c7 3118 str.w r3, [r7, #280] @ 0x118 + rq.clen = index_input; + 8004a5e: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8004a62: f8c7 311c str.w r3, [r7, #284] @ 0x11c + rq.rparam = &status; + 8004a66: f107 030f add.w r3, r7, #15 + 8004a6a: f8c7 3120 str.w r3, [r7, #288] @ 0x120 + rq.rlen = 1; + 8004a6e: 2301 movs r3, #1 + 8004a70: f8c7 3124 str.w r3, [r7, #292] @ 0x124 + if ( hci_send_req(&rq, FALSE) < 0 ) + 8004a74: f507 7388 add.w r3, r7, #272 @ 0x110 + 8004a78: 2100 movs r1, #0 + 8004a7a: 4618 mov r0, r3 + 8004a7c: f001 f932 bl 8005ce4 <hci_send_req> + 8004a80: 4603 mov r3, r0 + 8004a82: 2b00 cmp r3, #0 + 8004a84: da01 bge.n 8004a8a <aci_gap_update_adv_data+0xd0> + return BLE_STATUS_TIMEOUT; + 8004a86: 23ff movs r3, #255 @ 0xff + 8004a88: e004 b.n 8004a94 <aci_gap_update_adv_data+0xda> + return status; + 8004a8a: f507 7398 add.w r3, r7, #304 @ 0x130 + 8004a8e: f2a3 1321 subw r3, r3, #289 @ 0x121 + 8004a92: 781b ldrb r3, [r3, #0] +} + 8004a94: 4618 mov r0, r3 + 8004a96: f507 7798 add.w r7, r7, #304 @ 0x130 + 8004a9a: 46bd mov sp, r7 + 8004a9c: bd80 pop {r7, pc} + +08004a9e <aci_gap_configure_filter_accept_list>: + return BLE_STATUS_TIMEOUT; + return status; +} + +tBleStatus aci_gap_configure_filter_accept_list( void ) +{ + 8004a9e: b580 push {r7, lr} + 8004aa0: b088 sub sp, #32 + 8004aa2: af00 add r7, sp, #0 + struct hci_request rq; + tBleStatus status = 0; + 8004aa4: 2300 movs r3, #0 + 8004aa6: 71fb strb r3, [r7, #7] + Osal_MemSet( &rq, 0, sizeof(rq) ); + 8004aa8: f107 0308 add.w r3, r7, #8 + 8004aac: 2218 movs r2, #24 + 8004aae: 2100 movs r1, #0 + 8004ab0: 4618 mov r0, r3 + 8004ab2: f000 fd88 bl 80055c6 <Osal_MemSet> + rq.ogf = 0x3f; + 8004ab6: 233f movs r3, #63 @ 0x3f + 8004ab8: 813b strh r3, [r7, #8] + rq.ocf = 0x092; + 8004aba: 2392 movs r3, #146 @ 0x92 + 8004abc: 817b strh r3, [r7, #10] + rq.rparam = &status; + 8004abe: 1dfb adds r3, r7, #7 + 8004ac0: 61bb str r3, [r7, #24] + rq.rlen = 1; + 8004ac2: 2301 movs r3, #1 + 8004ac4: 61fb str r3, [r7, #28] + if ( hci_send_req(&rq, FALSE) < 0 ) + 8004ac6: f107 0308 add.w r3, r7, #8 + 8004aca: 2100 movs r1, #0 + 8004acc: 4618 mov r0, r3 + 8004ace: f001 f909 bl 8005ce4 <hci_send_req> + 8004ad2: 4603 mov r3, r0 + 8004ad4: 2b00 cmp r3, #0 + 8004ad6: da01 bge.n 8004adc <aci_gap_configure_filter_accept_list+0x3e> + return BLE_STATUS_TIMEOUT; + 8004ad8: 23ff movs r3, #255 @ 0xff + 8004ada: e000 b.n 8004ade <aci_gap_configure_filter_accept_list+0x40> + return status; + 8004adc: 79fb ldrb r3, [r7, #7] +} + 8004ade: 4618 mov r0, r3 + 8004ae0: 3720 adds r7, #32 + 8004ae2: 46bd mov sp, r7 + 8004ae4: bd80 pop {r7, pc} + +08004ae6 <aci_gatt_init>: + */ + +#include "auto/ble_gatt_aci.h" + +tBleStatus aci_gatt_init( void ) +{ + 8004ae6: b580 push {r7, lr} + 8004ae8: b088 sub sp, #32 + 8004aea: af00 add r7, sp, #0 + struct hci_request rq; + tBleStatus status = 0; + 8004aec: 2300 movs r3, #0 + 8004aee: 71fb strb r3, [r7, #7] + Osal_MemSet( &rq, 0, sizeof(rq) ); + 8004af0: f107 0308 add.w r3, r7, #8 + 8004af4: 2218 movs r2, #24 + 8004af6: 2100 movs r1, #0 + 8004af8: 4618 mov r0, r3 + 8004afa: f000 fd64 bl 80055c6 <Osal_MemSet> + rq.ogf = 0x3f; + 8004afe: 233f movs r3, #63 @ 0x3f + 8004b00: 813b strh r3, [r7, #8] + rq.ocf = 0x101; + 8004b02: f240 1301 movw r3, #257 @ 0x101 + 8004b06: 817b strh r3, [r7, #10] + rq.rparam = &status; + 8004b08: 1dfb adds r3, r7, #7 + 8004b0a: 61bb str r3, [r7, #24] + rq.rlen = 1; + 8004b0c: 2301 movs r3, #1 + 8004b0e: 61fb str r3, [r7, #28] + if ( hci_send_req(&rq, FALSE) < 0 ) + 8004b10: f107 0308 add.w r3, r7, #8 + 8004b14: 2100 movs r1, #0 + 8004b16: 4618 mov r0, r3 + 8004b18: f001 f8e4 bl 8005ce4 <hci_send_req> + 8004b1c: 4603 mov r3, r0 + 8004b1e: 2b00 cmp r3, #0 + 8004b20: da01 bge.n 8004b26 <aci_gatt_init+0x40> + return BLE_STATUS_TIMEOUT; + 8004b22: 23ff movs r3, #255 @ 0xff + 8004b24: e000 b.n 8004b28 <aci_gatt_init+0x42> + return status; + 8004b26: 79fb ldrb r3, [r7, #7] +} + 8004b28: 4618 mov r0, r3 + 8004b2a: 3720 adds r7, #32 + 8004b2c: 46bd mov sp, r7 + 8004b2e: bd80 pop {r7, pc} + +08004b30 <aci_gatt_add_service>: +tBleStatus aci_gatt_add_service( uint8_t Service_UUID_Type, + const Service_UUID_t* Service_UUID, + uint8_t Service_Type, + uint8_t Max_Attribute_Records, + uint16_t* Service_Handle ) +{ + 8004b30: b590 push {r4, r7, lr} + 8004b32: b0cf sub sp, #316 @ 0x13c + 8004b34: af00 add r7, sp, #0 + 8004b36: 4604 mov r4, r0 + 8004b38: f507 709c add.w r0, r7, #312 @ 0x138 + 8004b3c: f5a0 709c sub.w r0, r0, #312 @ 0x138 + 8004b40: 6001 str r1, [r0, #0] + 8004b42: 4610 mov r0, r2 + 8004b44: 4619 mov r1, r3 + 8004b46: f507 739c add.w r3, r7, #312 @ 0x138 + 8004b4a: f2a3 1331 subw r3, r3, #305 @ 0x131 + 8004b4e: 4622 mov r2, r4 + 8004b50: 701a strb r2, [r3, #0] + 8004b52: f507 739c add.w r3, r7, #312 @ 0x138 + 8004b56: f5a3 7399 sub.w r3, r3, #306 @ 0x132 + 8004b5a: 4602 mov r2, r0 + 8004b5c: 701a strb r2, [r3, #0] + 8004b5e: f507 739c add.w r3, r7, #312 @ 0x138 + 8004b62: f2a3 1333 subw r3, r3, #307 @ 0x133 + 8004b66: 460a mov r2, r1 + 8004b68: 701a strb r2, [r3, #0] + struct hci_request rq; + uint8_t cmd_buffer[BLE_CMD_MAX_PARAM_LEN]; + aci_gatt_add_service_cp0 *cp0 = (aci_gatt_add_service_cp0*)(cmd_buffer); + 8004b6a: f107 0310 add.w r3, r7, #16 + 8004b6e: f8c7 3130 str.w r3, [r7, #304] @ 0x130 + aci_gatt_add_service_cp1 *cp1 = (aci_gatt_add_service_cp1*)(cmd_buffer + 1 + (Service_UUID_Type == 1 ? 2 : (Service_UUID_Type == 2 ? 16 : 0))); + 8004b72: f507 739c add.w r3, r7, #312 @ 0x138 + 8004b76: f2a3 1331 subw r3, r3, #305 @ 0x131 + 8004b7a: 781b ldrb r3, [r3, #0] + 8004b7c: 2b01 cmp r3, #1 + 8004b7e: d00a beq.n 8004b96 <aci_gatt_add_service+0x66> + 8004b80: f507 739c add.w r3, r7, #312 @ 0x138 + 8004b84: f2a3 1331 subw r3, r3, #305 @ 0x131 + 8004b88: 781b ldrb r3, [r3, #0] + 8004b8a: 2b02 cmp r3, #2 + 8004b8c: d101 bne.n 8004b92 <aci_gatt_add_service+0x62> + 8004b8e: 2311 movs r3, #17 + 8004b90: e002 b.n 8004b98 <aci_gatt_add_service+0x68> + 8004b92: 2301 movs r3, #1 + 8004b94: e000 b.n 8004b98 <aci_gatt_add_service+0x68> + 8004b96: 2303 movs r3, #3 + 8004b98: f107 0210 add.w r2, r7, #16 + 8004b9c: 4413 add r3, r2 + 8004b9e: f8c7 312c str.w r3, [r7, #300] @ 0x12c + aci_gatt_add_service_rp0 resp; + Osal_MemSet( &resp, 0, sizeof(resp) ); + 8004ba2: f107 030c add.w r3, r7, #12 + 8004ba6: 2203 movs r2, #3 + 8004ba8: 2100 movs r1, #0 + 8004baa: 4618 mov r0, r3 + 8004bac: f000 fd0b bl 80055c6 <Osal_MemSet> + int index_input = 0; + 8004bb0: 2300 movs r3, #0 + 8004bb2: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Service_UUID_Type = Service_UUID_Type; + 8004bb6: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130 + 8004bba: f507 729c add.w r2, r7, #312 @ 0x138 + 8004bbe: f2a2 1231 subw r2, r2, #305 @ 0x131 + 8004bc2: 7812 ldrb r2, [r2, #0] + 8004bc4: 701a strb r2, [r3, #0] + index_input += 1; + 8004bc6: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8004bca: 3301 adds r3, #1 + 8004bcc: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + /* var_len_data input */ + { + uint8_t size; + switch ( Service_UUID_Type ) + 8004bd0: f507 739c add.w r3, r7, #312 @ 0x138 + 8004bd4: f2a3 1331 subw r3, r3, #305 @ 0x131 + 8004bd8: 781b ldrb r3, [r3, #0] + 8004bda: 2b01 cmp r3, #1 + 8004bdc: d002 beq.n 8004be4 <aci_gatt_add_service+0xb4> + 8004bde: 2b02 cmp r3, #2 + 8004be0: d004 beq.n 8004bec <aci_gatt_add_service+0xbc> + 8004be2: e007 b.n 8004bf4 <aci_gatt_add_service+0xc4> + { + case 1: size = 2; break; + 8004be4: 2302 movs r3, #2 + 8004be6: f887 3137 strb.w r3, [r7, #311] @ 0x137 + 8004bea: e005 b.n 8004bf8 <aci_gatt_add_service+0xc8> + case 2: size = 16; break; + 8004bec: 2310 movs r3, #16 + 8004bee: f887 3137 strb.w r3, [r7, #311] @ 0x137 + 8004bf2: e001 b.n 8004bf8 <aci_gatt_add_service+0xc8> + default: return BLE_STATUS_ERROR; + 8004bf4: 2397 movs r3, #151 @ 0x97 + 8004bf6: e06c b.n 8004cd2 <aci_gatt_add_service+0x1a2> + } + Osal_MemCpy( (void*)&cp0->Service_UUID, (const void*)Service_UUID, size ); + 8004bf8: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130 + 8004bfc: 1c58 adds r0, r3, #1 + 8004bfe: f897 2137 ldrb.w r2, [r7, #311] @ 0x137 + 8004c02: f507 739c add.w r3, r7, #312 @ 0x138 + 8004c06: f5a3 739c sub.w r3, r3, #312 @ 0x138 + 8004c0a: 6819 ldr r1, [r3, #0] + 8004c0c: f000 fccb bl 80055a6 <Osal_MemCpy> + index_input += size; + 8004c10: f897 3137 ldrb.w r3, [r7, #311] @ 0x137 + 8004c14: f8d7 2128 ldr.w r2, [r7, #296] @ 0x128 + 8004c18: 4413 add r3, r2 + 8004c1a: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + { + cp1->Service_Type = Service_Type; + 8004c1e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 8004c22: f507 729c add.w r2, r7, #312 @ 0x138 + 8004c26: f5a2 7299 sub.w r2, r2, #306 @ 0x132 + 8004c2a: 7812 ldrb r2, [r2, #0] + 8004c2c: 701a strb r2, [r3, #0] + } + index_input += 1; + 8004c2e: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8004c32: 3301 adds r3, #1 + 8004c34: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + { + cp1->Max_Attribute_Records = Max_Attribute_Records; + 8004c38: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 8004c3c: f507 729c add.w r2, r7, #312 @ 0x138 + 8004c40: f2a2 1233 subw r2, r2, #307 @ 0x133 + 8004c44: 7812 ldrb r2, [r2, #0] + 8004c46: 705a strb r2, [r3, #1] + } + index_input += 1; + 8004c48: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8004c4c: 3301 adds r3, #1 + 8004c4e: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + } + Osal_MemSet( &rq, 0, sizeof(rq) ); + 8004c52: f507 7388 add.w r3, r7, #272 @ 0x110 + 8004c56: 2218 movs r2, #24 + 8004c58: 2100 movs r1, #0 + 8004c5a: 4618 mov r0, r3 + 8004c5c: f000 fcb3 bl 80055c6 <Osal_MemSet> + rq.ogf = 0x3f; + 8004c60: 233f movs r3, #63 @ 0x3f + 8004c62: f8a7 3110 strh.w r3, [r7, #272] @ 0x110 + rq.ocf = 0x102; + 8004c66: f44f 7381 mov.w r3, #258 @ 0x102 + 8004c6a: f8a7 3112 strh.w r3, [r7, #274] @ 0x112 + rq.cparam = cmd_buffer; + 8004c6e: f107 0310 add.w r3, r7, #16 + 8004c72: f8c7 3118 str.w r3, [r7, #280] @ 0x118 + rq.clen = index_input; + 8004c76: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8004c7a: f8c7 311c str.w r3, [r7, #284] @ 0x11c + rq.rparam = &resp; + 8004c7e: f107 030c add.w r3, r7, #12 + 8004c82: f8c7 3120 str.w r3, [r7, #288] @ 0x120 + rq.rlen = sizeof(resp); + 8004c86: 2303 movs r3, #3 + 8004c88: f8c7 3124 str.w r3, [r7, #292] @ 0x124 + if ( hci_send_req(&rq, FALSE) < 0 ) + 8004c8c: f507 7388 add.w r3, r7, #272 @ 0x110 + 8004c90: 2100 movs r1, #0 + 8004c92: 4618 mov r0, r3 + 8004c94: f001 f826 bl 8005ce4 <hci_send_req> + 8004c98: 4603 mov r3, r0 + 8004c9a: 2b00 cmp r3, #0 + 8004c9c: da01 bge.n 8004ca2 <aci_gatt_add_service+0x172> + return BLE_STATUS_TIMEOUT; + 8004c9e: 23ff movs r3, #255 @ 0xff + 8004ca0: e017 b.n 8004cd2 <aci_gatt_add_service+0x1a2> + if ( resp.Status ) + 8004ca2: f507 739c add.w r3, r7, #312 @ 0x138 + 8004ca6: f5a3 7396 sub.w r3, r3, #300 @ 0x12c + 8004caa: 781b ldrb r3, [r3, #0] + 8004cac: 2b00 cmp r3, #0 + 8004cae: d005 beq.n 8004cbc <aci_gatt_add_service+0x18c> + return resp.Status; + 8004cb0: f507 739c add.w r3, r7, #312 @ 0x138 + 8004cb4: f5a3 7396 sub.w r3, r3, #300 @ 0x12c + 8004cb8: 781b ldrb r3, [r3, #0] + 8004cba: e00a b.n 8004cd2 <aci_gatt_add_service+0x1a2> + *Service_Handle = resp.Service_Handle; + 8004cbc: f507 739c add.w r3, r7, #312 @ 0x138 + 8004cc0: f5a3 7396 sub.w r3, r3, #300 @ 0x12c + 8004cc4: f8b3 3001 ldrh.w r3, [r3, #1] + 8004cc8: b29a uxth r2, r3 + 8004cca: f8d7 3148 ldr.w r3, [r7, #328] @ 0x148 + 8004cce: 801a strh r2, [r3, #0] + return BLE_STATUS_SUCCESS; + 8004cd0: 2300 movs r3, #0 +} + 8004cd2: 4618 mov r0, r3 + 8004cd4: f507 779e add.w r7, r7, #316 @ 0x13c + 8004cd8: 46bd mov sp, r7 + 8004cda: bd90 pop {r4, r7, pc} + +08004cdc <aci_gatt_add_char>: + uint8_t Security_Permissions, + uint8_t GATT_Evt_Mask, + uint8_t Enc_Key_Size, + uint8_t Is_Variable, + uint16_t* Char_Handle ) +{ + 8004cdc: b590 push {r4, r7, lr} + 8004cde: b0d1 sub sp, #324 @ 0x144 + 8004ce0: af00 add r7, sp, #0 + 8004ce2: 4604 mov r4, r0 + 8004ce4: 4608 mov r0, r1 + 8004ce6: f507 71a0 add.w r1, r7, #320 @ 0x140 + 8004cea: f5a1 719c sub.w r1, r1, #312 @ 0x138 + 8004cee: 600a str r2, [r1, #0] + 8004cf0: 4619 mov r1, r3 + 8004cf2: f507 73a0 add.w r3, r7, #320 @ 0x140 + 8004cf6: f5a3 7399 sub.w r3, r3, #306 @ 0x132 + 8004cfa: 4622 mov r2, r4 + 8004cfc: 801a strh r2, [r3, #0] + 8004cfe: f507 73a0 add.w r3, r7, #320 @ 0x140 + 8004d02: f2a3 1333 subw r3, r3, #307 @ 0x133 + 8004d06: 4602 mov r2, r0 + 8004d08: 701a strb r2, [r3, #0] + 8004d0a: f507 73a0 add.w r3, r7, #320 @ 0x140 + 8004d0e: f5a3 739d sub.w r3, r3, #314 @ 0x13a + 8004d12: 460a mov r2, r1 + 8004d14: 801a strh r2, [r3, #0] + struct hci_request rq; + uint8_t cmd_buffer[BLE_CMD_MAX_PARAM_LEN]; + aci_gatt_add_char_cp0 *cp0 = (aci_gatt_add_char_cp0*)(cmd_buffer); + 8004d16: f107 0318 add.w r3, r7, #24 + 8004d1a: f8c7 3138 str.w r3, [r7, #312] @ 0x138 + aci_gatt_add_char_cp1 *cp1 = (aci_gatt_add_char_cp1*)(cmd_buffer + 2 + 1 + (Char_UUID_Type == 1 ? 2 : (Char_UUID_Type == 2 ? 16 : 0))); + 8004d1e: f507 73a0 add.w r3, r7, #320 @ 0x140 + 8004d22: f2a3 1333 subw r3, r3, #307 @ 0x133 + 8004d26: 781b ldrb r3, [r3, #0] + 8004d28: 2b01 cmp r3, #1 + 8004d2a: d00a beq.n 8004d42 <aci_gatt_add_char+0x66> + 8004d2c: f507 73a0 add.w r3, r7, #320 @ 0x140 + 8004d30: f2a3 1333 subw r3, r3, #307 @ 0x133 + 8004d34: 781b ldrb r3, [r3, #0] + 8004d36: 2b02 cmp r3, #2 + 8004d38: d101 bne.n 8004d3e <aci_gatt_add_char+0x62> + 8004d3a: 2313 movs r3, #19 + 8004d3c: e002 b.n 8004d44 <aci_gatt_add_char+0x68> + 8004d3e: 2303 movs r3, #3 + 8004d40: e000 b.n 8004d44 <aci_gatt_add_char+0x68> + 8004d42: 2305 movs r3, #5 + 8004d44: f107 0218 add.w r2, r7, #24 + 8004d48: 4413 add r3, r2 + 8004d4a: f8c7 3134 str.w r3, [r7, #308] @ 0x134 + aci_gatt_add_char_rp0 resp; + Osal_MemSet( &resp, 0, sizeof(resp) ); + 8004d4e: f107 0314 add.w r3, r7, #20 + 8004d52: 2203 movs r2, #3 + 8004d54: 2100 movs r1, #0 + 8004d56: 4618 mov r0, r3 + 8004d58: f000 fc35 bl 80055c6 <Osal_MemSet> + int index_input = 0; + 8004d5c: 2300 movs r3, #0 + 8004d5e: f8c7 3130 str.w r3, [r7, #304] @ 0x130 + cp0->Service_Handle = Service_Handle; + 8004d62: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 + 8004d66: f507 72a0 add.w r2, r7, #320 @ 0x140 + 8004d6a: f5a2 7299 sub.w r2, r2, #306 @ 0x132 + 8004d6e: 8812 ldrh r2, [r2, #0] + 8004d70: 801a strh r2, [r3, #0] + index_input += 2; + 8004d72: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130 + 8004d76: 3302 adds r3, #2 + 8004d78: f8c7 3130 str.w r3, [r7, #304] @ 0x130 + cp0->Char_UUID_Type = Char_UUID_Type; + 8004d7c: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 + 8004d80: f507 72a0 add.w r2, r7, #320 @ 0x140 + 8004d84: f2a2 1233 subw r2, r2, #307 @ 0x133 + 8004d88: 7812 ldrb r2, [r2, #0] + 8004d8a: 709a strb r2, [r3, #2] + index_input += 1; + 8004d8c: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130 + 8004d90: 3301 adds r3, #1 + 8004d92: f8c7 3130 str.w r3, [r7, #304] @ 0x130 + /* var_len_data input */ + { + uint8_t size; + switch ( Char_UUID_Type ) + 8004d96: f507 73a0 add.w r3, r7, #320 @ 0x140 + 8004d9a: f2a3 1333 subw r3, r3, #307 @ 0x133 + 8004d9e: 781b ldrb r3, [r3, #0] + 8004da0: 2b01 cmp r3, #1 + 8004da2: d002 beq.n 8004daa <aci_gatt_add_char+0xce> + 8004da4: 2b02 cmp r3, #2 + 8004da6: d004 beq.n 8004db2 <aci_gatt_add_char+0xd6> + 8004da8: e007 b.n 8004dba <aci_gatt_add_char+0xde> + { + case 1: size = 2; break; + 8004daa: 2302 movs r3, #2 + 8004dac: f887 313f strb.w r3, [r7, #319] @ 0x13f + 8004db0: e005 b.n 8004dbe <aci_gatt_add_char+0xe2> + case 2: size = 16; break; + 8004db2: 2310 movs r3, #16 + 8004db4: f887 313f strb.w r3, [r7, #319] @ 0x13f + 8004db8: e001 b.n 8004dbe <aci_gatt_add_char+0xe2> + default: return BLE_STATUS_ERROR; + 8004dba: 2397 movs r3, #151 @ 0x97 + 8004dbc: e091 b.n 8004ee2 <aci_gatt_add_char+0x206> + } + Osal_MemCpy( (void*)&cp0->Char_UUID, (const void*)Char_UUID, size ); + 8004dbe: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 + 8004dc2: 1cd8 adds r0, r3, #3 + 8004dc4: f897 213f ldrb.w r2, [r7, #319] @ 0x13f + 8004dc8: f507 73a0 add.w r3, r7, #320 @ 0x140 + 8004dcc: f5a3 739c sub.w r3, r3, #312 @ 0x138 + 8004dd0: 6819 ldr r1, [r3, #0] + 8004dd2: f000 fbe8 bl 80055a6 <Osal_MemCpy> + index_input += size; + 8004dd6: f897 313f ldrb.w r3, [r7, #319] @ 0x13f + 8004dda: f8d7 2130 ldr.w r2, [r7, #304] @ 0x130 + 8004dde: 4413 add r3, r2 + 8004de0: f8c7 3130 str.w r3, [r7, #304] @ 0x130 + { + cp1->Char_Value_Length = Char_Value_Length; + 8004de4: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 + 8004de8: f507 72a0 add.w r2, r7, #320 @ 0x140 + 8004dec: f5a2 729d sub.w r2, r2, #314 @ 0x13a + 8004df0: 8812 ldrh r2, [r2, #0] + 8004df2: 801a strh r2, [r3, #0] + } + index_input += 2; + 8004df4: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130 + 8004df8: 3302 adds r3, #2 + 8004dfa: f8c7 3130 str.w r3, [r7, #304] @ 0x130 + { + cp1->Char_Properties = Char_Properties; + 8004dfe: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 + 8004e02: f897 2150 ldrb.w r2, [r7, #336] @ 0x150 + 8004e06: 709a strb r2, [r3, #2] + } + index_input += 1; + 8004e08: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130 + 8004e0c: 3301 adds r3, #1 + 8004e0e: f8c7 3130 str.w r3, [r7, #304] @ 0x130 + { + cp1->Security_Permissions = Security_Permissions; + 8004e12: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 + 8004e16: f897 2154 ldrb.w r2, [r7, #340] @ 0x154 + 8004e1a: 70da strb r2, [r3, #3] + } + index_input += 1; + 8004e1c: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130 + 8004e20: 3301 adds r3, #1 + 8004e22: f8c7 3130 str.w r3, [r7, #304] @ 0x130 + { + cp1->GATT_Evt_Mask = GATT_Evt_Mask; + 8004e26: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 + 8004e2a: f897 2158 ldrb.w r2, [r7, #344] @ 0x158 + 8004e2e: 711a strb r2, [r3, #4] + } + index_input += 1; + 8004e30: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130 + 8004e34: 3301 adds r3, #1 + 8004e36: f8c7 3130 str.w r3, [r7, #304] @ 0x130 + { + cp1->Enc_Key_Size = Enc_Key_Size; + 8004e3a: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 + 8004e3e: f897 215c ldrb.w r2, [r7, #348] @ 0x15c + 8004e42: 715a strb r2, [r3, #5] + } + index_input += 1; + 8004e44: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130 + 8004e48: 3301 adds r3, #1 + 8004e4a: f8c7 3130 str.w r3, [r7, #304] @ 0x130 + { + cp1->Is_Variable = Is_Variable; + 8004e4e: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 + 8004e52: f897 2160 ldrb.w r2, [r7, #352] @ 0x160 + 8004e56: 719a strb r2, [r3, #6] + } + index_input += 1; + 8004e58: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130 + 8004e5c: 3301 adds r3, #1 + 8004e5e: f8c7 3130 str.w r3, [r7, #304] @ 0x130 + } + Osal_MemSet( &rq, 0, sizeof(rq) ); + 8004e62: f507 738c add.w r3, r7, #280 @ 0x118 + 8004e66: 2218 movs r2, #24 + 8004e68: 2100 movs r1, #0 + 8004e6a: 4618 mov r0, r3 + 8004e6c: f000 fbab bl 80055c6 <Osal_MemSet> + rq.ogf = 0x3f; + 8004e70: 233f movs r3, #63 @ 0x3f + 8004e72: f8a7 3118 strh.w r3, [r7, #280] @ 0x118 + rq.ocf = 0x104; + 8004e76: f44f 7382 mov.w r3, #260 @ 0x104 + 8004e7a: f8a7 311a strh.w r3, [r7, #282] @ 0x11a + rq.cparam = cmd_buffer; + 8004e7e: f107 0318 add.w r3, r7, #24 + 8004e82: f8c7 3120 str.w r3, [r7, #288] @ 0x120 + rq.clen = index_input; + 8004e86: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130 + 8004e8a: f8c7 3124 str.w r3, [r7, #292] @ 0x124 + rq.rparam = &resp; + 8004e8e: f107 0314 add.w r3, r7, #20 + 8004e92: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + rq.rlen = sizeof(resp); + 8004e96: 2303 movs r3, #3 + 8004e98: f8c7 312c str.w r3, [r7, #300] @ 0x12c + if ( hci_send_req(&rq, FALSE) < 0 ) + 8004e9c: f507 738c add.w r3, r7, #280 @ 0x118 + 8004ea0: 2100 movs r1, #0 + 8004ea2: 4618 mov r0, r3 + 8004ea4: f000 ff1e bl 8005ce4 <hci_send_req> + 8004ea8: 4603 mov r3, r0 + 8004eaa: 2b00 cmp r3, #0 + 8004eac: da01 bge.n 8004eb2 <aci_gatt_add_char+0x1d6> + return BLE_STATUS_TIMEOUT; + 8004eae: 23ff movs r3, #255 @ 0xff + 8004eb0: e017 b.n 8004ee2 <aci_gatt_add_char+0x206> + if ( resp.Status ) + 8004eb2: f507 73a0 add.w r3, r7, #320 @ 0x140 + 8004eb6: f5a3 7396 sub.w r3, r3, #300 @ 0x12c + 8004eba: 781b ldrb r3, [r3, #0] + 8004ebc: 2b00 cmp r3, #0 + 8004ebe: d005 beq.n 8004ecc <aci_gatt_add_char+0x1f0> + return resp.Status; + 8004ec0: f507 73a0 add.w r3, r7, #320 @ 0x140 + 8004ec4: f5a3 7396 sub.w r3, r3, #300 @ 0x12c + 8004ec8: 781b ldrb r3, [r3, #0] + 8004eca: e00a b.n 8004ee2 <aci_gatt_add_char+0x206> + *Char_Handle = resp.Char_Handle; + 8004ecc: f507 73a0 add.w r3, r7, #320 @ 0x140 + 8004ed0: f5a3 7396 sub.w r3, r3, #300 @ 0x12c + 8004ed4: f8b3 3001 ldrh.w r3, [r3, #1] + 8004ed8: b29a uxth r2, r3 + 8004eda: f8d7 3164 ldr.w r3, [r7, #356] @ 0x164 + 8004ede: 801a strh r2, [r3, #0] + return BLE_STATUS_SUCCESS; + 8004ee0: 2300 movs r3, #0 +} + 8004ee2: 4618 mov r0, r3 + 8004ee4: f507 77a2 add.w r7, r7, #324 @ 0x144 + 8004ee8: 46bd mov sp, r7 + 8004eea: bd90 pop {r4, r7, pc} + +08004eec <aci_gatt_update_char_value>: +tBleStatus aci_gatt_update_char_value( uint16_t Service_Handle, + uint16_t Char_Handle, + uint8_t Val_Offset, + uint8_t Char_Value_Length, + const uint8_t* Char_Value ) +{ + 8004eec: b5b0 push {r4, r5, r7, lr} + 8004eee: b0cc sub sp, #304 @ 0x130 + 8004ef0: af00 add r7, sp, #0 + 8004ef2: 4605 mov r5, r0 + 8004ef4: 460c mov r4, r1 + 8004ef6: 4610 mov r0, r2 + 8004ef8: 4619 mov r1, r3 + 8004efa: f507 7398 add.w r3, r7, #304 @ 0x130 + 8004efe: f5a3 7395 sub.w r3, r3, #298 @ 0x12a + 8004f02: 462a mov r2, r5 + 8004f04: 801a strh r2, [r3, #0] + 8004f06: f507 7398 add.w r3, r7, #304 @ 0x130 + 8004f0a: f5a3 7396 sub.w r3, r3, #300 @ 0x12c + 8004f0e: 4622 mov r2, r4 + 8004f10: 801a strh r2, [r3, #0] + 8004f12: f507 7398 add.w r3, r7, #304 @ 0x130 + 8004f16: f2a3 132d subw r3, r3, #301 @ 0x12d + 8004f1a: 4602 mov r2, r0 + 8004f1c: 701a strb r2, [r3, #0] + 8004f1e: f507 7398 add.w r3, r7, #304 @ 0x130 + 8004f22: f5a3 7397 sub.w r3, r3, #302 @ 0x12e + 8004f26: 460a mov r2, r1 + 8004f28: 701a strb r2, [r3, #0] + struct hci_request rq; + uint8_t cmd_buffer[BLE_CMD_MAX_PARAM_LEN]; + aci_gatt_update_char_value_cp0 *cp0 = (aci_gatt_update_char_value_cp0*)(cmd_buffer); + 8004f2a: f107 0310 add.w r3, r7, #16 + 8004f2e: f8c7 312c str.w r3, [r7, #300] @ 0x12c + tBleStatus status = 0; + 8004f32: f507 7398 add.w r3, r7, #304 @ 0x130 + 8004f36: f2a3 1321 subw r3, r3, #289 @ 0x121 + 8004f3a: 2200 movs r2, #0 + 8004f3c: 701a strb r2, [r3, #0] + int index_input = 0; + 8004f3e: 2300 movs r3, #0 + 8004f40: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Service_Handle = Service_Handle; + 8004f44: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 8004f48: f507 7298 add.w r2, r7, #304 @ 0x130 + 8004f4c: f5a2 7295 sub.w r2, r2, #298 @ 0x12a + 8004f50: 8812 ldrh r2, [r2, #0] + 8004f52: 801a strh r2, [r3, #0] + index_input += 2; + 8004f54: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8004f58: 3302 adds r3, #2 + 8004f5a: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Char_Handle = Char_Handle; + 8004f5e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 8004f62: f507 7298 add.w r2, r7, #304 @ 0x130 + 8004f66: f5a2 7296 sub.w r2, r2, #300 @ 0x12c + 8004f6a: 8812 ldrh r2, [r2, #0] + 8004f6c: 805a strh r2, [r3, #2] + index_input += 2; + 8004f6e: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8004f72: 3302 adds r3, #2 + 8004f74: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Val_Offset = Val_Offset; + 8004f78: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 8004f7c: f507 7298 add.w r2, r7, #304 @ 0x130 + 8004f80: f2a2 122d subw r2, r2, #301 @ 0x12d + 8004f84: 7812 ldrb r2, [r2, #0] + 8004f86: 711a strb r2, [r3, #4] + index_input += 1; + 8004f88: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8004f8c: 3301 adds r3, #1 + 8004f8e: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Char_Value_Length = Char_Value_Length; + 8004f92: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 8004f96: f507 7298 add.w r2, r7, #304 @ 0x130 + 8004f9a: f5a2 7297 sub.w r2, r2, #302 @ 0x12e + 8004f9e: 7812 ldrb r2, [r2, #0] + 8004fa0: 715a strb r2, [r3, #5] + index_input += 1; + 8004fa2: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8004fa6: 3301 adds r3, #1 + 8004fa8: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + Osal_MemCpy( (void*)&cp0->Char_Value, (const void*)Char_Value, Char_Value_Length ); + 8004fac: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 8004fb0: 1d98 adds r0, r3, #6 + 8004fb2: f507 7398 add.w r3, r7, #304 @ 0x130 + 8004fb6: f5a3 7397 sub.w r3, r3, #302 @ 0x12e + 8004fba: 781b ldrb r3, [r3, #0] + 8004fbc: 461a mov r2, r3 + 8004fbe: f8d7 1140 ldr.w r1, [r7, #320] @ 0x140 + 8004fc2: f000 faf0 bl 80055a6 <Osal_MemCpy> + index_input += Char_Value_Length; + 8004fc6: f507 7398 add.w r3, r7, #304 @ 0x130 + 8004fca: f5a3 7397 sub.w r3, r3, #302 @ 0x12e + 8004fce: 781b ldrb r3, [r3, #0] + 8004fd0: f8d7 2128 ldr.w r2, [r7, #296] @ 0x128 + 8004fd4: 4413 add r3, r2 + 8004fd6: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + Osal_MemSet( &rq, 0, sizeof(rq) ); + 8004fda: f507 7388 add.w r3, r7, #272 @ 0x110 + 8004fde: 2218 movs r2, #24 + 8004fe0: 2100 movs r1, #0 + 8004fe2: 4618 mov r0, r3 + 8004fe4: f000 faef bl 80055c6 <Osal_MemSet> + rq.ogf = 0x3f; + 8004fe8: 233f movs r3, #63 @ 0x3f + 8004fea: f8a7 3110 strh.w r3, [r7, #272] @ 0x110 + rq.ocf = 0x106; + 8004fee: f44f 7383 mov.w r3, #262 @ 0x106 + 8004ff2: f8a7 3112 strh.w r3, [r7, #274] @ 0x112 + rq.cparam = cmd_buffer; + 8004ff6: f107 0310 add.w r3, r7, #16 + 8004ffa: f8c7 3118 str.w r3, [r7, #280] @ 0x118 + rq.clen = index_input; + 8004ffe: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8005002: f8c7 311c str.w r3, [r7, #284] @ 0x11c + rq.rparam = &status; + 8005006: f107 030f add.w r3, r7, #15 + 800500a: f8c7 3120 str.w r3, [r7, #288] @ 0x120 + rq.rlen = 1; + 800500e: 2301 movs r3, #1 + 8005010: f8c7 3124 str.w r3, [r7, #292] @ 0x124 + if ( hci_send_req(&rq, FALSE) < 0 ) + 8005014: f507 7388 add.w r3, r7, #272 @ 0x110 + 8005018: 2100 movs r1, #0 + 800501a: 4618 mov r0, r3 + 800501c: f000 fe62 bl 8005ce4 <hci_send_req> + 8005020: 4603 mov r3, r0 + 8005022: 2b00 cmp r3, #0 + 8005024: da01 bge.n 800502a <aci_gatt_update_char_value+0x13e> + return BLE_STATUS_TIMEOUT; + 8005026: 23ff movs r3, #255 @ 0xff + 8005028: e004 b.n 8005034 <aci_gatt_update_char_value+0x148> + return status; + 800502a: f507 7398 add.w r3, r7, #304 @ 0x130 + 800502e: f2a3 1321 subw r3, r3, #289 @ 0x121 + 8005032: 781b ldrb r3, [r3, #0] +} + 8005034: 4618 mov r0, r3 + 8005036: f507 7798 add.w r7, r7, #304 @ 0x130 + 800503a: 46bd mov sp, r7 + 800503c: bdb0 pop {r4, r5, r7, pc} + +0800503e <aci_gatt_confirm_indication>: + return BLE_STATUS_TIMEOUT; + return status; +} + +tBleStatus aci_gatt_confirm_indication( uint16_t Connection_Handle ) +{ + 800503e: b580 push {r7, lr} + 8005040: b0cc sub sp, #304 @ 0x130 + 8005042: af00 add r7, sp, #0 + 8005044: 4602 mov r2, r0 + 8005046: f507 7398 add.w r3, r7, #304 @ 0x130 + 800504a: f5a3 7395 sub.w r3, r3, #298 @ 0x12a + 800504e: 801a strh r2, [r3, #0] + struct hci_request rq; + uint8_t cmd_buffer[BLE_CMD_MAX_PARAM_LEN]; + aci_gatt_confirm_indication_cp0 *cp0 = (aci_gatt_confirm_indication_cp0*)(cmd_buffer); + 8005050: f107 0310 add.w r3, r7, #16 + 8005054: f8c7 312c str.w r3, [r7, #300] @ 0x12c + tBleStatus status = 0; + 8005058: f507 7398 add.w r3, r7, #304 @ 0x130 + 800505c: f2a3 1321 subw r3, r3, #289 @ 0x121 + 8005060: 2200 movs r2, #0 + 8005062: 701a strb r2, [r3, #0] + int index_input = 0; + 8005064: 2300 movs r3, #0 + 8005066: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Connection_Handle = Connection_Handle; + 800506a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 800506e: f507 7298 add.w r2, r7, #304 @ 0x130 + 8005072: f5a2 7295 sub.w r2, r2, #298 @ 0x12a + 8005076: 8812 ldrh r2, [r2, #0] + 8005078: 801a strh r2, [r3, #0] + index_input += 2; + 800507a: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 800507e: 3302 adds r3, #2 + 8005080: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + Osal_MemSet( &rq, 0, sizeof(rq) ); + 8005084: f507 7388 add.w r3, r7, #272 @ 0x110 + 8005088: 2218 movs r2, #24 + 800508a: 2100 movs r1, #0 + 800508c: 4618 mov r0, r3 + 800508e: f000 fa9a bl 80055c6 <Osal_MemSet> + rq.ogf = 0x3f; + 8005092: 233f movs r3, #63 @ 0x3f + 8005094: f8a7 3110 strh.w r3, [r7, #272] @ 0x110 + rq.ocf = 0x125; + 8005098: f240 1325 movw r3, #293 @ 0x125 + 800509c: f8a7 3112 strh.w r3, [r7, #274] @ 0x112 + rq.cparam = cmd_buffer; + 80050a0: f107 0310 add.w r3, r7, #16 + 80050a4: f8c7 3118 str.w r3, [r7, #280] @ 0x118 + rq.clen = index_input; + 80050a8: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 80050ac: f8c7 311c str.w r3, [r7, #284] @ 0x11c + rq.rparam = &status; + 80050b0: f107 030f add.w r3, r7, #15 + 80050b4: f8c7 3120 str.w r3, [r7, #288] @ 0x120 + rq.rlen = 1; + 80050b8: 2301 movs r3, #1 + 80050ba: f8c7 3124 str.w r3, [r7, #292] @ 0x124 + if ( hci_send_req(&rq, FALSE) < 0 ) + 80050be: f507 7388 add.w r3, r7, #272 @ 0x110 + 80050c2: 2100 movs r1, #0 + 80050c4: 4618 mov r0, r3 + 80050c6: f000 fe0d bl 8005ce4 <hci_send_req> + 80050ca: 4603 mov r3, r0 + 80050cc: 2b00 cmp r3, #0 + 80050ce: da01 bge.n 80050d4 <aci_gatt_confirm_indication+0x96> + return BLE_STATUS_TIMEOUT; + 80050d0: 23ff movs r3, #255 @ 0xff + 80050d2: e004 b.n 80050de <aci_gatt_confirm_indication+0xa0> + return status; + 80050d4: f507 7398 add.w r3, r7, #304 @ 0x130 + 80050d8: f2a3 1321 subw r3, r3, #289 @ 0x121 + 80050dc: 781b ldrb r3, [r3, #0] +} + 80050de: 4618 mov r0, r3 + 80050e0: f507 7798 add.w r7, r7, #304 @ 0x130 + 80050e4: 46bd mov sp, r7 + 80050e6: bd80 pop {r7, pc} + +080050e8 <aci_hal_write_config_data>: +#include "auto/ble_hal_aci.h" + +tBleStatus aci_hal_write_config_data( uint8_t Offset, + uint8_t Length, + const uint8_t* Value ) +{ + 80050e8: b580 push {r7, lr} + 80050ea: b0cc sub sp, #304 @ 0x130 + 80050ec: af00 add r7, sp, #0 + 80050ee: f507 7398 add.w r3, r7, #304 @ 0x130 + 80050f2: f5a3 7398 sub.w r3, r3, #304 @ 0x130 + 80050f6: 601a str r2, [r3, #0] + 80050f8: f507 7398 add.w r3, r7, #304 @ 0x130 + 80050fc: f2a3 1329 subw r3, r3, #297 @ 0x129 + 8005100: 4602 mov r2, r0 + 8005102: 701a strb r2, [r3, #0] + 8005104: f507 7398 add.w r3, r7, #304 @ 0x130 + 8005108: f5a3 7395 sub.w r3, r3, #298 @ 0x12a + 800510c: 460a mov r2, r1 + 800510e: 701a strb r2, [r3, #0] + struct hci_request rq; + uint8_t cmd_buffer[BLE_CMD_MAX_PARAM_LEN]; + aci_hal_write_config_data_cp0 *cp0 = (aci_hal_write_config_data_cp0*)(cmd_buffer); + 8005110: f107 0310 add.w r3, r7, #16 + 8005114: f8c7 312c str.w r3, [r7, #300] @ 0x12c + tBleStatus status = 0; + 8005118: f507 7398 add.w r3, r7, #304 @ 0x130 + 800511c: f2a3 1321 subw r3, r3, #289 @ 0x121 + 8005120: 2200 movs r2, #0 + 8005122: 701a strb r2, [r3, #0] + int index_input = 0; + 8005124: 2300 movs r3, #0 + 8005126: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Offset = Offset; + 800512a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 800512e: f507 7298 add.w r2, r7, #304 @ 0x130 + 8005132: f2a2 1229 subw r2, r2, #297 @ 0x129 + 8005136: 7812 ldrb r2, [r2, #0] + 8005138: 701a strb r2, [r3, #0] + index_input += 1; + 800513a: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 800513e: 3301 adds r3, #1 + 8005140: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Length = Length; + 8005144: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 8005148: f507 7298 add.w r2, r7, #304 @ 0x130 + 800514c: f5a2 7295 sub.w r2, r2, #298 @ 0x12a + 8005150: 7812 ldrb r2, [r2, #0] + 8005152: 705a strb r2, [r3, #1] + index_input += 1; + 8005154: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8005158: 3301 adds r3, #1 + 800515a: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + Osal_MemCpy( (void*)&cp0->Value, (const void*)Value, Length ); + 800515e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 8005162: 1c98 adds r0, r3, #2 + 8005164: f507 7398 add.w r3, r7, #304 @ 0x130 + 8005168: f5a3 7395 sub.w r3, r3, #298 @ 0x12a + 800516c: 781a ldrb r2, [r3, #0] + 800516e: f507 7398 add.w r3, r7, #304 @ 0x130 + 8005172: f5a3 7398 sub.w r3, r3, #304 @ 0x130 + 8005176: 6819 ldr r1, [r3, #0] + 8005178: f000 fa15 bl 80055a6 <Osal_MemCpy> + index_input += Length; + 800517c: f507 7398 add.w r3, r7, #304 @ 0x130 + 8005180: f5a3 7395 sub.w r3, r3, #298 @ 0x12a + 8005184: 781b ldrb r3, [r3, #0] + 8005186: f8d7 2128 ldr.w r2, [r7, #296] @ 0x128 + 800518a: 4413 add r3, r2 + 800518c: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + Osal_MemSet( &rq, 0, sizeof(rq) ); + 8005190: f507 7388 add.w r3, r7, #272 @ 0x110 + 8005194: 2218 movs r2, #24 + 8005196: 2100 movs r1, #0 + 8005198: 4618 mov r0, r3 + 800519a: f000 fa14 bl 80055c6 <Osal_MemSet> + rq.ogf = 0x3f; + 800519e: 233f movs r3, #63 @ 0x3f + 80051a0: f8a7 3110 strh.w r3, [r7, #272] @ 0x110 + rq.ocf = 0x00c; + 80051a4: 230c movs r3, #12 + 80051a6: f8a7 3112 strh.w r3, [r7, #274] @ 0x112 + rq.cparam = cmd_buffer; + 80051aa: f107 0310 add.w r3, r7, #16 + 80051ae: f8c7 3118 str.w r3, [r7, #280] @ 0x118 + rq.clen = index_input; + 80051b2: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 80051b6: f8c7 311c str.w r3, [r7, #284] @ 0x11c + rq.rparam = &status; + 80051ba: f107 030f add.w r3, r7, #15 + 80051be: f8c7 3120 str.w r3, [r7, #288] @ 0x120 + rq.rlen = 1; + 80051c2: 2301 movs r3, #1 + 80051c4: f8c7 3124 str.w r3, [r7, #292] @ 0x124 + if ( hci_send_req(&rq, FALSE) < 0 ) + 80051c8: f507 7388 add.w r3, r7, #272 @ 0x110 + 80051cc: 2100 movs r1, #0 + 80051ce: 4618 mov r0, r3 + 80051d0: f000 fd88 bl 8005ce4 <hci_send_req> + 80051d4: 4603 mov r3, r0 + 80051d6: 2b00 cmp r3, #0 + 80051d8: da01 bge.n 80051de <aci_hal_write_config_data+0xf6> + return BLE_STATUS_TIMEOUT; + 80051da: 23ff movs r3, #255 @ 0xff + 80051dc: e004 b.n 80051e8 <aci_hal_write_config_data+0x100> + return status; + 80051de: f507 7398 add.w r3, r7, #304 @ 0x130 + 80051e2: f2a3 1321 subw r3, r3, #289 @ 0x121 + 80051e6: 781b ldrb r3, [r3, #0] +} + 80051e8: 4618 mov r0, r3 + 80051ea: f507 7798 add.w r7, r7, #304 @ 0x130 + 80051ee: 46bd mov sp, r7 + 80051f0: bd80 pop {r7, pc} + +080051f2 <aci_hal_set_tx_power_level>: + return BLE_STATUS_SUCCESS; +} + +tBleStatus aci_hal_set_tx_power_level( uint8_t En_High_Power, + uint8_t PA_Level ) +{ + 80051f2: b580 push {r7, lr} + 80051f4: b0cc sub sp, #304 @ 0x130 + 80051f6: af00 add r7, sp, #0 + 80051f8: 4602 mov r2, r0 + 80051fa: f507 7398 add.w r3, r7, #304 @ 0x130 + 80051fe: f2a3 1329 subw r3, r3, #297 @ 0x129 + 8005202: 701a strb r2, [r3, #0] + 8005204: f507 7398 add.w r3, r7, #304 @ 0x130 + 8005208: f5a3 7395 sub.w r3, r3, #298 @ 0x12a + 800520c: 460a mov r2, r1 + 800520e: 701a strb r2, [r3, #0] + struct hci_request rq; + uint8_t cmd_buffer[BLE_CMD_MAX_PARAM_LEN]; + aci_hal_set_tx_power_level_cp0 *cp0 = (aci_hal_set_tx_power_level_cp0*)(cmd_buffer); + 8005210: f107 0310 add.w r3, r7, #16 + 8005214: f8c7 312c str.w r3, [r7, #300] @ 0x12c + tBleStatus status = 0; + 8005218: f507 7398 add.w r3, r7, #304 @ 0x130 + 800521c: f2a3 1321 subw r3, r3, #289 @ 0x121 + 8005220: 2200 movs r2, #0 + 8005222: 701a strb r2, [r3, #0] + int index_input = 0; + 8005224: 2300 movs r3, #0 + 8005226: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->En_High_Power = En_High_Power; + 800522a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 800522e: f507 7298 add.w r2, r7, #304 @ 0x130 + 8005232: f2a2 1229 subw r2, r2, #297 @ 0x129 + 8005236: 7812 ldrb r2, [r2, #0] + 8005238: 701a strb r2, [r3, #0] + index_input += 1; + 800523a: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 800523e: 3301 adds r3, #1 + 8005240: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->PA_Level = PA_Level; + 8005244: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 8005248: f507 7298 add.w r2, r7, #304 @ 0x130 + 800524c: f5a2 7295 sub.w r2, r2, #298 @ 0x12a + 8005250: 7812 ldrb r2, [r2, #0] + 8005252: 705a strb r2, [r3, #1] + index_input += 1; + 8005254: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8005258: 3301 adds r3, #1 + 800525a: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + Osal_MemSet( &rq, 0, sizeof(rq) ); + 800525e: f507 7388 add.w r3, r7, #272 @ 0x110 + 8005262: 2218 movs r2, #24 + 8005264: 2100 movs r1, #0 + 8005266: 4618 mov r0, r3 + 8005268: f000 f9ad bl 80055c6 <Osal_MemSet> + rq.ogf = 0x3f; + 800526c: 233f movs r3, #63 @ 0x3f + 800526e: f8a7 3110 strh.w r3, [r7, #272] @ 0x110 + rq.ocf = 0x00f; + 8005272: 230f movs r3, #15 + 8005274: f8a7 3112 strh.w r3, [r7, #274] @ 0x112 + rq.cparam = cmd_buffer; + 8005278: f107 0310 add.w r3, r7, #16 + 800527c: f8c7 3118 str.w r3, [r7, #280] @ 0x118 + rq.clen = index_input; + 8005280: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8005284: f8c7 311c str.w r3, [r7, #284] @ 0x11c + rq.rparam = &status; + 8005288: f107 030f add.w r3, r7, #15 + 800528c: f8c7 3120 str.w r3, [r7, #288] @ 0x120 + rq.rlen = 1; + 8005290: 2301 movs r3, #1 + 8005292: f8c7 3124 str.w r3, [r7, #292] @ 0x124 + if ( hci_send_req(&rq, FALSE) < 0 ) + 8005296: f507 7388 add.w r3, r7, #272 @ 0x110 + 800529a: 2100 movs r1, #0 + 800529c: 4618 mov r0, r3 + 800529e: f000 fd21 bl 8005ce4 <hci_send_req> + 80052a2: 4603 mov r3, r0 + 80052a4: 2b00 cmp r3, #0 + 80052a6: da01 bge.n 80052ac <aci_hal_set_tx_power_level+0xba> + return BLE_STATUS_TIMEOUT; + 80052a8: 23ff movs r3, #255 @ 0xff + 80052aa: e004 b.n 80052b6 <aci_hal_set_tx_power_level+0xc4> + return status; + 80052ac: f507 7398 add.w r3, r7, #304 @ 0x130 + 80052b0: f2a3 1321 subw r3, r3, #289 @ 0x121 + 80052b4: 781b ldrb r3, [r3, #0] +} + 80052b6: 4618 mov r0, r3 + 80052b8: f507 7798 add.w r7, r7, #304 @ 0x130 + 80052bc: 46bd mov sp, r7 + 80052be: bd80 pop {r7, pc} + +080052c0 <aci_hal_set_radio_activity_mask>: + Osal_MemCpy( (void*)Link_Connection_Handle, (const void*)resp.Link_Connection_Handle, 16 ); + return BLE_STATUS_SUCCESS; +} + +tBleStatus aci_hal_set_radio_activity_mask( uint16_t Radio_Activity_Mask ) +{ + 80052c0: b580 push {r7, lr} + 80052c2: b0cc sub sp, #304 @ 0x130 + 80052c4: af00 add r7, sp, #0 + 80052c6: 4602 mov r2, r0 + 80052c8: f507 7398 add.w r3, r7, #304 @ 0x130 + 80052cc: f5a3 7395 sub.w r3, r3, #298 @ 0x12a + 80052d0: 801a strh r2, [r3, #0] + struct hci_request rq; + uint8_t cmd_buffer[BLE_CMD_MAX_PARAM_LEN]; + aci_hal_set_radio_activity_mask_cp0 *cp0 = (aci_hal_set_radio_activity_mask_cp0*)(cmd_buffer); + 80052d2: f107 0310 add.w r3, r7, #16 + 80052d6: f8c7 312c str.w r3, [r7, #300] @ 0x12c + tBleStatus status = 0; + 80052da: f507 7398 add.w r3, r7, #304 @ 0x130 + 80052de: f2a3 1321 subw r3, r3, #289 @ 0x121 + 80052e2: 2200 movs r2, #0 + 80052e4: 701a strb r2, [r3, #0] + int index_input = 0; + 80052e6: 2300 movs r3, #0 + 80052e8: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->Radio_Activity_Mask = Radio_Activity_Mask; + 80052ec: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 80052f0: f507 7298 add.w r2, r7, #304 @ 0x130 + 80052f4: f5a2 7295 sub.w r2, r2, #298 @ 0x12a + 80052f8: 8812 ldrh r2, [r2, #0] + 80052fa: 801a strh r2, [r3, #0] + index_input += 2; + 80052fc: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8005300: 3302 adds r3, #2 + 8005302: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + Osal_MemSet( &rq, 0, sizeof(rq) ); + 8005306: f507 7388 add.w r3, r7, #272 @ 0x110 + 800530a: 2218 movs r2, #24 + 800530c: 2100 movs r1, #0 + 800530e: 4618 mov r0, r3 + 8005310: f000 f959 bl 80055c6 <Osal_MemSet> + rq.ogf = 0x3f; + 8005314: 233f movs r3, #63 @ 0x3f + 8005316: f8a7 3110 strh.w r3, [r7, #272] @ 0x110 + rq.ocf = 0x018; + 800531a: 2318 movs r3, #24 + 800531c: f8a7 3112 strh.w r3, [r7, #274] @ 0x112 + rq.cparam = cmd_buffer; + 8005320: f107 0310 add.w r3, r7, #16 + 8005324: f8c7 3118 str.w r3, [r7, #280] @ 0x118 + rq.clen = index_input; + 8005328: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 800532c: f8c7 311c str.w r3, [r7, #284] @ 0x11c + rq.rparam = &status; + 8005330: f107 030f add.w r3, r7, #15 + 8005334: f8c7 3120 str.w r3, [r7, #288] @ 0x120 + rq.rlen = 1; + 8005338: 2301 movs r3, #1 + 800533a: f8c7 3124 str.w r3, [r7, #292] @ 0x124 + if ( hci_send_req(&rq, FALSE) < 0 ) + 800533e: f507 7388 add.w r3, r7, #272 @ 0x110 + 8005342: 2100 movs r1, #0 + 8005344: 4618 mov r0, r3 + 8005346: f000 fccd bl 8005ce4 <hci_send_req> + 800534a: 4603 mov r3, r0 + 800534c: 2b00 cmp r3, #0 + 800534e: da01 bge.n 8005354 <aci_hal_set_radio_activity_mask+0x94> + return BLE_STATUS_TIMEOUT; + 8005350: 23ff movs r3, #255 @ 0xff + 8005352: e004 b.n 800535e <aci_hal_set_radio_activity_mask+0x9e> + return status; + 8005354: f507 7398 add.w r3, r7, #304 @ 0x130 + 8005358: f2a3 1321 subw r3, r3, #289 @ 0x121 + 800535c: 781b ldrb r3, [r3, #0] +} + 800535e: 4618 mov r0, r3 + 8005360: f507 7798 add.w r7, r7, #304 @ 0x130 + 8005364: 46bd mov sp, r7 + 8005366: bd80 pop {r7, pc} + +08005368 <hci_reset>: + return BLE_STATUS_TIMEOUT; + return status; +} + +tBleStatus hci_reset( void ) +{ + 8005368: b580 push {r7, lr} + 800536a: b088 sub sp, #32 + 800536c: af00 add r7, sp, #0 + struct hci_request rq; + tBleStatus status = 0; + 800536e: 2300 movs r3, #0 + 8005370: 71fb strb r3, [r7, #7] + Osal_MemSet( &rq, 0, sizeof(rq) ); + 8005372: f107 0308 add.w r3, r7, #8 + 8005376: 2218 movs r2, #24 + 8005378: 2100 movs r1, #0 + 800537a: 4618 mov r0, r3 + 800537c: f000 f923 bl 80055c6 <Osal_MemSet> + rq.ogf = 0x03; + 8005380: 2303 movs r3, #3 + 8005382: 813b strh r3, [r7, #8] + rq.ocf = 0x003; + 8005384: 2303 movs r3, #3 + 8005386: 817b strh r3, [r7, #10] + rq.rparam = &status; + 8005388: 1dfb adds r3, r7, #7 + 800538a: 61bb str r3, [r7, #24] + rq.rlen = 1; + 800538c: 2301 movs r3, #1 + 800538e: 61fb str r3, [r7, #28] + if ( hci_send_req(&rq, FALSE) < 0 ) + 8005390: f107 0308 add.w r3, r7, #8 + 8005394: 2100 movs r1, #0 + 8005396: 4618 mov r0, r3 + 8005398: f000 fca4 bl 8005ce4 <hci_send_req> + 800539c: 4603 mov r3, r0 + 800539e: 2b00 cmp r3, #0 + 80053a0: da01 bge.n 80053a6 <hci_reset+0x3e> + return BLE_STATUS_TIMEOUT; + 80053a2: 23ff movs r3, #255 @ 0xff + 80053a4: e000 b.n 80053a8 <hci_reset+0x40> + return status; + 80053a6: 79fb ldrb r3, [r7, #7] +} + 80053a8: 4618 mov r0, r3 + 80053aa: 3720 adds r7, #32 + 80053ac: 46bd mov sp, r7 + 80053ae: bd80 pop {r7, pc} + +080053b0 <hci_le_read_phy>: +} + +tBleStatus hci_le_read_phy( uint16_t Connection_Handle, + uint8_t* TX_PHY, + uint8_t* RX_PHY ) +{ + 80053b0: b580 push {r7, lr} + 80053b2: b0ce sub sp, #312 @ 0x138 + 80053b4: af00 add r7, sp, #0 + 80053b6: f507 739c add.w r3, r7, #312 @ 0x138 + 80053ba: f5a3 7398 sub.w r3, r3, #304 @ 0x130 + 80053be: 6019 str r1, [r3, #0] + 80053c0: f507 739c add.w r3, r7, #312 @ 0x138 + 80053c4: f5a3 739a sub.w r3, r3, #308 @ 0x134 + 80053c8: 601a str r2, [r3, #0] + 80053ca: f507 739c add.w r3, r7, #312 @ 0x138 + 80053ce: f5a3 7395 sub.w r3, r3, #298 @ 0x12a + 80053d2: 4602 mov r2, r0 + 80053d4: 801a strh r2, [r3, #0] + struct hci_request rq; + uint8_t cmd_buffer[BLE_CMD_MAX_PARAM_LEN]; + hci_le_read_phy_cp0 *cp0 = (hci_le_read_phy_cp0*)(cmd_buffer); + 80053d6: f107 0318 add.w r3, r7, #24 + 80053da: f8c7 3134 str.w r3, [r7, #308] @ 0x134 + hci_le_read_phy_rp0 resp; + Osal_MemSet( &resp, 0, sizeof(resp) ); + 80053de: f107 0310 add.w r3, r7, #16 + 80053e2: 2205 movs r2, #5 + 80053e4: 2100 movs r1, #0 + 80053e6: 4618 mov r0, r3 + 80053e8: f000 f8ed bl 80055c6 <Osal_MemSet> + int index_input = 0; + 80053ec: 2300 movs r3, #0 + 80053ee: f8c7 3130 str.w r3, [r7, #304] @ 0x130 + cp0->Connection_Handle = Connection_Handle; + 80053f2: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 + 80053f6: f507 729c add.w r2, r7, #312 @ 0x138 + 80053fa: f5a2 7295 sub.w r2, r2, #298 @ 0x12a + 80053fe: 8812 ldrh r2, [r2, #0] + 8005400: 801a strh r2, [r3, #0] + index_input += 2; + 8005402: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130 + 8005406: 3302 adds r3, #2 + 8005408: f8c7 3130 str.w r3, [r7, #304] @ 0x130 + Osal_MemSet( &rq, 0, sizeof(rq) ); + 800540c: f507 738c add.w r3, r7, #280 @ 0x118 + 8005410: 2218 movs r2, #24 + 8005412: 2100 movs r1, #0 + 8005414: 4618 mov r0, r3 + 8005416: f000 f8d6 bl 80055c6 <Osal_MemSet> + rq.ogf = 0x08; + 800541a: 2308 movs r3, #8 + 800541c: f8a7 3118 strh.w r3, [r7, #280] @ 0x118 + rq.ocf = 0x030; + 8005420: 2330 movs r3, #48 @ 0x30 + 8005422: f8a7 311a strh.w r3, [r7, #282] @ 0x11a + rq.cparam = cmd_buffer; + 8005426: f107 0318 add.w r3, r7, #24 + 800542a: f8c7 3120 str.w r3, [r7, #288] @ 0x120 + rq.clen = index_input; + 800542e: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130 + 8005432: f8c7 3124 str.w r3, [r7, #292] @ 0x124 + rq.rparam = &resp; + 8005436: f107 0310 add.w r3, r7, #16 + 800543a: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + rq.rlen = sizeof(resp); + 800543e: 2305 movs r3, #5 + 8005440: f8c7 312c str.w r3, [r7, #300] @ 0x12c + if ( hci_send_req(&rq, FALSE) < 0 ) + 8005444: f507 738c add.w r3, r7, #280 @ 0x118 + 8005448: 2100 movs r1, #0 + 800544a: 4618 mov r0, r3 + 800544c: f000 fc4a bl 8005ce4 <hci_send_req> + 8005450: 4603 mov r3, r0 + 8005452: 2b00 cmp r3, #0 + 8005454: da01 bge.n 800545a <hci_le_read_phy+0xaa> + return BLE_STATUS_TIMEOUT; + 8005456: 23ff movs r3, #255 @ 0xff + 8005458: e023 b.n 80054a2 <hci_le_read_phy+0xf2> + if ( resp.Status ) + 800545a: f507 739c add.w r3, r7, #312 @ 0x138 + 800545e: f5a3 7394 sub.w r3, r3, #296 @ 0x128 + 8005462: 781b ldrb r3, [r3, #0] + 8005464: 2b00 cmp r3, #0 + 8005466: d005 beq.n 8005474 <hci_le_read_phy+0xc4> + return resp.Status; + 8005468: f507 739c add.w r3, r7, #312 @ 0x138 + 800546c: f5a3 7394 sub.w r3, r3, #296 @ 0x128 + 8005470: 781b ldrb r3, [r3, #0] + 8005472: e016 b.n 80054a2 <hci_le_read_phy+0xf2> + *TX_PHY = resp.TX_PHY; + 8005474: f507 739c add.w r3, r7, #312 @ 0x138 + 8005478: f5a3 7394 sub.w r3, r3, #296 @ 0x128 + 800547c: 78da ldrb r2, [r3, #3] + 800547e: f507 739c add.w r3, r7, #312 @ 0x138 + 8005482: f5a3 7398 sub.w r3, r3, #304 @ 0x130 + 8005486: 681b ldr r3, [r3, #0] + 8005488: 701a strb r2, [r3, #0] + *RX_PHY = resp.RX_PHY; + 800548a: f507 739c add.w r3, r7, #312 @ 0x138 + 800548e: f5a3 7394 sub.w r3, r3, #296 @ 0x128 + 8005492: 791a ldrb r2, [r3, #4] + 8005494: f507 739c add.w r3, r7, #312 @ 0x138 + 8005498: f5a3 739a sub.w r3, r3, #308 @ 0x134 + 800549c: 681b ldr r3, [r3, #0] + 800549e: 701a strb r2, [r3, #0] + return BLE_STATUS_SUCCESS; + 80054a0: 2300 movs r3, #0 +} + 80054a2: 4618 mov r0, r3 + 80054a4: f507 779c add.w r7, r7, #312 @ 0x138 + 80054a8: 46bd mov sp, r7 + 80054aa: bd80 pop {r7, pc} + +080054ac <hci_le_set_default_phy>: + +tBleStatus hci_le_set_default_phy( uint8_t ALL_PHYS, + uint8_t TX_PHYS, + uint8_t RX_PHYS ) +{ + 80054ac: b590 push {r4, r7, lr} + 80054ae: b0cd sub sp, #308 @ 0x134 + 80054b0: af00 add r7, sp, #0 + 80054b2: 4604 mov r4, r0 + 80054b4: 4608 mov r0, r1 + 80054b6: 4611 mov r1, r2 + 80054b8: f507 7398 add.w r3, r7, #304 @ 0x130 + 80054bc: f2a3 1329 subw r3, r3, #297 @ 0x129 + 80054c0: 4622 mov r2, r4 + 80054c2: 701a strb r2, [r3, #0] + 80054c4: f507 7398 add.w r3, r7, #304 @ 0x130 + 80054c8: f5a3 7395 sub.w r3, r3, #298 @ 0x12a + 80054cc: 4602 mov r2, r0 + 80054ce: 701a strb r2, [r3, #0] + 80054d0: f507 7398 add.w r3, r7, #304 @ 0x130 + 80054d4: f2a3 132b subw r3, r3, #299 @ 0x12b + 80054d8: 460a mov r2, r1 + 80054da: 701a strb r2, [r3, #0] + struct hci_request rq; + uint8_t cmd_buffer[BLE_CMD_MAX_PARAM_LEN]; + hci_le_set_default_phy_cp0 *cp0 = (hci_le_set_default_phy_cp0*)(cmd_buffer); + 80054dc: f107 0310 add.w r3, r7, #16 + 80054e0: f8c7 312c str.w r3, [r7, #300] @ 0x12c + tBleStatus status = 0; + 80054e4: f507 7398 add.w r3, r7, #304 @ 0x130 + 80054e8: f2a3 1321 subw r3, r3, #289 @ 0x121 + 80054ec: 2200 movs r2, #0 + 80054ee: 701a strb r2, [r3, #0] + int index_input = 0; + 80054f0: 2300 movs r3, #0 + 80054f2: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->ALL_PHYS = ALL_PHYS; + 80054f6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 80054fa: f507 7298 add.w r2, r7, #304 @ 0x130 + 80054fe: f2a2 1229 subw r2, r2, #297 @ 0x129 + 8005502: 7812 ldrb r2, [r2, #0] + 8005504: 701a strb r2, [r3, #0] + index_input += 1; + 8005506: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 800550a: 3301 adds r3, #1 + 800550c: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->TX_PHYS = TX_PHYS; + 8005510: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 8005514: f507 7298 add.w r2, r7, #304 @ 0x130 + 8005518: f5a2 7295 sub.w r2, r2, #298 @ 0x12a + 800551c: 7812 ldrb r2, [r2, #0] + 800551e: 705a strb r2, [r3, #1] + index_input += 1; + 8005520: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 8005524: 3301 adds r3, #1 + 8005526: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + cp0->RX_PHYS = RX_PHYS; + 800552a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c + 800552e: f507 7298 add.w r2, r7, #304 @ 0x130 + 8005532: f2a2 122b subw r2, r2, #299 @ 0x12b + 8005536: 7812 ldrb r2, [r2, #0] + 8005538: 709a strb r2, [r3, #2] + index_input += 1; + 800553a: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 800553e: 3301 adds r3, #1 + 8005540: f8c7 3128 str.w r3, [r7, #296] @ 0x128 + Osal_MemSet( &rq, 0, sizeof(rq) ); + 8005544: f507 7388 add.w r3, r7, #272 @ 0x110 + 8005548: 2218 movs r2, #24 + 800554a: 2100 movs r1, #0 + 800554c: 4618 mov r0, r3 + 800554e: f000 f83a bl 80055c6 <Osal_MemSet> + rq.ogf = 0x08; + 8005552: 2308 movs r3, #8 + 8005554: f8a7 3110 strh.w r3, [r7, #272] @ 0x110 + rq.ocf = 0x031; + 8005558: 2331 movs r3, #49 @ 0x31 + 800555a: f8a7 3112 strh.w r3, [r7, #274] @ 0x112 + rq.cparam = cmd_buffer; + 800555e: f107 0310 add.w r3, r7, #16 + 8005562: f8c7 3118 str.w r3, [r7, #280] @ 0x118 + rq.clen = index_input; + 8005566: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128 + 800556a: f8c7 311c str.w r3, [r7, #284] @ 0x11c + rq.rparam = &status; + 800556e: f107 030f add.w r3, r7, #15 + 8005572: f8c7 3120 str.w r3, [r7, #288] @ 0x120 + rq.rlen = 1; + 8005576: 2301 movs r3, #1 + 8005578: f8c7 3124 str.w r3, [r7, #292] @ 0x124 + if ( hci_send_req(&rq, FALSE) < 0 ) + 800557c: f507 7388 add.w r3, r7, #272 @ 0x110 + 8005580: 2100 movs r1, #0 + 8005582: 4618 mov r0, r3 + 8005584: f000 fbae bl 8005ce4 <hci_send_req> + 8005588: 4603 mov r3, r0 + 800558a: 2b00 cmp r3, #0 + 800558c: da01 bge.n 8005592 <hci_le_set_default_phy+0xe6> + return BLE_STATUS_TIMEOUT; + 800558e: 23ff movs r3, #255 @ 0xff + 8005590: e004 b.n 800559c <hci_le_set_default_phy+0xf0> + return status; + 8005592: f507 7398 add.w r3, r7, #304 @ 0x130 + 8005596: f2a3 1321 subw r3, r3, #289 @ 0x121 + 800559a: 781b ldrb r3, [r3, #0] +} + 800559c: 4618 mov r0, r3 + 800559e: f507 779a add.w r7, r7, #308 @ 0x134 + 80055a2: 46bd mov sp, r7 + 80055a4: bd90 pop {r4, r7, pc} + +080055a6 <Osal_MemCpy>: + * Osal_MemCpy + * + */ + +void* Osal_MemCpy( void *dest, const void *src, unsigned int size ) +{ + 80055a6: b580 push {r7, lr} + 80055a8: b084 sub sp, #16 + 80055aa: af00 add r7, sp, #0 + 80055ac: 60f8 str r0, [r7, #12] + 80055ae: 60b9 str r1, [r7, #8] + 80055b0: 607a str r2, [r7, #4] + return memcpy( dest, src, size ); + 80055b2: 687a ldr r2, [r7, #4] + 80055b4: 68b9 ldr r1, [r7, #8] + 80055b6: 68f8 ldr r0, [r7, #12] + 80055b8: f002 fae2 bl 8007b80 <memcpy> + 80055bc: 4603 mov r3, r0 +} + 80055be: 4618 mov r0, r3 + 80055c0: 3710 adds r7, #16 + 80055c2: 46bd mov sp, r7 + 80055c4: bd80 pop {r7, pc} + +080055c6 <Osal_MemSet>: + * Osal_MemSet + * + */ + +void* Osal_MemSet( void *ptr, int value, unsigned int size ) +{ + 80055c6: b580 push {r7, lr} + 80055c8: b084 sub sp, #16 + 80055ca: af00 add r7, sp, #0 + 80055cc: 60f8 str r0, [r7, #12] + 80055ce: 60b9 str r1, [r7, #8] + 80055d0: 607a str r2, [r7, #4] + return memset( ptr, value, size ); + 80055d2: 687a ldr r2, [r7, #4] + 80055d4: 68b9 ldr r1, [r7, #8] + 80055d6: 68f8 ldr r0, [r7, #12] + 80055d8: f002 faa5 bl 8007b26 <memset> + 80055dc: 4603 mov r3, r0 +} + 80055de: 4618 mov r0, r3 + 80055e0: 3710 adds r7, #16 + 80055e2: 46bd mov sp, r7 + 80055e4: bd80 pop {r7, pc} + ... + +080055e8 <PeerToPeer_Event_Handler>: + * @brief Event handler + * @param Event: Address of the buffer holding the Event + * @retval Ack: Return whether the Event has been managed or not + */ +static SVCCTL_EvtAckStatus_t PeerToPeer_Event_Handler(void *Event) +{ + 80055e8: b580 push {r7, lr} + 80055ea: b08a sub sp, #40 @ 0x28 + 80055ec: af00 add r7, sp, #0 + 80055ee: 6078 str r0, [r7, #4] + hci_event_pckt *event_pckt; + evt_blecore_aci *blecore_evt; + aci_gatt_attribute_modified_event_rp0 * attribute_modified; + P2PS_STM_App_Notification_evt_t Notification; + + return_value = SVCCTL_EvtNotAck; + 80055f0: 2300 movs r3, #0 + 80055f2: f887 3027 strb.w r3, [r7, #39] @ 0x27 + event_pckt = (hci_event_pckt *)(((hci_uart_pckt*)Event)->data); + 80055f6: 687b ldr r3, [r7, #4] + 80055f8: 3301 adds r3, #1 + 80055fa: 623b str r3, [r7, #32] + + switch(event_pckt->evt) + 80055fc: 6a3b ldr r3, [r7, #32] + 80055fe: 781b ldrb r3, [r3, #0] + 8005600: 2bff cmp r3, #255 @ 0xff + 8005602: d14c bne.n 800569e <PeerToPeer_Event_Handler+0xb6> + { + case HCI_VENDOR_SPECIFIC_DEBUG_EVT_CODE: + { + blecore_evt = (evt_blecore_aci*)event_pckt->data; + 8005604: 6a3b ldr r3, [r7, #32] + 8005606: 3302 adds r3, #2 + 8005608: 61fb str r3, [r7, #28] + switch(blecore_evt->ecode) + 800560a: 69fb ldr r3, [r7, #28] + 800560c: 881b ldrh r3, [r3, #0] + 800560e: b29b uxth r3, r3 + 8005610: 461a mov r2, r3 + 8005612: f640 4301 movw r3, #3073 @ 0xc01 + 8005616: 429a cmp r2, r3 + 8005618: d13d bne.n 8005696 <PeerToPeer_Event_Handler+0xae> + { + case ACI_GATT_ATTRIBUTE_MODIFIED_VSEVT_CODE: + { + attribute_modified = (aci_gatt_attribute_modified_event_rp0*)blecore_evt->data; + 800561a: 69fb ldr r3, [r7, #28] + 800561c: 3302 adds r3, #2 + 800561e: 61bb str r3, [r7, #24] + if(attribute_modified->Attr_Handle == (aPeerToPeerContext.P2PNotifyServerToClientCharHdle + 2)) + 8005620: 69bb ldr r3, [r7, #24] + 8005622: 885b ldrh r3, [r3, #2] + 8005624: b29b uxth r3, r3 + 8005626: 461a mov r2, r3 + 8005628: 4b20 ldr r3, [pc, #128] @ (80056ac <PeerToPeer_Event_Handler+0xc4>) + 800562a: 889b ldrh r3, [r3, #4] + 800562c: 3302 adds r3, #2 + 800562e: 429a cmp r2, r3 + 8005630: d118 bne.n 8005664 <PeerToPeer_Event_Handler+0x7c> + { + /** + * Descriptor handle + */ + return_value = SVCCTL_EvtAckFlowEnable; + 8005632: 2301 movs r3, #1 + 8005634: f887 3027 strb.w r3, [r7, #39] @ 0x27 + /** + * Notify to application + */ + if(attribute_modified->Attr_Data[0] & COMSVC_Notification) + 8005638: 69bb ldr r3, [r7, #24] + 800563a: 7a1b ldrb r3, [r3, #8] + 800563c: f003 0301 and.w r3, r3, #1 + 8005640: 2b00 cmp r3, #0 + 8005642: d007 beq.n 8005654 <PeerToPeer_Event_Handler+0x6c> + { + Notification.P2P_Evt_Opcode = P2PS_STM__NOTIFY_ENABLED_EVT; + 8005644: 2300 movs r3, #0 + 8005646: 723b strb r3, [r7, #8] + P2PS_STM_App_Notification(&Notification); + 8005648: f107 0308 add.w r3, r7, #8 + 800564c: 4618 mov r0, r3 + 800564e: f001 fc5f bl 8006f10 <P2PS_STM_App_Notification> + Notification.DataTransfered.pPayload=attribute_modified->Attr_Data; + P2PS_STM_App_Notification(&Notification); + } +#endif + } + break; + 8005652: e022 b.n 800569a <PeerToPeer_Event_Handler+0xb2> + Notification.P2P_Evt_Opcode = P2PS_STM_NOTIFY_DISABLED_EVT; + 8005654: 2301 movs r3, #1 + 8005656: 723b strb r3, [r7, #8] + P2PS_STM_App_Notification(&Notification); + 8005658: f107 0308 add.w r3, r7, #8 + 800565c: 4618 mov r0, r3 + 800565e: f001 fc57 bl 8006f10 <P2PS_STM_App_Notification> + break; + 8005662: e01a b.n 800569a <PeerToPeer_Event_Handler+0xb2> + else if(attribute_modified->Attr_Handle == (aPeerToPeerContext.P2PWriteClientToServerCharHdle + 1)) + 8005664: 69bb ldr r3, [r7, #24] + 8005666: 885b ldrh r3, [r3, #2] + 8005668: b29b uxth r3, r3 + 800566a: 461a mov r2, r3 + 800566c: 4b0f ldr r3, [pc, #60] @ (80056ac <PeerToPeer_Event_Handler+0xc4>) + 800566e: 885b ldrh r3, [r3, #2] + 8005670: 3301 adds r3, #1 + 8005672: 429a cmp r2, r3 + 8005674: d111 bne.n 800569a <PeerToPeer_Event_Handler+0xb2> + Notification.P2P_Evt_Opcode = P2PS_STM_WRITE_EVT; + 8005676: 2303 movs r3, #3 + 8005678: 723b strb r3, [r7, #8] + Notification.DataTransfered.Length=attribute_modified->Attr_Data_Length; + 800567a: 69bb ldr r3, [r7, #24] + 800567c: 88db ldrh r3, [r3, #6] + 800567e: b29b uxth r3, r3 + 8005680: b2db uxtb r3, r3 + 8005682: 743b strb r3, [r7, #16] + Notification.DataTransfered.pPayload=attribute_modified->Attr_Data; + 8005684: 69bb ldr r3, [r7, #24] + 8005686: 3308 adds r3, #8 + 8005688: 60fb str r3, [r7, #12] + P2PS_STM_App_Notification(&Notification); + 800568a: f107 0308 add.w r3, r7, #8 + 800568e: 4618 mov r0, r3 + 8005690: f001 fc3e bl 8006f10 <P2PS_STM_App_Notification> + break; + 8005694: e001 b.n 800569a <PeerToPeer_Event_Handler+0xb2> + + default: + break; + 8005696: bf00 nop + 8005698: e002 b.n 80056a0 <PeerToPeer_Event_Handler+0xb8> + break; + 800569a: bf00 nop + } + } + break; /* HCI_HCI_VENDOR_SPECIFIC_DEBUG_EVT_CODE_SPECIFIC */ + 800569c: e000 b.n 80056a0 <PeerToPeer_Event_Handler+0xb8> + + default: + break; + 800569e: bf00 nop + } + + return(return_value); + 80056a0: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 +}/* end SVCCTL_EvtAckStatus_t */ + 80056a4: 4618 mov r0, r3 + 80056a6: 3728 adds r7, #40 @ 0x28 + 80056a8: 46bd mov sp, r7 + 80056aa: bd80 pop {r7, pc} + 80056ac: 2000002c .word 0x2000002c + +080056b0 <P2PS_STM_Init>: + * @brief Service initialization + * @param None + * @retval None + */ +void P2PS_STM_Init(void) +{ + 80056b0: b580 push {r7, lr} + 80056b2: b08a sub sp, #40 @ 0x28 + 80056b4: af06 add r7, sp, #24 + Char_UUID_t uuid16; + + /** + * Register the event handler to the BLE controller + */ + SVCCTL_RegisterSvcHandler(PeerToPeer_Event_Handler); + 80056b6: 484a ldr r0, [pc, #296] @ (80057e0 <P2PS_STM_Init+0x130>) + 80056b8: f000 f94a bl 8005950 <SVCCTL_RegisterSvcHandler> + * 2 for P2P Write characteristic + + * 2 for P2P Notify characteristic + + * 1 for client char configuration descriptor + + * + */ + COPY_P2P_SERVICE_UUID(uuid16.Char_UUID_128); + 80056bc: 238f movs r3, #143 @ 0x8f + 80056be: 703b strb r3, [r7, #0] + 80056c0: 23e5 movs r3, #229 @ 0xe5 + 80056c2: 707b strb r3, [r7, #1] + 80056c4: 23b3 movs r3, #179 @ 0xb3 + 80056c6: 70bb strb r3, [r7, #2] + 80056c8: 23d5 movs r3, #213 @ 0xd5 + 80056ca: 70fb strb r3, [r7, #3] + 80056cc: 232e movs r3, #46 @ 0x2e + 80056ce: 713b strb r3, [r7, #4] + 80056d0: 237f movs r3, #127 @ 0x7f + 80056d2: 717b strb r3, [r7, #5] + 80056d4: 234a movs r3, #74 @ 0x4a + 80056d6: 71bb strb r3, [r7, #6] + 80056d8: 2398 movs r3, #152 @ 0x98 + 80056da: 71fb strb r3, [r7, #7] + 80056dc: 232a movs r3, #42 @ 0x2a + 80056de: 723b strb r3, [r7, #8] + 80056e0: 2348 movs r3, #72 @ 0x48 + 80056e2: 727b strb r3, [r7, #9] + 80056e4: 237a movs r3, #122 @ 0x7a + 80056e6: 72bb strb r3, [r7, #10] + 80056e8: 23cc movs r3, #204 @ 0xcc + 80056ea: 72fb strb r3, [r7, #11] + 80056ec: 2340 movs r3, #64 @ 0x40 + 80056ee: 733b strb r3, [r7, #12] + 80056f0: 23fe movs r3, #254 @ 0xfe + 80056f2: 737b strb r3, [r7, #13] + 80056f4: 2300 movs r3, #0 + 80056f6: 73bb strb r3, [r7, #14] + 80056f8: 2300 movs r3, #0 + 80056fa: 73fb strb r3, [r7, #15] + aci_gatt_add_service(UUID_TYPE_128, + 80056fc: 4639 mov r1, r7 + 80056fe: 4b39 ldr r3, [pc, #228] @ (80057e4 <P2PS_STM_Init+0x134>) + 8005700: 9300 str r3, [sp, #0] + 8005702: 2306 movs r3, #6 + 8005704: 2201 movs r2, #1 + 8005706: 2002 movs r0, #2 + 8005708: f7ff fa12 bl 8004b30 <aci_gatt_add_service> + &(aPeerToPeerContext.PeerToPeerSvcHdle)); + + /** + * Add LED Characteristic + */ + COPY_P2P_WRITE_CHAR_UUID(uuid16.Char_UUID_128); + 800570c: 2319 movs r3, #25 + 800570e: 703b strb r3, [r7, #0] + 8005710: 23ed movs r3, #237 @ 0xed + 8005712: 707b strb r3, [r7, #1] + 8005714: 2382 movs r3, #130 @ 0x82 + 8005716: 70bb strb r3, [r7, #2] + 8005718: 23ae movs r3, #174 @ 0xae + 800571a: 70fb strb r3, [r7, #3] + 800571c: 23ed movs r3, #237 @ 0xed + 800571e: 713b strb r3, [r7, #4] + 8005720: 2321 movs r3, #33 @ 0x21 + 8005722: 717b strb r3, [r7, #5] + 8005724: 234c movs r3, #76 @ 0x4c + 8005726: 71bb strb r3, [r7, #6] + 8005728: 239d movs r3, #157 @ 0x9d + 800572a: 71fb strb r3, [r7, #7] + 800572c: 2341 movs r3, #65 @ 0x41 + 800572e: 723b strb r3, [r7, #8] + 8005730: 2345 movs r3, #69 @ 0x45 + 8005732: 727b strb r3, [r7, #9] + 8005734: 2322 movs r3, #34 @ 0x22 + 8005736: 72bb strb r3, [r7, #10] + 8005738: 238e movs r3, #142 @ 0x8e + 800573a: 72fb strb r3, [r7, #11] + 800573c: 2341 movs r3, #65 @ 0x41 + 800573e: 733b strb r3, [r7, #12] + 8005740: 23fe movs r3, #254 @ 0xfe + 8005742: 737b strb r3, [r7, #13] + 8005744: 2300 movs r3, #0 + 8005746: 73bb strb r3, [r7, #14] + 8005748: 2300 movs r3, #0 + 800574a: 73fb strb r3, [r7, #15] + aci_gatt_add_char(aPeerToPeerContext.PeerToPeerSvcHdle, + 800574c: 4b25 ldr r3, [pc, #148] @ (80057e4 <P2PS_STM_Init+0x134>) + 800574e: 8818 ldrh r0, [r3, #0] + 8005750: 463a mov r2, r7 + 8005752: 4b25 ldr r3, [pc, #148] @ (80057e8 <P2PS_STM_Init+0x138>) + 8005754: 9305 str r3, [sp, #20] + 8005756: 2301 movs r3, #1 + 8005758: 9304 str r3, [sp, #16] + 800575a: 230a movs r3, #10 + 800575c: 9303 str r3, [sp, #12] + 800575e: 2301 movs r3, #1 + 8005760: 9302 str r3, [sp, #8] + 8005762: 2300 movs r3, #0 + 8005764: 9301 str r3, [sp, #4] + 8005766: 2306 movs r3, #6 + 8005768: 9300 str r3, [sp, #0] + 800576a: 2302 movs r3, #2 + 800576c: 2102 movs r1, #2 + 800576e: f7ff fab5 bl 8004cdc <aci_gatt_add_char> + &(aPeerToPeerContext.P2PWriteClientToServerCharHdle)); + + /** + * Add Button Characteristic + */ + COPY_P2P_NOTIFY_UUID(uuid16.Char_UUID_128); + 8005772: 2319 movs r3, #25 + 8005774: 703b strb r3, [r7, #0] + 8005776: 23ed movs r3, #237 @ 0xed + 8005778: 707b strb r3, [r7, #1] + 800577a: 2382 movs r3, #130 @ 0x82 + 800577c: 70bb strb r3, [r7, #2] + 800577e: 23ae movs r3, #174 @ 0xae + 8005780: 70fb strb r3, [r7, #3] + 8005782: 23ed movs r3, #237 @ 0xed + 8005784: 713b strb r3, [r7, #4] + 8005786: 2321 movs r3, #33 @ 0x21 + 8005788: 717b strb r3, [r7, #5] + 800578a: 234c movs r3, #76 @ 0x4c + 800578c: 71bb strb r3, [r7, #6] + 800578e: 239d movs r3, #157 @ 0x9d + 8005790: 71fb strb r3, [r7, #7] + 8005792: 2341 movs r3, #65 @ 0x41 + 8005794: 723b strb r3, [r7, #8] + 8005796: 2345 movs r3, #69 @ 0x45 + 8005798: 727b strb r3, [r7, #9] + 800579a: 2322 movs r3, #34 @ 0x22 + 800579c: 72bb strb r3, [r7, #10] + 800579e: 238e movs r3, #142 @ 0x8e + 80057a0: 72fb strb r3, [r7, #11] + 80057a2: 2342 movs r3, #66 @ 0x42 + 80057a4: 733b strb r3, [r7, #12] + 80057a6: 23fe movs r3, #254 @ 0xfe + 80057a8: 737b strb r3, [r7, #13] + 80057aa: 2300 movs r3, #0 + 80057ac: 73bb strb r3, [r7, #14] + 80057ae: 2300 movs r3, #0 + 80057b0: 73fb strb r3, [r7, #15] + aci_gatt_add_char(aPeerToPeerContext.PeerToPeerSvcHdle, + 80057b2: 4b0c ldr r3, [pc, #48] @ (80057e4 <P2PS_STM_Init+0x134>) + 80057b4: 8818 ldrh r0, [r3, #0] + 80057b6: 463a mov r2, r7 + 80057b8: 4b0c ldr r3, [pc, #48] @ (80057ec <P2PS_STM_Init+0x13c>) + 80057ba: 9305 str r3, [sp, #20] + 80057bc: 2301 movs r3, #1 + 80057be: 9304 str r3, [sp, #16] + 80057c0: 230a movs r3, #10 + 80057c2: 9303 str r3, [sp, #12] + 80057c4: 2301 movs r3, #1 + 80057c6: 9302 str r3, [sp, #8] + 80057c8: 2300 movs r3, #0 + 80057ca: 9301 str r3, [sp, #4] + 80057cc: 2310 movs r3, #16 + 80057ce: 9300 str r3, [sp, #0] + 80057d0: 2302 movs r3, #2 + 80057d2: 2102 movs r1, #2 + 80057d4: f7ff fa82 bl 8004cdc <aci_gatt_add_char> + 0, + &(aPeerToPeerContext.RebootReqCharHdle)); +#endif + + + return; + 80057d8: bf00 nop +} + 80057da: 3710 adds r7, #16 + 80057dc: 46bd mov sp, r7 + 80057de: bd80 pop {r7, pc} + 80057e0: 080055e9 .word 0x080055e9 + 80057e4: 2000002c .word 0x2000002c + 80057e8: 2000002e .word 0x2000002e + 80057ec: 20000030 .word 0x20000030 + +080057f0 <BAS_Init>: +/* Private functions ----------------------------------------------------------*/ +/* Weak functions ----------------------------------------------------------*/ +void BVOPUS_STM_Init(void); + +__WEAK void BAS_Init( void ) +{ + 80057f0: b480 push {r7} + 80057f2: af00 add r7, sp, #0 + return; + 80057f4: bf00 nop +} + 80057f6: 46bd mov sp, r7 + 80057f8: f85d 7b04 ldr.w r7, [sp], #4 + 80057fc: 4770 bx lr + +080057fe <BLS_Init>: + +__WEAK void BLS_Init( void ) +{ + 80057fe: b480 push {r7} + 8005800: af00 add r7, sp, #0 + return; + 8005802: bf00 nop +} + 8005804: 46bd mov sp, r7 + 8005806: f85d 7b04 ldr.w r7, [sp], #4 + 800580a: 4770 bx lr + +0800580c <CRS_STM_Init>: +__WEAK void CRS_STM_Init( void ) +{ + 800580c: b480 push {r7} + 800580e: af00 add r7, sp, #0 + return; + 8005810: bf00 nop +} + 8005812: 46bd mov sp, r7 + 8005814: f85d 7b04 ldr.w r7, [sp], #4 + 8005818: 4770 bx lr + +0800581a <DIS_Init>: +__WEAK void DIS_Init( void ) +{ + 800581a: b480 push {r7} + 800581c: af00 add r7, sp, #0 + return; + 800581e: bf00 nop +} + 8005820: 46bd mov sp, r7 + 8005822: f85d 7b04 ldr.w r7, [sp], #4 + 8005826: 4770 bx lr + +08005828 <EDS_STM_Init>: +__WEAK void EDS_STM_Init( void ) +{ + 8005828: b480 push {r7} + 800582a: af00 add r7, sp, #0 + return; + 800582c: bf00 nop +} + 800582e: 46bd mov sp, r7 + 8005830: f85d 7b04 ldr.w r7, [sp], #4 + 8005834: 4770 bx lr + +08005836 <HIDS_Init>: +__WEAK void HIDS_Init( void ) +{ + 8005836: b480 push {r7} + 8005838: af00 add r7, sp, #0 + return; + 800583a: bf00 nop +} + 800583c: 46bd mov sp, r7 + 800583e: f85d 7b04 ldr.w r7, [sp], #4 + 8005842: 4770 bx lr + +08005844 <HRS_Init>: +__WEAK void HRS_Init( void ) +{ + 8005844: b480 push {r7} + 8005846: af00 add r7, sp, #0 + return; + 8005848: bf00 nop +} + 800584a: 46bd mov sp, r7 + 800584c: f85d 7b04 ldr.w r7, [sp], #4 + 8005850: 4770 bx lr + +08005852 <HTS_Init>: +__WEAK void HTS_Init( void ) +{ + 8005852: b480 push {r7} + 8005854: af00 add r7, sp, #0 + return; + 8005856: bf00 nop +} + 8005858: 46bd mov sp, r7 + 800585a: f85d 7b04 ldr.w r7, [sp], #4 + 800585e: 4770 bx lr + +08005860 <IAS_Init>: +__WEAK void IAS_Init( void ) +{ + 8005860: b480 push {r7} + 8005862: af00 add r7, sp, #0 + return; + 8005864: bf00 nop +} + 8005866: 46bd mov sp, r7 + 8005868: f85d 7b04 ldr.w r7, [sp], #4 + 800586c: 4770 bx lr + +0800586e <LLS_Init>: +__WEAK void LLS_Init( void ) +{ + 800586e: b480 push {r7} + 8005870: af00 add r7, sp, #0 + return; + 8005872: bf00 nop +} + 8005874: 46bd mov sp, r7 + 8005876: f85d 7b04 ldr.w r7, [sp], #4 + 800587a: 4770 bx lr + +0800587c <TPS_Init>: +__WEAK void TPS_Init( void ) +{ + 800587c: b480 push {r7} + 800587e: af00 add r7, sp, #0 + return; + 8005880: bf00 nop +} + 8005882: 46bd mov sp, r7 + 8005884: f85d 7b04 ldr.w r7, [sp], #4 + 8005888: 4770 bx lr + +0800588a <MOTENV_STM_Init>: +__WEAK void MOTENV_STM_Init( void ) +{ + 800588a: b480 push {r7} + 800588c: af00 add r7, sp, #0 + return; + 800588e: bf00 nop +} + 8005890: 46bd mov sp, r7 + 8005892: f85d 7b04 ldr.w r7, [sp], #4 + 8005896: 4770 bx lr + +08005898 <ZDD_STM_Init>: +__WEAK void P2PS_STM_Init( void ) +{ + return; +} +__WEAK void ZDD_STM_Init( void ) +{ + 8005898: b480 push {r7} + 800589a: af00 add r7, sp, #0 + return; + 800589c: bf00 nop +} + 800589e: 46bd mov sp, r7 + 80058a0: f85d 7b04 ldr.w r7, [sp], #4 + 80058a4: 4770 bx lr + +080058a6 <OTAS_STM_Init>: +__WEAK void OTAS_STM_Init( void ) +{ + 80058a6: b480 push {r7} + 80058a8: af00 add r7, sp, #0 + return; + 80058aa: bf00 nop +} + 80058ac: 46bd mov sp, r7 + 80058ae: f85d 7b04 ldr.w r7, [sp], #4 + 80058b2: 4770 bx lr + +080058b4 <MESH_Init>: +__WEAK void MESH_Init( void ) +{ + 80058b4: b480 push {r7} + 80058b6: af00 add r7, sp, #0 + return; + 80058b8: bf00 nop +} + 80058ba: 46bd mov sp, r7 + 80058bc: f85d 7b04 ldr.w r7, [sp], #4 + 80058c0: 4770 bx lr + +080058c2 <BVOPUS_STM_Init>: +__WEAK void BVOPUS_STM_Init( void ) +{ + 80058c2: b480 push {r7} + 80058c4: af00 add r7, sp, #0 + return; + 80058c6: bf00 nop +} + 80058c8: 46bd mov sp, r7 + 80058ca: f85d 7b04 ldr.w r7, [sp], #4 + 80058ce: 4770 bx lr + +080058d0 <SVCCTL_InitCustomSvc>: +__WEAK void SVCCTL_InitCustomSvc( void ) +{ + 80058d0: b480 push {r7} + 80058d2: af00 add r7, sp, #0 + return; + 80058d4: bf00 nop +} + 80058d6: 46bd mov sp, r7 + 80058d8: f85d 7b04 ldr.w r7, [sp], #4 + 80058dc: 4770 bx lr + ... + +080058e0 <SVCCTL_Init>: + +/* Functions Definition ------------------------------------------------------*/ + +void SVCCTL_Init( void ) +{ + 80058e0: b580 push {r7, lr} + 80058e2: af00 add r7, sp, #0 + + /** + * Initialize the number of registered Handler + */ + SVCCTL_EvtHandler.NbreOfRegisteredHandler = 0; + 80058e4: 4b04 ldr r3, [pc, #16] @ (80058f8 <SVCCTL_Init+0x18>) + 80058e6: 2200 movs r2, #0 + 80058e8: 771a strb r2, [r3, #28] + SVCCTL_CltHandler.NbreOfRegisteredHandler = 0; + 80058ea: 4b04 ldr r3, [pc, #16] @ (80058fc <SVCCTL_Init+0x1c>) + 80058ec: 2200 movs r2, #0 + 80058ee: 701a strb r2, [r3, #0] + + /** + * Add and Initialize requested services + */ + SVCCTL_SvcInit(); + 80058f0: f000 f806 bl 8005900 <SVCCTL_SvcInit> + + return; + 80058f4: bf00 nop +} + 80058f6: bd80 pop {r7, pc} + 80058f8: 20000034 .word 0x20000034 + 80058fc: 20000054 .word 0x20000054 + +08005900 <SVCCTL_SvcInit>: + +__WEAK void SVCCTL_SvcInit(void) +{ + 8005900: b580 push {r7, lr} + 8005902: af00 add r7, sp, #0 + BAS_Init(); + 8005904: f7ff ff74 bl 80057f0 <BAS_Init> + + BLS_Init(); + 8005908: f7ff ff79 bl 80057fe <BLS_Init> + + CRS_STM_Init(); + 800590c: f7ff ff7e bl 800580c <CRS_STM_Init> + + DIS_Init(); + 8005910: f7ff ff83 bl 800581a <DIS_Init> + + EDS_STM_Init(); + 8005914: f7ff ff88 bl 8005828 <EDS_STM_Init> + + HIDS_Init(); + 8005918: f7ff ff8d bl 8005836 <HIDS_Init> + + HRS_Init(); + 800591c: f7ff ff92 bl 8005844 <HRS_Init> + + HTS_Init(); + 8005920: f7ff ff97 bl 8005852 <HTS_Init> + + IAS_Init(); + 8005924: f7ff ff9c bl 8005860 <IAS_Init> + + LLS_Init(); + 8005928: f7ff ffa1 bl 800586e <LLS_Init> + + TPS_Init(); + 800592c: f7ff ffa6 bl 800587c <TPS_Init> + + MOTENV_STM_Init(); + 8005930: f7ff ffab bl 800588a <MOTENV_STM_Init> + + P2PS_STM_Init(); + 8005934: f7ff febc bl 80056b0 <P2PS_STM_Init> + + ZDD_STM_Init(); + 8005938: f7ff ffae bl 8005898 <ZDD_STM_Init> + + OTAS_STM_Init(); + 800593c: f7ff ffb3 bl 80058a6 <OTAS_STM_Init> + + BVOPUS_STM_Init(); + 8005940: f7ff ffbf bl 80058c2 <BVOPUS_STM_Init> + + MESH_Init(); + 8005944: f7ff ffb6 bl 80058b4 <MESH_Init> + + SVCCTL_InitCustomSvc(); + 8005948: f7ff ffc2 bl 80058d0 <SVCCTL_InitCustomSvc> + + return; + 800594c: bf00 nop +} + 800594e: bd80 pop {r7, pc} + +08005950 <SVCCTL_RegisterSvcHandler>: + * @brief BLE Controller initialization + * @param None + * @retval None + */ +void SVCCTL_RegisterSvcHandler( SVC_CTL_p_EvtHandler_t pfBLE_SVC_Service_Event_Handler ) +{ + 8005950: b480 push {r7} + 8005952: b083 sub sp, #12 + 8005954: af00 add r7, sp, #0 + 8005956: 6078 str r0, [r7, #4] +#if (BLE_CFG_SVC_MAX_NBR_CB > 0) + SVCCTL_EvtHandler.SVCCTL__SvcHandlerTab[SVCCTL_EvtHandler.NbreOfRegisteredHandler] = pfBLE_SVC_Service_Event_Handler; + 8005958: 4b09 ldr r3, [pc, #36] @ (8005980 <SVCCTL_RegisterSvcHandler+0x30>) + 800595a: 7f1b ldrb r3, [r3, #28] + 800595c: 4619 mov r1, r3 + 800595e: 4a08 ldr r2, [pc, #32] @ (8005980 <SVCCTL_RegisterSvcHandler+0x30>) + 8005960: 687b ldr r3, [r7, #4] + 8005962: f842 3021 str.w r3, [r2, r1, lsl #2] + SVCCTL_EvtHandler.NbreOfRegisteredHandler++; + 8005966: 4b06 ldr r3, [pc, #24] @ (8005980 <SVCCTL_RegisterSvcHandler+0x30>) + 8005968: 7f1b ldrb r3, [r3, #28] + 800596a: 3301 adds r3, #1 + 800596c: b2da uxtb r2, r3 + 800596e: 4b04 ldr r3, [pc, #16] @ (8005980 <SVCCTL_RegisterSvcHandler+0x30>) + 8005970: 771a strb r2, [r3, #28] +#else + (void)(pfBLE_SVC_Service_Event_Handler); +#endif + + return; + 8005972: bf00 nop +} + 8005974: 370c adds r7, #12 + 8005976: 46bd mov sp, r7 + 8005978: f85d 7b04 ldr.w r7, [sp], #4 + 800597c: 4770 bx lr + 800597e: bf00 nop + 8005980: 20000034 .word 0x20000034 + +08005984 <SVCCTL_UserEvtRx>: + + return; +} + +__WEAK SVCCTL_UserEvtFlowStatus_t SVCCTL_UserEvtRx( void *pckt ) +{ + 8005984: b580 push {r7, lr} + 8005986: b086 sub sp, #24 + 8005988: af00 add r7, sp, #0 + 800598a: 6078 str r0, [r7, #4] + evt_blecore_aci *blecore_evt; + SVCCTL_EvtAckStatus_t event_notification_status; + SVCCTL_UserEvtFlowStatus_t return_status; + uint8_t index; + + event_pckt = (hci_event_pckt*) ((hci_uart_pckt *) pckt)->data; + 800598c: 687b ldr r3, [r7, #4] + 800598e: 3301 adds r3, #1 + 8005990: 613b str r3, [r7, #16] + event_notification_status = SVCCTL_EvtNotAck; + 8005992: 2300 movs r3, #0 + 8005994: 75fb strb r3, [r7, #23] + + switch (event_pckt->evt) + 8005996: 693b ldr r3, [r7, #16] + 8005998: 781b ldrb r3, [r3, #0] + 800599a: 2bff cmp r3, #255 @ 0xff + 800599c: d125 bne.n 80059ea <SVCCTL_UserEvtRx+0x66> + { + case HCI_VENDOR_SPECIFIC_DEBUG_EVT_CODE: + { + blecore_evt = (evt_blecore_aci*) event_pckt->data; + 800599e: 693b ldr r3, [r7, #16] + 80059a0: 3302 adds r3, #2 + 80059a2: 60fb str r3, [r7, #12] + + switch ((blecore_evt->ecode) & SVCCTL_EGID_EVT_MASK) + 80059a4: 68fb ldr r3, [r7, #12] + 80059a6: 881b ldrh r3, [r3, #0] + 80059a8: b29b uxth r3, r3 + 80059aa: f403 437f and.w r3, r3, #65280 @ 0xff00 + 80059ae: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 + 80059b2: d118 bne.n 80059e6 <SVCCTL_UserEvtRx+0x62> + { + case SVCCTL_GATT_EVT_TYPE: +#if (BLE_CFG_SVC_MAX_NBR_CB > 0) + /* For Service event handler */ + for (index = 0; index < SVCCTL_EvtHandler.NbreOfRegisteredHandler; index++) + 80059b4: 2300 movs r3, #0 + 80059b6: 757b strb r3, [r7, #21] + 80059b8: e00d b.n 80059d6 <SVCCTL_UserEvtRx+0x52> + { + event_notification_status = SVCCTL_EvtHandler.SVCCTL__SvcHandlerTab[index](pckt); + 80059ba: 7d7b ldrb r3, [r7, #21] + 80059bc: 4a1a ldr r2, [pc, #104] @ (8005a28 <SVCCTL_UserEvtRx+0xa4>) + 80059be: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80059c2: 6878 ldr r0, [r7, #4] + 80059c4: 4798 blx r3 + 80059c6: 4603 mov r3, r0 + 80059c8: 75fb strb r3, [r7, #23] + /** + * When a GATT event has been acknowledged by a Service, there is no need to call the other registered handlers + * a GATT event is relevant for only one Service + */ + if (event_notification_status != SVCCTL_EvtNotAck) + 80059ca: 7dfb ldrb r3, [r7, #23] + 80059cc: 2b00 cmp r3, #0 + 80059ce: d108 bne.n 80059e2 <SVCCTL_UserEvtRx+0x5e> + for (index = 0; index < SVCCTL_EvtHandler.NbreOfRegisteredHandler; index++) + 80059d0: 7d7b ldrb r3, [r7, #21] + 80059d2: 3301 adds r3, #1 + 80059d4: 757b strb r3, [r7, #21] + 80059d6: 4b14 ldr r3, [pc, #80] @ (8005a28 <SVCCTL_UserEvtRx+0xa4>) + 80059d8: 7f1b ldrb r3, [r3, #28] + 80059da: 7d7a ldrb r2, [r7, #21] + 80059dc: 429a cmp r2, r3 + 80059de: d3ec bcc.n 80059ba <SVCCTL_UserEvtRx+0x36> + */ + break; + } + } +#endif + break; + 80059e0: e002 b.n 80059e8 <SVCCTL_UserEvtRx+0x64> + break; + 80059e2: bf00 nop + break; + 80059e4: e000 b.n 80059e8 <SVCCTL_UserEvtRx+0x64> + + default: + break; + 80059e6: bf00 nop + } + } + break; /* HCI_HCI_VENDOR_SPECIFIC_DEBUG_EVT_CODE_SPECIFIC */ + 80059e8: e000 b.n 80059ec <SVCCTL_UserEvtRx+0x68> + + default: + break; + 80059ea: bf00 nop + + /** + * When no registered handlers (either Service or Client) has acknowledged the GATT event, it is reported to the application + * a GAP event is always reported to the application. + */ + switch (event_notification_status) + 80059ec: 7dfb ldrb r3, [r7, #23] + 80059ee: 2b02 cmp r3, #2 + 80059f0: d00f beq.n 8005a12 <SVCCTL_UserEvtRx+0x8e> + 80059f2: 2b02 cmp r3, #2 + 80059f4: dc10 bgt.n 8005a18 <SVCCTL_UserEvtRx+0x94> + 80059f6: 2b00 cmp r3, #0 + 80059f8: d002 beq.n 8005a00 <SVCCTL_UserEvtRx+0x7c> + 80059fa: 2b01 cmp r3, #1 + 80059fc: d006 beq.n 8005a0c <SVCCTL_UserEvtRx+0x88> + 80059fe: e00b b.n 8005a18 <SVCCTL_UserEvtRx+0x94> + case SVCCTL_EvtNotAck: + /** + * The event has NOT been managed. + * It shall be passed to the application for processing + */ + return_status = SVCCTL_App_Notification(pckt); + 8005a00: 6878 ldr r0, [r7, #4] + 8005a02: f000 ffb1 bl 8006968 <SVCCTL_App_Notification> + 8005a06: 4603 mov r3, r0 + 8005a08: 75bb strb r3, [r7, #22] + break; + 8005a0a: e008 b.n 8005a1e <SVCCTL_UserEvtRx+0x9a> + + case SVCCTL_EvtAckFlowEnable: + return_status = SVCCTL_UserEvtFlowEnable; + 8005a0c: 2301 movs r3, #1 + 8005a0e: 75bb strb r3, [r7, #22] + break; + 8005a10: e005 b.n 8005a1e <SVCCTL_UserEvtRx+0x9a> + + case SVCCTL_EvtAckFlowDisable: + return_status = SVCCTL_UserEvtFlowDisable; + 8005a12: 2300 movs r3, #0 + 8005a14: 75bb strb r3, [r7, #22] + break; + 8005a16: e002 b.n 8005a1e <SVCCTL_UserEvtRx+0x9a> + + default: + return_status = SVCCTL_UserEvtFlowEnable; + 8005a18: 2301 movs r3, #1 + 8005a1a: 75bb strb r3, [r7, #22] + break; + 8005a1c: bf00 nop + } + + return (return_status); + 8005a1e: 7dbb ldrb r3, [r7, #22] +} + 8005a20: 4618 mov r0, r3 + 8005a22: 3718 adds r7, #24 + 8005a24: 46bd mov sp, r7 + 8005a26: bd80 pop {r7, pc} + 8005a28: 20000034 .word 0x20000034 + +08005a2c <SHCI_C2_BLE_Init>: + + return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]); +} + +SHCI_CmdStatus_t SHCI_C2_BLE_Init( SHCI_C2_Ble_Init_Cmd_Packet_t *pCmdPacket ) +{ + 8005a2c: b580 push {r7, lr} + 8005a2e: b088 sub sp, #32 + 8005a30: af00 add r7, sp, #0 + 8005a32: 6078 str r0, [r7, #4] + * Buffer is large enough to hold command complete without payload + */ + uint8_t local_buffer[TL_BLEEVT_CC_BUFFER_SIZE]; + TL_EvtPacket_t * p_rsp; + + p_rsp = (TL_EvtPacket_t *)local_buffer; + 8005a34: f107 030c add.w r3, r7, #12 + 8005a38: 61fb str r3, [r7, #28] + + shci_send( SHCI_OPCODE_C2_BLE_INIT, + sizeof( SHCI_C2_Ble_Init_Cmd_Param_t ), + (uint8_t*)&pCmdPacket->Param, + 8005a3a: 687b ldr r3, [r7, #4] + 8005a3c: f103 020c add.w r2, r3, #12 + shci_send( SHCI_OPCODE_C2_BLE_INIT, + 8005a40: 69fb ldr r3, [r7, #28] + 8005a42: 212f movs r1, #47 @ 0x2f + 8005a44: f64f 4066 movw r0, #64614 @ 0xfc66 + 8005a48: f000 fae8 bl 800601c <shci_send> + p_rsp ); + + return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]); + 8005a4c: 69fb ldr r3, [r7, #28] + 8005a4e: 330b adds r3, #11 + 8005a50: 78db ldrb r3, [r3, #3] +} + 8005a52: 4618 mov r0, r3 + 8005a54: 3720 adds r7, #32 + 8005a56: 46bd mov sp, r7 + 8005a58: bd80 pop {r7, pc} + +08005a5a <SHCI_C2_DEBUG_Init>: + + return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]); +} + +SHCI_CmdStatus_t SHCI_C2_DEBUG_Init( SHCI_C2_DEBUG_Init_Cmd_Packet_t *pCmdPacket ) +{ + 8005a5a: b580 push {r7, lr} + 8005a5c: b088 sub sp, #32 + 8005a5e: af00 add r7, sp, #0 + 8005a60: 6078 str r0, [r7, #4] + * Buffer is large enough to hold command complete without payload + */ + uint8_t local_buffer[TL_BLEEVT_CC_BUFFER_SIZE]; + TL_EvtPacket_t * p_rsp; + + p_rsp = (TL_EvtPacket_t *)local_buffer; + 8005a62: f107 030c add.w r3, r7, #12 + 8005a66: 61fb str r3, [r7, #28] + + shci_send( SHCI_OPCODE_C2_DEBUG_INIT, + sizeof( SHCI_C2_DEBUG_init_Cmd_Param_t ), + (uint8_t*)&pCmdPacket->Param, + 8005a68: 687b ldr r3, [r7, #4] + 8005a6a: f103 020c add.w r2, r3, #12 + shci_send( SHCI_OPCODE_C2_DEBUG_INIT, + 8005a6e: 69fb ldr r3, [r7, #28] + 8005a70: 210f movs r1, #15 + 8005a72: f64f 4068 movw r0, #64616 @ 0xfc68 + 8005a76: f000 fad1 bl 800601c <shci_send> + p_rsp ); + + return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]); + 8005a7a: 69fb ldr r3, [r7, #28] + 8005a7c: 330b adds r3, #11 + 8005a7e: 78db ldrb r3, [r3, #3] +} + 8005a80: 4618 mov r0, r3 + 8005a82: 3720 adds r7, #32 + 8005a84: 46bd mov sp, r7 + 8005a86: bd80 pop {r7, pc} + +08005a88 <SHCI_C2_Config>: + + return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]); +} + +SHCI_CmdStatus_t SHCI_C2_Config(SHCI_C2_CONFIG_Cmd_Param_t *pCmdPacket) +{ + 8005a88: b580 push {r7, lr} + 8005a8a: b088 sub sp, #32 + 8005a8c: af00 add r7, sp, #0 + 8005a8e: 6078 str r0, [r7, #4] + * Buffer is large enough to hold command complete without payload + */ + uint8_t local_buffer[TL_BLEEVT_CC_BUFFER_SIZE]; + TL_EvtPacket_t * p_rsp; + + p_rsp = (TL_EvtPacket_t *)local_buffer; + 8005a90: f107 030c add.w r3, r7, #12 + 8005a94: 61fb str r3, [r7, #28] + + shci_send( SHCI_OPCODE_C2_CONFIG, + 8005a96: 69fb ldr r3, [r7, #28] + 8005a98: 687a ldr r2, [r7, #4] + 8005a9a: 2110 movs r1, #16 + 8005a9c: f64f 4075 movw r0, #64629 @ 0xfc75 + 8005aa0: f000 fabc bl 800601c <shci_send> + sizeof(SHCI_C2_CONFIG_Cmd_Param_t), + (uint8_t*)pCmdPacket, + p_rsp ); + + return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]); + 8005aa4: 69fb ldr r3, [r7, #28] + 8005aa6: 330b adds r3, #11 + 8005aa8: 78db ldrb r3, [r3, #3] +} + 8005aaa: 4618 mov r0, r3 + 8005aac: 3720 adds r7, #32 + 8005aae: 46bd mov sp, r7 + 8005ab0: bd80 pop {r7, pc} + ... + +08005ab4 <SHCI_GetWirelessFwInfo>: + * Local System COMMAND + * These commands are NOT sent to the CPU2 + */ + +SHCI_CmdStatus_t SHCI_GetWirelessFwInfo( WirelessFwInfo_t* pWirelessInfo ) +{ + 8005ab4: b480 push {r7} + 8005ab6: b08b sub sp, #44 @ 0x2c + 8005ab8: af00 add r7, sp, #0 + 8005aba: 6078 str r0, [r7, #4] + uint32_t ipccdba = 0; + 8005abc: 2300 movs r3, #0 + 8005abe: 613b str r3, [r7, #16] + MB_RefTable_t * p_RefTable = NULL; + 8005ac0: 2300 movs r3, #0 + 8005ac2: 60fb str r3, [r7, #12] + uint32_t wireless_firmware_version = 0; + 8005ac4: 2300 movs r3, #0 + 8005ac6: 627b str r3, [r7, #36] @ 0x24 + uint32_t wireless_firmware_memorySize = 0; + 8005ac8: 2300 movs r3, #0 + 8005aca: 623b str r3, [r7, #32] + uint32_t wireless_firmware_infoStack = 0; + 8005acc: 2300 movs r3, #0 + 8005ace: 61fb str r3, [r7, #28] + MB_FUS_DeviceInfoTable_t * p_fus_device_info_table = NULL; + 8005ad0: 2300 movs r3, #0 + 8005ad2: 60bb str r3, [r7, #8] + uint32_t fus_version = 0; + 8005ad4: 2300 movs r3, #0 + 8005ad6: 61bb str r3, [r7, #24] + uint32_t fus_memorySize = 0; + 8005ad8: 2300 movs r3, #0 + 8005ada: 617b str r3, [r7, #20] + + ipccdba = READ_BIT( FLASH->IPCCBR, FLASH_IPCCBR_IPCCDBA ); + 8005adc: 4b4a ldr r3, [pc, #296] @ (8005c08 <SHCI_GetWirelessFwInfo+0x154>) + 8005ade: 6bdb ldr r3, [r3, #60] @ 0x3c + 8005ae0: f3c3 030d ubfx r3, r3, #0, #14 + 8005ae4: 613b str r3, [r7, #16] + /** + * The Device Info Table mapping depends on which firmware is running on CPU2. + * If the FUS is running on CPU2, FUS_DEVICE_INFO_TABLE_VALIDITY_KEYWORD shall be written in the table. + * Otherwise, it means the Wireless Firmware is running on the CPU2 + */ + p_fus_device_info_table = (MB_FUS_DeviceInfoTable_t*)(*(uint32_t*)((ipccdba<<2) + SRAM2A_BASE)); + 8005ae6: 693b ldr r3, [r7, #16] + 8005ae8: 009b lsls r3, r3, #2 + 8005aea: f103 5300 add.w r3, r3, #536870912 @ 0x20000000 + 8005aee: f503 3340 add.w r3, r3, #196608 @ 0x30000 + 8005af2: 681b ldr r3, [r3, #0] + 8005af4: 60bb str r3, [r7, #8] + + if(p_fus_device_info_table->DeviceInfoTableState == FUS_DEVICE_INFO_TABLE_VALIDITY_KEYWORD) + 8005af6: 68bb ldr r3, [r7, #8] + 8005af8: 681b ldr r3, [r3, #0] + 8005afa: 4a44 ldr r2, [pc, #272] @ (8005c0c <SHCI_GetWirelessFwInfo+0x158>) + 8005afc: 4293 cmp r3, r2 + 8005afe: d10f bne.n 8005b20 <SHCI_GetWirelessFwInfo+0x6c> + /* The FUS is running on CPU2 */ + /** + * Retrieve the WirelessFwInfoTable + * This table is stored in RAM at startup during the TL (transport layer) initialization + */ + wireless_firmware_version = p_fus_device_info_table->WirelessStackVersion; + 8005b00: 68bb ldr r3, [r7, #8] + 8005b02: 695b ldr r3, [r3, #20] + 8005b04: 627b str r3, [r7, #36] @ 0x24 + wireless_firmware_memorySize = p_fus_device_info_table->WirelessStackMemorySize; + 8005b06: 68bb ldr r3, [r7, #8] + 8005b08: 699b ldr r3, [r3, #24] + 8005b0a: 623b str r3, [r7, #32] + wireless_firmware_infoStack = p_fus_device_info_table->WirelessFirmwareBleInfo; + 8005b0c: 68bb ldr r3, [r7, #8] + 8005b0e: 69db ldr r3, [r3, #28] + 8005b10: 61fb str r3, [r7, #28] + + /** + * Retrieve the FusInfoTable + * This table is stored in RAM at startup during the TL (transport layer) initialization + */ + fus_version = p_fus_device_info_table->FusVersion; + 8005b12: 68bb ldr r3, [r7, #8] + 8005b14: 68db ldr r3, [r3, #12] + 8005b16: 61bb str r3, [r7, #24] + fus_memorySize = p_fus_device_info_table->FusMemorySize; + 8005b18: 68bb ldr r3, [r7, #8] + 8005b1a: 691b ldr r3, [r3, #16] + 8005b1c: 617b str r3, [r7, #20] + 8005b1e: e01a b.n 8005b56 <SHCI_GetWirelessFwInfo+0xa2> + } + else + { + /* The Wireless Firmware is running on CPU2 */ + p_RefTable = (MB_RefTable_t*)((ipccdba<<2) + SRAM2A_BASE); + 8005b20: 693b ldr r3, [r7, #16] + 8005b22: 009b lsls r3, r3, #2 + 8005b24: f103 5300 add.w r3, r3, #536870912 @ 0x20000000 + 8005b28: f503 3340 add.w r3, r3, #196608 @ 0x30000 + 8005b2c: 60fb str r3, [r7, #12] + + /** + * Retrieve the WirelessFwInfoTable + * This table is stored in RAM at startup during the TL (transport layer) initialization + */ + wireless_firmware_version = p_RefTable->p_device_info_table->WirelessFwInfoTable.Version; + 8005b2e: 68fb ldr r3, [r7, #12] + 8005b30: 681b ldr r3, [r3, #0] + 8005b32: 691b ldr r3, [r3, #16] + 8005b34: 627b str r3, [r7, #36] @ 0x24 + wireless_firmware_memorySize = p_RefTable->p_device_info_table->WirelessFwInfoTable.MemorySize; + 8005b36: 68fb ldr r3, [r7, #12] + 8005b38: 681b ldr r3, [r3, #0] + 8005b3a: 695b ldr r3, [r3, #20] + 8005b3c: 623b str r3, [r7, #32] + wireless_firmware_infoStack = p_RefTable->p_device_info_table->WirelessFwInfoTable.InfoStack; + 8005b3e: 68fb ldr r3, [r7, #12] + 8005b40: 681b ldr r3, [r3, #0] + 8005b42: 699b ldr r3, [r3, #24] + 8005b44: 61fb str r3, [r7, #28] + + /** + * Retrieve the FusInfoTable + * This table is stored in RAM at startup during the TL (transport layer) initialization + */ + fus_version = p_RefTable->p_device_info_table->FusInfoTable.Version; + 8005b46: 68fb ldr r3, [r7, #12] + 8005b48: 681b ldr r3, [r3, #0] + 8005b4a: 685b ldr r3, [r3, #4] + 8005b4c: 61bb str r3, [r7, #24] + fus_memorySize = p_RefTable->p_device_info_table->FusInfoTable.MemorySize; + 8005b4e: 68fb ldr r3, [r7, #12] + 8005b50: 681b ldr r3, [r3, #0] + 8005b52: 689b ldr r3, [r3, #8] + 8005b54: 617b str r3, [r7, #20] + + /** + * Retrieve the WirelessFwInfoTable + * This table is stored in RAM at startup during the TL (transport layer) initialization + */ + pWirelessInfo->VersionMajor = ((wireless_firmware_version & INFO_VERSION_MAJOR_MASK) >> INFO_VERSION_MAJOR_OFFSET); + 8005b56: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005b58: 0e1b lsrs r3, r3, #24 + 8005b5a: b2da uxtb r2, r3 + 8005b5c: 687b ldr r3, [r7, #4] + 8005b5e: 701a strb r2, [r3, #0] + pWirelessInfo->VersionMinor = ((wireless_firmware_version & INFO_VERSION_MINOR_MASK) >> INFO_VERSION_MINOR_OFFSET); + 8005b60: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005b62: 0c1b lsrs r3, r3, #16 + 8005b64: b2da uxtb r2, r3 + 8005b66: 687b ldr r3, [r7, #4] + 8005b68: 705a strb r2, [r3, #1] + pWirelessInfo->VersionSub = ((wireless_firmware_version & INFO_VERSION_SUB_MASK) >> INFO_VERSION_SUB_OFFSET); + 8005b6a: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005b6c: 0a1b lsrs r3, r3, #8 + 8005b6e: b2da uxtb r2, r3 + 8005b70: 687b ldr r3, [r7, #4] + 8005b72: 709a strb r2, [r3, #2] + pWirelessInfo->VersionBranch = ((wireless_firmware_version & INFO_VERSION_BRANCH_MASK) >> INFO_VERSION_BRANCH_OFFSET); + 8005b74: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005b76: 091b lsrs r3, r3, #4 + 8005b78: b2db uxtb r3, r3 + 8005b7a: f003 030f and.w r3, r3, #15 + 8005b7e: b2da uxtb r2, r3 + 8005b80: 687b ldr r3, [r7, #4] + 8005b82: 70da strb r2, [r3, #3] + pWirelessInfo->VersionReleaseType = ((wireless_firmware_version & INFO_VERSION_TYPE_MASK) >> INFO_VERSION_TYPE_OFFSET); + 8005b84: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005b86: b2db uxtb r3, r3 + 8005b88: f003 030f and.w r3, r3, #15 + 8005b8c: b2da uxtb r2, r3 + 8005b8e: 687b ldr r3, [r7, #4] + 8005b90: 711a strb r2, [r3, #4] + + pWirelessInfo->MemorySizeSram2B = ((wireless_firmware_memorySize & INFO_SIZE_SRAM2B_MASK) >> INFO_SIZE_SRAM2B_OFFSET); + 8005b92: 6a3b ldr r3, [r7, #32] + 8005b94: 0e1b lsrs r3, r3, #24 + 8005b96: b2da uxtb r2, r3 + 8005b98: 687b ldr r3, [r7, #4] + 8005b9a: 715a strb r2, [r3, #5] + pWirelessInfo->MemorySizeSram2A = ((wireless_firmware_memorySize & INFO_SIZE_SRAM2A_MASK) >> INFO_SIZE_SRAM2A_OFFSET); + 8005b9c: 6a3b ldr r3, [r7, #32] + 8005b9e: 0c1b lsrs r3, r3, #16 + 8005ba0: b2da uxtb r2, r3 + 8005ba2: 687b ldr r3, [r7, #4] + 8005ba4: 719a strb r2, [r3, #6] + pWirelessInfo->MemorySizeSram1 = ((wireless_firmware_memorySize & INFO_SIZE_SRAM1_MASK) >> INFO_SIZE_SRAM1_OFFSET); + 8005ba6: 6a3b ldr r3, [r7, #32] + 8005ba8: 0a1b lsrs r3, r3, #8 + 8005baa: b2da uxtb r2, r3 + 8005bac: 687b ldr r3, [r7, #4] + 8005bae: 71da strb r2, [r3, #7] + pWirelessInfo->MemorySizeFlash = ((wireless_firmware_memorySize & INFO_SIZE_FLASH_MASK) >> INFO_SIZE_FLASH_OFFSET); + 8005bb0: 6a3b ldr r3, [r7, #32] + 8005bb2: b2da uxtb r2, r3 + 8005bb4: 687b ldr r3, [r7, #4] + 8005bb6: 721a strb r2, [r3, #8] + + pWirelessInfo->StackType = ((wireless_firmware_infoStack & INFO_STACK_TYPE_MASK) >> INFO_STACK_TYPE_OFFSET); + 8005bb8: 69fb ldr r3, [r7, #28] + 8005bba: b2da uxtb r2, r3 + 8005bbc: 687b ldr r3, [r7, #4] + 8005bbe: 725a strb r2, [r3, #9] + + /** + * Retrieve the FusInfoTable + * This table is stored in RAM at startup during the TL (transport layer) initialization + */ + pWirelessInfo->FusVersionMajor = ((fus_version & INFO_VERSION_MAJOR_MASK) >> INFO_VERSION_MAJOR_OFFSET); + 8005bc0: 69bb ldr r3, [r7, #24] + 8005bc2: 0e1b lsrs r3, r3, #24 + 8005bc4: b2da uxtb r2, r3 + 8005bc6: 687b ldr r3, [r7, #4] + 8005bc8: 729a strb r2, [r3, #10] + pWirelessInfo->FusVersionMinor = ((fus_version & INFO_VERSION_MINOR_MASK) >> INFO_VERSION_MINOR_OFFSET); + 8005bca: 69bb ldr r3, [r7, #24] + 8005bcc: 0c1b lsrs r3, r3, #16 + 8005bce: b2da uxtb r2, r3 + 8005bd0: 687b ldr r3, [r7, #4] + 8005bd2: 72da strb r2, [r3, #11] + pWirelessInfo->FusVersionSub = ((fus_version & INFO_VERSION_SUB_MASK) >> INFO_VERSION_SUB_OFFSET); + 8005bd4: 69bb ldr r3, [r7, #24] + 8005bd6: 0a1b lsrs r3, r3, #8 + 8005bd8: b2da uxtb r2, r3 + 8005bda: 687b ldr r3, [r7, #4] + 8005bdc: 731a strb r2, [r3, #12] + + pWirelessInfo->FusMemorySizeSram2B = ((fus_memorySize & INFO_SIZE_SRAM2B_MASK) >> INFO_SIZE_SRAM2B_OFFSET); + 8005bde: 697b ldr r3, [r7, #20] + 8005be0: 0e1b lsrs r3, r3, #24 + 8005be2: b2da uxtb r2, r3 + 8005be4: 687b ldr r3, [r7, #4] + 8005be6: 735a strb r2, [r3, #13] + pWirelessInfo->FusMemorySizeSram2A = ((fus_memorySize & INFO_SIZE_SRAM2A_MASK) >> INFO_SIZE_SRAM2A_OFFSET); + 8005be8: 697b ldr r3, [r7, #20] + 8005bea: 0c1b lsrs r3, r3, #16 + 8005bec: b2da uxtb r2, r3 + 8005bee: 687b ldr r3, [r7, #4] + 8005bf0: 739a strb r2, [r3, #14] + pWirelessInfo->FusMemorySizeFlash = ((fus_memorySize & INFO_SIZE_FLASH_MASK) >> INFO_SIZE_FLASH_OFFSET); + 8005bf2: 697b ldr r3, [r7, #20] + 8005bf4: b2da uxtb r2, r3 + 8005bf6: 687b ldr r3, [r7, #4] + 8005bf8: 73da strb r2, [r3, #15] + + return (SHCI_Success); + 8005bfa: 2300 movs r3, #0 +} + 8005bfc: 4618 mov r0, r3 + 8005bfe: 372c adds r7, #44 @ 0x2c + 8005c00: 46bd mov sp, r7 + 8005c02: f85d 7b04 ldr.w r7, [sp], #4 + 8005c06: 4770 bx lr + 8005c08: 58004000 .word 0x58004000 + 8005c0c: a94656b9 .word 0xa94656b9 + +08005c10 <hci_init>: +static void TlEvtReceived(TL_EvtPacket_t *hcievt); +static void TlInit( TL_CmdPacket_t * p_cmdbuffer ); + +/* Interface ------- ---------------------------------------------------------*/ +void hci_init(void(* UserEvtRx)(void* pData), void* pConf) +{ + 8005c10: b580 push {r7, lr} + 8005c12: b082 sub sp, #8 + 8005c14: af00 add r7, sp, #0 + 8005c16: 6078 str r0, [r7, #4] + 8005c18: 6039 str r1, [r7, #0] + StatusNotCallBackFunction = ((HCI_TL_HciInitConf_t *)pConf)->StatusNotCallBack; + 8005c1a: 683b ldr r3, [r7, #0] + 8005c1c: 685b ldr r3, [r3, #4] + 8005c1e: 4a08 ldr r2, [pc, #32] @ (8005c40 <hci_init+0x30>) + 8005c20: 6013 str r3, [r2, #0] + hciContext.UserEvtRx = UserEvtRx; + 8005c22: 4a08 ldr r2, [pc, #32] @ (8005c44 <hci_init+0x34>) + 8005c24: 687b ldr r3, [r7, #4] + 8005c26: 61d3 str r3, [r2, #28] + + hci_register_io_bus (&hciContext.io); + 8005c28: 4806 ldr r0, [pc, #24] @ (8005c44 <hci_init+0x34>) + 8005c2a: f000 f979 bl 8005f20 <hci_register_io_bus> + + TlInit((TL_CmdPacket_t *)(((HCI_TL_HciInitConf_t *)pConf)->p_cmdbuffer)); + 8005c2e: 683b ldr r3, [r7, #0] + 8005c30: 681b ldr r3, [r3, #0] + 8005c32: 4618 mov r0, r3 + 8005c34: f000 f8da bl 8005dec <TlInit> + + return; + 8005c38: bf00 nop +} + 8005c3a: 3708 adds r7, #8 + 8005c3c: 46bd mov sp, r7 + 8005c3e: bd80 pop {r7, pc} + 8005c40: 2000021c .word 0x2000021c + 8005c44: 200001f4 .word 0x200001f4 + +08005c48 <hci_user_evt_proc>: + +void hci_user_evt_proc(void) +{ + 8005c48: b580 push {r7, lr} + 8005c4a: b084 sub sp, #16 + 8005c4c: af00 add r7, sp, #0 + /** + * It is more secure to use LST_remove_head()/LST_insert_head() compare to LST_get_next_node()/LST_remove_node() + * in case the user overwrite the header where the next/prev pointers are located + */ + + if((LST_is_empty(&HciAsynchEventQueue) == FALSE) && (UserEventFlow != HCI_TL_UserEventFlow_Disable)) + 8005c4e: 4822 ldr r0, [pc, #136] @ (8005cd8 <hci_user_evt_proc+0x90>) + 8005c50: f000 fd3e bl 80066d0 <LST_is_empty> + 8005c54: 4603 mov r3, r0 + 8005c56: 2b00 cmp r3, #0 + 8005c58: d12b bne.n 8005cb2 <hci_user_evt_proc+0x6a> + 8005c5a: 4b20 ldr r3, [pc, #128] @ (8005cdc <hci_user_evt_proc+0x94>) + 8005c5c: 781b ldrb r3, [r3, #0] + 8005c5e: 2b00 cmp r3, #0 + 8005c60: d027 beq.n 8005cb2 <hci_user_evt_proc+0x6a> + { + LST_remove_head ( &HciAsynchEventQueue, (tListNode **)&phcievtbuffer ); + 8005c62: f107 030c add.w r3, r7, #12 + 8005c66: 4619 mov r1, r3 + 8005c68: 481b ldr r0, [pc, #108] @ (8005cd8 <hci_user_evt_proc+0x90>) + 8005c6a: f000 fdc0 bl 80067ee <LST_remove_head> + + if (hciContext.UserEvtRx != NULL) + 8005c6e: 4b1c ldr r3, [pc, #112] @ (8005ce0 <hci_user_evt_proc+0x98>) + 8005c70: 69db ldr r3, [r3, #28] + 8005c72: 2b00 cmp r3, #0 + 8005c74: d00c beq.n 8005c90 <hci_user_evt_proc+0x48> + { + UserEvtRxParam.pckt = phcievtbuffer; + 8005c76: 68fb ldr r3, [r7, #12] + 8005c78: 60bb str r3, [r7, #8] + UserEvtRxParam.status = HCI_TL_UserEventFlow_Enable; + 8005c7a: 2301 movs r3, #1 + 8005c7c: 713b strb r3, [r7, #4] + hciContext.UserEvtRx((void *)&UserEvtRxParam); + 8005c7e: 4b18 ldr r3, [pc, #96] @ (8005ce0 <hci_user_evt_proc+0x98>) + 8005c80: 69db ldr r3, [r3, #28] + 8005c82: 1d3a adds r2, r7, #4 + 8005c84: 4610 mov r0, r2 + 8005c86: 4798 blx r3 + UserEventFlow = UserEvtRxParam.status; + 8005c88: 793a ldrb r2, [r7, #4] + 8005c8a: 4b14 ldr r3, [pc, #80] @ (8005cdc <hci_user_evt_proc+0x94>) + 8005c8c: 701a strb r2, [r3, #0] + 8005c8e: e002 b.n 8005c96 <hci_user_evt_proc+0x4e> + } + else + { + UserEventFlow = HCI_TL_UserEventFlow_Enable; + 8005c90: 4b12 ldr r3, [pc, #72] @ (8005cdc <hci_user_evt_proc+0x94>) + 8005c92: 2201 movs r2, #1 + 8005c94: 701a strb r2, [r3, #0] + } + + if(UserEventFlow != HCI_TL_UserEventFlow_Disable) + 8005c96: 4b11 ldr r3, [pc, #68] @ (8005cdc <hci_user_evt_proc+0x94>) + 8005c98: 781b ldrb r3, [r3, #0] + 8005c9a: 2b00 cmp r3, #0 + 8005c9c: d004 beq.n 8005ca8 <hci_user_evt_proc+0x60> + { + TL_MM_EvtDone( phcievtbuffer ); + 8005c9e: 68fb ldr r3, [r7, #12] + 8005ca0: 4618 mov r0, r3 + 8005ca2: f000 fc11 bl 80064c8 <TL_MM_EvtDone> + 8005ca6: e004 b.n 8005cb2 <hci_user_evt_proc+0x6a> + else + { + /** + * put back the event in the queue + */ + LST_insert_head ( &HciAsynchEventQueue, (tListNode *)phcievtbuffer ); + 8005ca8: 68fb ldr r3, [r7, #12] + 8005caa: 4619 mov r1, r3 + 8005cac: 480a ldr r0, [pc, #40] @ (8005cd8 <hci_user_evt_proc+0x90>) + 8005cae: f000 fd31 bl 8006714 <LST_insert_head> + } + } + + if((LST_is_empty(&HciAsynchEventQueue) == FALSE) && (UserEventFlow != HCI_TL_UserEventFlow_Disable)) + 8005cb2: 4809 ldr r0, [pc, #36] @ (8005cd8 <hci_user_evt_proc+0x90>) + 8005cb4: f000 fd0c bl 80066d0 <LST_is_empty> + 8005cb8: 4603 mov r3, r0 + 8005cba: 2b00 cmp r3, #0 + 8005cbc: d107 bne.n 8005cce <hci_user_evt_proc+0x86> + 8005cbe: 4b07 ldr r3, [pc, #28] @ (8005cdc <hci_user_evt_proc+0x94>) + 8005cc0: 781b ldrb r3, [r3, #0] + 8005cc2: 2b00 cmp r3, #0 + 8005cc4: d003 beq.n 8005cce <hci_user_evt_proc+0x86> + { + hci_notify_asynch_evt((void*) &HciAsynchEventQueue); + 8005cc6: 4804 ldr r0, [pc, #16] @ (8005cd8 <hci_user_evt_proc+0x90>) + 8005cc8: f001 f8c9 bl 8006e5e <hci_notify_asynch_evt> + } + + + return; + 8005ccc: bf00 nop + 8005cce: bf00 nop +} + 8005cd0: 3710 adds r7, #16 + 8005cd2: 46bd mov sp, r7 + 8005cd4: bd80 pop {r7, pc} + 8005cd6: bf00 nop + 8005cd8: 2000005c .word 0x2000005c + 8005cdc: 20000068 .word 0x20000068 + 8005ce0: 200001f4 .word 0x200001f4 + +08005ce4 <hci_send_req>: + + return; +} + +int hci_send_req(struct hci_request *p_cmd, uint8_t async) +{ + 8005ce4: b580 push {r7, lr} + 8005ce6: b088 sub sp, #32 + 8005ce8: af00 add r7, sp, #0 + 8005cea: 6078 str r0, [r7, #4] + 8005cec: 460b mov r3, r1 + 8005cee: 70fb strb r3, [r7, #3] + TL_CsEvt_t *pcommand_status_event; + TL_EvtPacket_t *pevtpacket; + uint8_t hci_cmd_complete_return_parameters_length; + HCI_TL_CmdStatus_t local_cmd_status; + + NotifyCmdStatus(HCI_TL_CmdBusy); + 8005cf0: 2000 movs r0, #0 + 8005cf2: f000 f8d1 bl 8005e98 <NotifyCmdStatus> + local_cmd_status = HCI_TL_CmdBusy; + 8005cf6: 2300 movs r3, #0 + 8005cf8: 77fb strb r3, [r7, #31] + opcode = ((p_cmd->ocf) & 0x03ff) | ((p_cmd->ogf) << 10); + 8005cfa: 687b ldr r3, [r7, #4] + 8005cfc: 885b ldrh r3, [r3, #2] + 8005cfe: b21b sxth r3, r3 + 8005d00: f3c3 0309 ubfx r3, r3, #0, #10 + 8005d04: b21a sxth r2, r3 + 8005d06: 687b ldr r3, [r7, #4] + 8005d08: 881b ldrh r3, [r3, #0] + 8005d0a: b21b sxth r3, r3 + 8005d0c: 029b lsls r3, r3, #10 + 8005d0e: b21b sxth r3, r3 + 8005d10: 4313 orrs r3, r2 + 8005d12: b21b sxth r3, r3 + 8005d14: 83bb strh r3, [r7, #28] + + CmdRspStatusFlag = HCI_TL_CMD_RESP_WAIT; + 8005d16: 4b33 ldr r3, [pc, #204] @ (8005de4 <hci_send_req+0x100>) + 8005d18: 2201 movs r2, #1 + 8005d1a: 701a strb r2, [r3, #0] + SendCmd(opcode, p_cmd->clen, p_cmd->cparam); + 8005d1c: 687b ldr r3, [r7, #4] + 8005d1e: 68db ldr r3, [r3, #12] + 8005d20: b2d9 uxtb r1, r3 + 8005d22: 687b ldr r3, [r7, #4] + 8005d24: 689a ldr r2, [r3, #8] + 8005d26: 8bbb ldrh r3, [r7, #28] + 8005d28: 4618 mov r0, r3 + 8005d2a: f000 f88f bl 8005e4c <SendCmd> + + while(local_cmd_status == HCI_TL_CmdBusy) + 8005d2e: e04e b.n 8005dce <hci_send_req+0xea> + { + hci_cmd_resp_wait(HCI_TL_DEFAULT_TIMEOUT); + 8005d30: f248 00e8 movw r0, #33000 @ 0x80e8 + 8005d34: f001 f8aa bl 8006e8c <hci_cmd_resp_wait> + + /** + * Process Cmd Event + */ + while(LST_is_empty(&HciCmdEventQueue) == FALSE) + 8005d38: e043 b.n 8005dc2 <hci_send_req+0xde> + { + LST_remove_head (&HciCmdEventQueue, (tListNode **)&pevtpacket); + 8005d3a: f107 030c add.w r3, r7, #12 + 8005d3e: 4619 mov r1, r3 + 8005d40: 4829 ldr r0, [pc, #164] @ (8005de8 <hci_send_req+0x104>) + 8005d42: f000 fd54 bl 80067ee <LST_remove_head> + + if(pevtpacket->evtserial.evt.evtcode == TL_BLEEVT_CS_OPCODE) + 8005d46: 68fb ldr r3, [r7, #12] + 8005d48: 7a5b ldrb r3, [r3, #9] + 8005d4a: 2b0f cmp r3, #15 + 8005d4c: d114 bne.n 8005d78 <hci_send_req+0x94> + { + pcommand_status_event = (TL_CsEvt_t*)pevtpacket->evtserial.evt.payload; + 8005d4e: 68fb ldr r3, [r7, #12] + 8005d50: 330b adds r3, #11 + 8005d52: 613b str r3, [r7, #16] + if(pcommand_status_event->cmdcode == opcode) + 8005d54: 693b ldr r3, [r7, #16] + 8005d56: 885b ldrh r3, [r3, #2] + 8005d58: b29b uxth r3, r3 + 8005d5a: 8bba ldrh r2, [r7, #28] + 8005d5c: 429a cmp r2, r3 + 8005d5e: d104 bne.n 8005d6a <hci_send_req+0x86> + { + *(uint8_t *)(p_cmd->rparam) = pcommand_status_event->status; + 8005d60: 687b ldr r3, [r7, #4] + 8005d62: 691b ldr r3, [r3, #16] + 8005d64: 693a ldr r2, [r7, #16] + 8005d66: 7812 ldrb r2, [r2, #0] + 8005d68: 701a strb r2, [r3, #0] + } + + if(pcommand_status_event->numcmd != 0) + 8005d6a: 693b ldr r3, [r7, #16] + 8005d6c: 785b ldrb r3, [r3, #1] + 8005d6e: 2b00 cmp r3, #0 + 8005d70: d027 beq.n 8005dc2 <hci_send_req+0xde> + { + local_cmd_status = HCI_TL_CmdAvailable; + 8005d72: 2301 movs r3, #1 + 8005d74: 77fb strb r3, [r7, #31] + 8005d76: e024 b.n 8005dc2 <hci_send_req+0xde> + } + } + else + { + pcommand_complete_event = (TL_CcEvt_t*)pevtpacket->evtserial.evt.payload; + 8005d78: 68fb ldr r3, [r7, #12] + 8005d7a: 330b adds r3, #11 + 8005d7c: 61bb str r3, [r7, #24] + + if(pcommand_complete_event->cmdcode == opcode) + 8005d7e: 69bb ldr r3, [r7, #24] + 8005d80: f8b3 3001 ldrh.w r3, [r3, #1] + 8005d84: b29b uxth r3, r3 + 8005d86: 8bba ldrh r2, [r7, #28] + 8005d88: 429a cmp r2, r3 + 8005d8a: d114 bne.n 8005db6 <hci_send_req+0xd2> + { + hci_cmd_complete_return_parameters_length = pevtpacket->evtserial.evt.plen - TL_EVT_HDR_SIZE; + 8005d8c: 68fb ldr r3, [r7, #12] + 8005d8e: 7a9b ldrb r3, [r3, #10] + 8005d90: 3b03 subs r3, #3 + 8005d92: 75fb strb r3, [r7, #23] + p_cmd->rlen = MIN(hci_cmd_complete_return_parameters_length, p_cmd->rlen); + 8005d94: 687b ldr r3, [r7, #4] + 8005d96: 695a ldr r2, [r3, #20] + 8005d98: 7dfb ldrb r3, [r7, #23] + 8005d9a: 429a cmp r2, r3 + 8005d9c: bfa8 it ge + 8005d9e: 461a movge r2, r3 + 8005da0: 687b ldr r3, [r7, #4] + 8005da2: 615a str r2, [r3, #20] + memcpy(p_cmd->rparam, pcommand_complete_event->payload, p_cmd->rlen); + 8005da4: 687b ldr r3, [r7, #4] + 8005da6: 6918 ldr r0, [r3, #16] + 8005da8: 69bb ldr r3, [r7, #24] + 8005daa: 1cd9 adds r1, r3, #3 + 8005dac: 687b ldr r3, [r7, #4] + 8005dae: 695b ldr r3, [r3, #20] + 8005db0: 461a mov r2, r3 + 8005db2: f001 fee5 bl 8007b80 <memcpy> + } + + if(pcommand_complete_event->numcmd != 0) + 8005db6: 69bb ldr r3, [r7, #24] + 8005db8: 781b ldrb r3, [r3, #0] + 8005dba: 2b00 cmp r3, #0 + 8005dbc: d001 beq.n 8005dc2 <hci_send_req+0xde> + { + local_cmd_status = HCI_TL_CmdAvailable; + 8005dbe: 2301 movs r3, #1 + 8005dc0: 77fb strb r3, [r7, #31] + while(LST_is_empty(&HciCmdEventQueue) == FALSE) + 8005dc2: 4809 ldr r0, [pc, #36] @ (8005de8 <hci_send_req+0x104>) + 8005dc4: f000 fc84 bl 80066d0 <LST_is_empty> + 8005dc8: 4603 mov r3, r0 + 8005dca: 2b00 cmp r3, #0 + 8005dcc: d0b5 beq.n 8005d3a <hci_send_req+0x56> + while(local_cmd_status == HCI_TL_CmdBusy) + 8005dce: 7ffb ldrb r3, [r7, #31] + 8005dd0: 2b00 cmp r3, #0 + 8005dd2: d0ad beq.n 8005d30 <hci_send_req+0x4c> + } + } + } + } + + NotifyCmdStatus(HCI_TL_CmdAvailable); + 8005dd4: 2001 movs r0, #1 + 8005dd6: f000 f85f bl 8005e98 <NotifyCmdStatus> + + return 0; + 8005dda: 2300 movs r3, #0 +} + 8005ddc: 4618 mov r0, r3 + 8005dde: 3720 adds r7, #32 + 8005de0: 46bd mov sp, r7 + 8005de2: bd80 pop {r7, pc} + 8005de4: 20000220 .word 0x20000220 + 8005de8: 20000214 .word 0x20000214 + +08005dec <TlInit>: + +/* Private functions ---------------------------------------------------------*/ +static void TlInit( TL_CmdPacket_t * p_cmdbuffer ) +{ + 8005dec: b580 push {r7, lr} + 8005dee: b086 sub sp, #24 + 8005df0: af00 add r7, sp, #0 + 8005df2: 6078 str r0, [r7, #4] + TL_BLE_InitConf_t Conf; + + /** + * Always initialize the command event queue + */ + LST_init_head (&HciCmdEventQueue); + 8005df4: 480f ldr r0, [pc, #60] @ (8005e34 <TlInit+0x48>) + 8005df6: f000 fc5b bl 80066b0 <LST_init_head> + + pCmdBuffer = p_cmdbuffer; + 8005dfa: 4a0f ldr r2, [pc, #60] @ (8005e38 <TlInit+0x4c>) + 8005dfc: 687b ldr r3, [r7, #4] + 8005dfe: 6013 str r3, [r2, #0] + + LST_init_head (&HciAsynchEventQueue); + 8005e00: 480e ldr r0, [pc, #56] @ (8005e3c <TlInit+0x50>) + 8005e02: f000 fc55 bl 80066b0 <LST_init_head> + + UserEventFlow = HCI_TL_UserEventFlow_Enable; + 8005e06: 4b0e ldr r3, [pc, #56] @ (8005e40 <TlInit+0x54>) + 8005e08: 2201 movs r2, #1 + 8005e0a: 701a strb r2, [r3, #0] + + /* Initialize low level driver */ + if (hciContext.io.Init) + 8005e0c: 4b0d ldr r3, [pc, #52] @ (8005e44 <TlInit+0x58>) + 8005e0e: 681b ldr r3, [r3, #0] + 8005e10: 2b00 cmp r3, #0 + 8005e12: d00a beq.n 8005e2a <TlInit+0x3e> + { + + Conf.p_cmdbuffer = (uint8_t *)p_cmdbuffer; + 8005e14: 687b ldr r3, [r7, #4] + 8005e16: 613b str r3, [r7, #16] + Conf.IoBusEvtCallBack = TlEvtReceived; + 8005e18: 4b0b ldr r3, [pc, #44] @ (8005e48 <TlInit+0x5c>) + 8005e1a: 60bb str r3, [r7, #8] + hciContext.io.Init(&Conf); + 8005e1c: 4b09 ldr r3, [pc, #36] @ (8005e44 <TlInit+0x58>) + 8005e1e: 681b ldr r3, [r3, #0] + 8005e20: f107 0208 add.w r2, r7, #8 + 8005e24: 4610 mov r0, r2 + 8005e26: 4798 blx r3 + } + + return; + 8005e28: bf00 nop + 8005e2a: bf00 nop +} + 8005e2c: 3718 adds r7, #24 + 8005e2e: 46bd mov sp, r7 + 8005e30: bd80 pop {r7, pc} + 8005e32: bf00 nop + 8005e34: 20000214 .word 0x20000214 + 8005e38: 20000064 .word 0x20000064 + 8005e3c: 2000005c .word 0x2000005c + 8005e40: 20000068 .word 0x20000068 + 8005e44: 200001f4 .word 0x200001f4 + 8005e48: 08005ed9 .word 0x08005ed9 + +08005e4c <SendCmd>: + +static void SendCmd(uint16_t opcode, uint8_t plen, void *param) +{ + 8005e4c: b580 push {r7, lr} + 8005e4e: b082 sub sp, #8 + 8005e50: af00 add r7, sp, #0 + 8005e52: 4603 mov r3, r0 + 8005e54: 603a str r2, [r7, #0] + 8005e56: 80fb strh r3, [r7, #6] + 8005e58: 460b mov r3, r1 + 8005e5a: 717b strb r3, [r7, #5] + pCmdBuffer->cmdserial.cmd.cmdcode = opcode; + 8005e5c: 4b0c ldr r3, [pc, #48] @ (8005e90 <SendCmd+0x44>) + 8005e5e: 681b ldr r3, [r3, #0] + 8005e60: 88fa ldrh r2, [r7, #6] + 8005e62: f8a3 2009 strh.w r2, [r3, #9] + pCmdBuffer->cmdserial.cmd.plen = plen; + 8005e66: 4b0a ldr r3, [pc, #40] @ (8005e90 <SendCmd+0x44>) + 8005e68: 681b ldr r3, [r3, #0] + 8005e6a: 797a ldrb r2, [r7, #5] + 8005e6c: 72da strb r2, [r3, #11] + memcpy( pCmdBuffer->cmdserial.cmd.payload, param, plen ); + 8005e6e: 4b08 ldr r3, [pc, #32] @ (8005e90 <SendCmd+0x44>) + 8005e70: 681b ldr r3, [r3, #0] + 8005e72: 330c adds r3, #12 + 8005e74: 797a ldrb r2, [r7, #5] + 8005e76: 6839 ldr r1, [r7, #0] + 8005e78: 4618 mov r0, r3 + 8005e7a: f001 fe81 bl 8007b80 <memcpy> + + hciContext.io.Send(0,0); + 8005e7e: 4b05 ldr r3, [pc, #20] @ (8005e94 <SendCmd+0x48>) + 8005e80: 691b ldr r3, [r3, #16] + 8005e82: 2100 movs r1, #0 + 8005e84: 2000 movs r0, #0 + 8005e86: 4798 blx r3 + + return; + 8005e88: bf00 nop +} + 8005e8a: 3708 adds r7, #8 + 8005e8c: 46bd mov sp, r7 + 8005e8e: bd80 pop {r7, pc} + 8005e90: 20000064 .word 0x20000064 + 8005e94: 200001f4 .word 0x200001f4 + +08005e98 <NotifyCmdStatus>: + +static void NotifyCmdStatus(HCI_TL_CmdStatus_t hcicmdstatus) +{ + 8005e98: b580 push {r7, lr} + 8005e9a: b082 sub sp, #8 + 8005e9c: af00 add r7, sp, #0 + 8005e9e: 4603 mov r3, r0 + 8005ea0: 71fb strb r3, [r7, #7] + if(hcicmdstatus == HCI_TL_CmdBusy) + 8005ea2: 79fb ldrb r3, [r7, #7] + 8005ea4: 2b00 cmp r3, #0 + 8005ea6: d108 bne.n 8005eba <NotifyCmdStatus+0x22> + { + if(StatusNotCallBackFunction != 0) + 8005ea8: 4b0a ldr r3, [pc, #40] @ (8005ed4 <NotifyCmdStatus+0x3c>) + 8005eaa: 681b ldr r3, [r3, #0] + 8005eac: 2b00 cmp r3, #0 + 8005eae: d00d beq.n 8005ecc <NotifyCmdStatus+0x34> + { + StatusNotCallBackFunction(HCI_TL_CmdBusy); + 8005eb0: 4b08 ldr r3, [pc, #32] @ (8005ed4 <NotifyCmdStatus+0x3c>) + 8005eb2: 681b ldr r3, [r3, #0] + 8005eb4: 2000 movs r0, #0 + 8005eb6: 4798 blx r3 + { + StatusNotCallBackFunction(HCI_TL_CmdAvailable); + } + } + + return; + 8005eb8: e008 b.n 8005ecc <NotifyCmdStatus+0x34> + if(StatusNotCallBackFunction != 0) + 8005eba: 4b06 ldr r3, [pc, #24] @ (8005ed4 <NotifyCmdStatus+0x3c>) + 8005ebc: 681b ldr r3, [r3, #0] + 8005ebe: 2b00 cmp r3, #0 + 8005ec0: d004 beq.n 8005ecc <NotifyCmdStatus+0x34> + StatusNotCallBackFunction(HCI_TL_CmdAvailable); + 8005ec2: 4b04 ldr r3, [pc, #16] @ (8005ed4 <NotifyCmdStatus+0x3c>) + 8005ec4: 681b ldr r3, [r3, #0] + 8005ec6: 2001 movs r0, #1 + 8005ec8: 4798 blx r3 + return; + 8005eca: bf00 nop + 8005ecc: bf00 nop +} + 8005ece: 3708 adds r7, #8 + 8005ed0: 46bd mov sp, r7 + 8005ed2: bd80 pop {r7, pc} + 8005ed4: 2000021c .word 0x2000021c + +08005ed8 <TlEvtReceived>: + +static void TlEvtReceived(TL_EvtPacket_t *hcievt) +{ + 8005ed8: b580 push {r7, lr} + 8005eda: b082 sub sp, #8 + 8005edc: af00 add r7, sp, #0 + 8005ede: 6078 str r0, [r7, #4] + if ( ((hcievt->evtserial.evt.evtcode) == TL_BLEEVT_CS_OPCODE) || ((hcievt->evtserial.evt.evtcode) == TL_BLEEVT_CC_OPCODE ) ) + 8005ee0: 687b ldr r3, [r7, #4] + 8005ee2: 7a5b ldrb r3, [r3, #9] + 8005ee4: 2b0f cmp r3, #15 + 8005ee6: d003 beq.n 8005ef0 <TlEvtReceived+0x18> + 8005ee8: 687b ldr r3, [r7, #4] + 8005eea: 7a5b ldrb r3, [r3, #9] + 8005eec: 2b0e cmp r3, #14 + 8005eee: d107 bne.n 8005f00 <TlEvtReceived+0x28> + { + LST_insert_tail(&HciCmdEventQueue, (tListNode *)hcievt); + 8005ef0: 6879 ldr r1, [r7, #4] + 8005ef2: 4809 ldr r0, [pc, #36] @ (8005f18 <TlEvtReceived+0x40>) + 8005ef4: f000 fc34 bl 8006760 <LST_insert_tail> + hci_cmd_resp_release(0); /**< Notify the application a full Cmd Event has been received */ + 8005ef8: 2000 movs r0, #0 + 8005efa: f000 ffbc bl 8006e76 <hci_cmd_resp_release> + 8005efe: e006 b.n 8005f0e <TlEvtReceived+0x36> + } + else + { + LST_insert_tail(&HciAsynchEventQueue, (tListNode *)hcievt); + 8005f00: 6879 ldr r1, [r7, #4] + 8005f02: 4806 ldr r0, [pc, #24] @ (8005f1c <TlEvtReceived+0x44>) + 8005f04: f000 fc2c bl 8006760 <LST_insert_tail> + hci_notify_asynch_evt((void*) &HciAsynchEventQueue); /**< Notify the application a full HCI event has been received */ + 8005f08: 4804 ldr r0, [pc, #16] @ (8005f1c <TlEvtReceived+0x44>) + 8005f0a: f000 ffa8 bl 8006e5e <hci_notify_asynch_evt> + } + + return; + 8005f0e: bf00 nop +} + 8005f10: 3708 adds r7, #8 + 8005f12: 46bd mov sp, r7 + 8005f14: bd80 pop {r7, pc} + 8005f16: bf00 nop + 8005f18: 20000214 .word 0x20000214 + 8005f1c: 2000005c .word 0x2000005c + +08005f20 <hci_register_io_bus>: +#include "hci_tl.h" +#include "tl.h" + + +void hci_register_io_bus(tHciIO* fops) +{ + 8005f20: b480 push {r7} + 8005f22: b083 sub sp, #12 + 8005f24: af00 add r7, sp, #0 + 8005f26: 6078 str r0, [r7, #4] + /* Register IO bus services */ + fops->Init = TL_BLE_Init; + 8005f28: 687b ldr r3, [r7, #4] + 8005f2a: 4a05 ldr r2, [pc, #20] @ (8005f40 <hci_register_io_bus+0x20>) + 8005f2c: 601a str r2, [r3, #0] + fops->Send = TL_BLE_SendCmd; + 8005f2e: 687b ldr r3, [r7, #4] + 8005f30: 4a04 ldr r2, [pc, #16] @ (8005f44 <hci_register_io_bus+0x24>) + 8005f32: 611a str r2, [r3, #16] + + return; + 8005f34: bf00 nop +} + 8005f36: 370c adds r7, #12 + 8005f38: 46bd mov sp, r7 + 8005f3a: f85d 7b04 ldr.w r7, [sp], #4 + 8005f3e: 4770 bx lr + 8005f40: 08006239 .word 0x08006239 + 8005f44: 080062a1 .word 0x080062a1 + +08005f48 <shci_init>: +static void TlUserEvtReceived(TL_EvtPacket_t *shcievt); +static void TlInit( TL_CmdPacket_t * p_cmdbuffer ); + +/* Interface ------- ---------------------------------------------------------*/ +void shci_init(void(* UserEvtRx)(void* pData), void* pConf) +{ + 8005f48: b580 push {r7, lr} + 8005f4a: b082 sub sp, #8 + 8005f4c: af00 add r7, sp, #0 + 8005f4e: 6078 str r0, [r7, #4] + 8005f50: 6039 str r1, [r7, #0] + StatusNotCallBackFunction = ((SHCI_TL_HciInitConf_t *)pConf)->StatusNotCallBack; + 8005f52: 683b ldr r3, [r7, #0] + 8005f54: 685b ldr r3, [r3, #4] + 8005f56: 4a08 ldr r2, [pc, #32] @ (8005f78 <shci_init+0x30>) + 8005f58: 6013 str r3, [r2, #0] + shciContext.UserEvtRx = UserEvtRx; + 8005f5a: 4a08 ldr r2, [pc, #32] @ (8005f7c <shci_init+0x34>) + 8005f5c: 687b ldr r3, [r7, #4] + 8005f5e: 61d3 str r3, [r2, #28] + + shci_register_io_bus (&shciContext.io); + 8005f60: 4806 ldr r0, [pc, #24] @ (8005f7c <shci_init+0x34>) + 8005f62: f000 f915 bl 8006190 <shci_register_io_bus> + + TlInit((TL_CmdPacket_t *)(((SHCI_TL_HciInitConf_t *)pConf)->p_cmdbuffer)); + 8005f66: 683b ldr r3, [r7, #0] + 8005f68: 681b ldr r3, [r3, #0] + 8005f6a: 4618 mov r0, r3 + 8005f6c: f000 f898 bl 80060a0 <TlInit> + + return; + 8005f70: bf00 nop +} + 8005f72: 3708 adds r7, #8 + 8005f74: 46bd mov sp, r7 + 8005f76: bd80 pop {r7, pc} + 8005f78: 20000244 .word 0x20000244 + 8005f7c: 20000224 .word 0x20000224 + +08005f80 <shci_user_evt_proc>: + +void shci_user_evt_proc(void) +{ + 8005f80: b580 push {r7, lr} + 8005f82: b084 sub sp, #16 + 8005f84: af00 add r7, sp, #0 + + /** + * It is more secure to use LST_remove_head()/LST_insert_head() compare to LST_get_next_node()/LST_remove_node() + * in case the user overwrite the header where the next/prev pointers are located + */ + if((LST_is_empty(&SHciAsynchEventQueue) == FALSE) && (SHCI_TL_UserEventFlow != SHCI_TL_UserEventFlow_Disable)) + 8005f86: 4822 ldr r0, [pc, #136] @ (8006010 <shci_user_evt_proc+0x90>) + 8005f88: f000 fba2 bl 80066d0 <LST_is_empty> + 8005f8c: 4603 mov r3, r0 + 8005f8e: 2b00 cmp r3, #0 + 8005f90: d12b bne.n 8005fea <shci_user_evt_proc+0x6a> + 8005f92: 4b20 ldr r3, [pc, #128] @ (8006014 <shci_user_evt_proc+0x94>) + 8005f94: 781b ldrb r3, [r3, #0] + 8005f96: 2b00 cmp r3, #0 + 8005f98: d027 beq.n 8005fea <shci_user_evt_proc+0x6a> + { + LST_remove_head ( &SHciAsynchEventQueue, (tListNode **)&phcievtbuffer ); + 8005f9a: f107 030c add.w r3, r7, #12 + 8005f9e: 4619 mov r1, r3 + 8005fa0: 481b ldr r0, [pc, #108] @ (8006010 <shci_user_evt_proc+0x90>) + 8005fa2: f000 fc24 bl 80067ee <LST_remove_head> + + if (shciContext.UserEvtRx != NULL) + 8005fa6: 4b1c ldr r3, [pc, #112] @ (8006018 <shci_user_evt_proc+0x98>) + 8005fa8: 69db ldr r3, [r3, #28] + 8005faa: 2b00 cmp r3, #0 + 8005fac: d00c beq.n 8005fc8 <shci_user_evt_proc+0x48> + { + UserEvtRxParam.pckt = phcievtbuffer; + 8005fae: 68fb ldr r3, [r7, #12] + 8005fb0: 60bb str r3, [r7, #8] + UserEvtRxParam.status = SHCI_TL_UserEventFlow_Enable; + 8005fb2: 2301 movs r3, #1 + 8005fb4: 713b strb r3, [r7, #4] + shciContext.UserEvtRx((void *)&UserEvtRxParam); + 8005fb6: 4b18 ldr r3, [pc, #96] @ (8006018 <shci_user_evt_proc+0x98>) + 8005fb8: 69db ldr r3, [r3, #28] + 8005fba: 1d3a adds r2, r7, #4 + 8005fbc: 4610 mov r0, r2 + 8005fbe: 4798 blx r3 + SHCI_TL_UserEventFlow = UserEvtRxParam.status; + 8005fc0: 793a ldrb r2, [r7, #4] + 8005fc2: 4b14 ldr r3, [pc, #80] @ (8006014 <shci_user_evt_proc+0x94>) + 8005fc4: 701a strb r2, [r3, #0] + 8005fc6: e002 b.n 8005fce <shci_user_evt_proc+0x4e> + } + else + { + SHCI_TL_UserEventFlow = SHCI_TL_UserEventFlow_Enable; + 8005fc8: 4b12 ldr r3, [pc, #72] @ (8006014 <shci_user_evt_proc+0x94>) + 8005fca: 2201 movs r2, #1 + 8005fcc: 701a strb r2, [r3, #0] + } + + if(SHCI_TL_UserEventFlow != SHCI_TL_UserEventFlow_Disable) + 8005fce: 4b11 ldr r3, [pc, #68] @ (8006014 <shci_user_evt_proc+0x94>) + 8005fd0: 781b ldrb r3, [r3, #0] + 8005fd2: 2b00 cmp r3, #0 + 8005fd4: d004 beq.n 8005fe0 <shci_user_evt_proc+0x60> + { + TL_MM_EvtDone( phcievtbuffer ); + 8005fd6: 68fb ldr r3, [r7, #12] + 8005fd8: 4618 mov r0, r3 + 8005fda: f000 fa75 bl 80064c8 <TL_MM_EvtDone> + 8005fde: e004 b.n 8005fea <shci_user_evt_proc+0x6a> + else + { + /** + * put back the event in the queue + */ + LST_insert_head ( &SHciAsynchEventQueue, (tListNode *)phcievtbuffer ); + 8005fe0: 68fb ldr r3, [r7, #12] + 8005fe2: 4619 mov r1, r3 + 8005fe4: 480a ldr r0, [pc, #40] @ (8006010 <shci_user_evt_proc+0x90>) + 8005fe6: f000 fb95 bl 8006714 <LST_insert_head> + } + } + + if((LST_is_empty(&SHciAsynchEventQueue) == FALSE) && (SHCI_TL_UserEventFlow != SHCI_TL_UserEventFlow_Disable)) + 8005fea: 4809 ldr r0, [pc, #36] @ (8006010 <shci_user_evt_proc+0x90>) + 8005fec: f000 fb70 bl 80066d0 <LST_is_empty> + 8005ff0: 4603 mov r3, r0 + 8005ff2: 2b00 cmp r3, #0 + 8005ff4: d107 bne.n 8006006 <shci_user_evt_proc+0x86> + 8005ff6: 4b07 ldr r3, [pc, #28] @ (8006014 <shci_user_evt_proc+0x94>) + 8005ff8: 781b ldrb r3, [r3, #0] + 8005ffa: 2b00 cmp r3, #0 + 8005ffc: d003 beq.n 8006006 <shci_user_evt_proc+0x86> + { + shci_notify_asynch_evt((void*) &SHciAsynchEventQueue); + 8005ffe: 4804 ldr r0, [pc, #16] @ (8006010 <shci_user_evt_proc+0x90>) + 8006000: f7fa fb07 bl 8000612 <shci_notify_asynch_evt> + } + + + return; + 8006004: bf00 nop + 8006006: bf00 nop +} + 8006008: 3710 adds r7, #16 + 800600a: 46bd mov sp, r7 + 800600c: bd80 pop {r7, pc} + 800600e: bf00 nop + 8006010: 2000006c .word 0x2000006c + 8006014: 2000007c .word 0x2000007c + 8006018: 20000224 .word 0x20000224 + +0800601c <shci_send>: + + return; +} + +void shci_send( uint16_t cmd_code, uint8_t len_cmd_payload, uint8_t * p_cmd_payload, TL_EvtPacket_t * p_rsp ) +{ + 800601c: b580 push {r7, lr} + 800601e: b084 sub sp, #16 + 8006020: af00 add r7, sp, #0 + 8006022: 60ba str r2, [r7, #8] + 8006024: 607b str r3, [r7, #4] + 8006026: 4603 mov r3, r0 + 8006028: 81fb strh r3, [r7, #14] + 800602a: 460b mov r3, r1 + 800602c: 737b strb r3, [r7, #13] + Cmd_SetStatus(SHCI_TL_CmdBusy); + 800602e: 2000 movs r0, #0 + 8006030: f000 f868 bl 8006104 <Cmd_SetStatus> + + pCmdBuffer->cmdserial.cmd.cmdcode = cmd_code; + 8006034: 4b17 ldr r3, [pc, #92] @ (8006094 <shci_send+0x78>) + 8006036: 681b ldr r3, [r3, #0] + 8006038: 89fa ldrh r2, [r7, #14] + 800603a: f8a3 2009 strh.w r2, [r3, #9] + pCmdBuffer->cmdserial.cmd.plen = len_cmd_payload; + 800603e: 4b15 ldr r3, [pc, #84] @ (8006094 <shci_send+0x78>) + 8006040: 681b ldr r3, [r3, #0] + 8006042: 7b7a ldrb r2, [r7, #13] + 8006044: 72da strb r2, [r3, #11] + + memcpy(pCmdBuffer->cmdserial.cmd.payload, p_cmd_payload, len_cmd_payload ); + 8006046: 4b13 ldr r3, [pc, #76] @ (8006094 <shci_send+0x78>) + 8006048: 681b ldr r3, [r3, #0] + 800604a: 330c adds r3, #12 + 800604c: 7b7a ldrb r2, [r7, #13] + 800604e: 68b9 ldr r1, [r7, #8] + 8006050: 4618 mov r0, r3 + 8006052: f001 fd95 bl 8007b80 <memcpy> + CmdRspStatusFlag = SHCI_TL_CMD_RESP_WAIT; + 8006056: 4b10 ldr r3, [pc, #64] @ (8006098 <shci_send+0x7c>) + 8006058: 2201 movs r2, #1 + 800605a: 701a strb r2, [r3, #0] + shciContext.io.Send(0,0); + 800605c: 4b0f ldr r3, [pc, #60] @ (800609c <shci_send+0x80>) + 800605e: 691b ldr r3, [r3, #16] + 8006060: 2100 movs r1, #0 + 8006062: 2000 movs r0, #0 + 8006064: 4798 blx r3 + + shci_cmd_resp_wait(SHCI_TL_DEFAULT_TIMEOUT); + 8006066: f248 00e8 movw r0, #33000 @ 0x80e8 + 800606a: f7fa fae9 bl 8000640 <shci_cmd_resp_wait> + + /** + * The command complete of a system command does not have the header + * It starts immediately with the evtserial field + */ + memcpy( &(p_rsp->evtserial), pCmdBuffer, ((TL_EvtSerial_t*)pCmdBuffer)->evt.plen + TL_EVT_HDR_SIZE ); + 800606e: 687b ldr r3, [r7, #4] + 8006070: f103 0008 add.w r0, r3, #8 + 8006074: 4b07 ldr r3, [pc, #28] @ (8006094 <shci_send+0x78>) + 8006076: 6819 ldr r1, [r3, #0] + 8006078: 4b06 ldr r3, [pc, #24] @ (8006094 <shci_send+0x78>) + 800607a: 681b ldr r3, [r3, #0] + 800607c: 789b ldrb r3, [r3, #2] + 800607e: 3303 adds r3, #3 + 8006080: 461a mov r2, r3 + 8006082: f001 fd7d bl 8007b80 <memcpy> + + Cmd_SetStatus(SHCI_TL_CmdAvailable); + 8006086: 2001 movs r0, #1 + 8006088: f000 f83c bl 8006104 <Cmd_SetStatus> + + return; + 800608c: bf00 nop +} + 800608e: 3710 adds r7, #16 + 8006090: 46bd mov sp, r7 + 8006092: bd80 pop {r7, pc} + 8006094: 20000078 .word 0x20000078 + 8006098: 20000248 .word 0x20000248 + 800609c: 20000224 .word 0x20000224 + +080060a0 <TlInit>: + +/* Private functions ---------------------------------------------------------*/ +static void TlInit( TL_CmdPacket_t * p_cmdbuffer ) +{ + 80060a0: b580 push {r7, lr} + 80060a2: b086 sub sp, #24 + 80060a4: af00 add r7, sp, #0 + 80060a6: 6078 str r0, [r7, #4] + TL_SYS_InitConf_t Conf; + + pCmdBuffer = p_cmdbuffer; + 80060a8: 4a10 ldr r2, [pc, #64] @ (80060ec <TlInit+0x4c>) + 80060aa: 687b ldr r3, [r7, #4] + 80060ac: 6013 str r3, [r2, #0] + + LST_init_head (&SHciAsynchEventQueue); + 80060ae: 4810 ldr r0, [pc, #64] @ (80060f0 <TlInit+0x50>) + 80060b0: f000 fafe bl 80066b0 <LST_init_head> + + Cmd_SetStatus(SHCI_TL_CmdAvailable); + 80060b4: 2001 movs r0, #1 + 80060b6: f000 f825 bl 8006104 <Cmd_SetStatus> + + SHCI_TL_UserEventFlow = SHCI_TL_UserEventFlow_Enable; + 80060ba: 4b0e ldr r3, [pc, #56] @ (80060f4 <TlInit+0x54>) + 80060bc: 2201 movs r2, #1 + 80060be: 701a strb r2, [r3, #0] + + /* Initialize low level driver */ + if (shciContext.io.Init) + 80060c0: 4b0d ldr r3, [pc, #52] @ (80060f8 <TlInit+0x58>) + 80060c2: 681b ldr r3, [r3, #0] + 80060c4: 2b00 cmp r3, #0 + 80060c6: d00c beq.n 80060e2 <TlInit+0x42> + { + + Conf.p_cmdbuffer = (uint8_t *)p_cmdbuffer; + 80060c8: 687b ldr r3, [r7, #4] + 80060ca: 617b str r3, [r7, #20] + Conf.IoBusCallBackCmdEvt = TlCmdEvtReceived; + 80060cc: 4b0b ldr r3, [pc, #44] @ (80060fc <TlInit+0x5c>) + 80060ce: 60fb str r3, [r7, #12] + Conf.IoBusCallBackUserEvt = TlUserEvtReceived; + 80060d0: 4b0b ldr r3, [pc, #44] @ (8006100 <TlInit+0x60>) + 80060d2: 613b str r3, [r7, #16] + shciContext.io.Init(&Conf); + 80060d4: 4b08 ldr r3, [pc, #32] @ (80060f8 <TlInit+0x58>) + 80060d6: 681b ldr r3, [r3, #0] + 80060d8: f107 020c add.w r2, r7, #12 + 80060dc: 4610 mov r0, r2 + 80060de: 4798 blx r3 + } + + return; + 80060e0: bf00 nop + 80060e2: bf00 nop +} + 80060e4: 3718 adds r7, #24 + 80060e6: 46bd mov sp, r7 + 80060e8: bd80 pop {r7, pc} + 80060ea: bf00 nop + 80060ec: 20000078 .word 0x20000078 + 80060f0: 2000006c .word 0x2000006c + 80060f4: 2000007c .word 0x2000007c + 80060f8: 20000224 .word 0x20000224 + 80060fc: 08006155 .word 0x08006155 + 8006100: 0800616d .word 0x0800616d + +08006104 <Cmd_SetStatus>: + +static void Cmd_SetStatus(SHCI_TL_CmdStatus_t shcicmdstatus) +{ + 8006104: b580 push {r7, lr} + 8006106: b082 sub sp, #8 + 8006108: af00 add r7, sp, #0 + 800610a: 4603 mov r3, r0 + 800610c: 71fb strb r3, [r7, #7] + if(shcicmdstatus == SHCI_TL_CmdBusy) + 800610e: 79fb ldrb r3, [r7, #7] + 8006110: 2b00 cmp r3, #0 + 8006112: d10b bne.n 800612c <Cmd_SetStatus+0x28> + { + if(StatusNotCallBackFunction != 0) + 8006114: 4b0d ldr r3, [pc, #52] @ (800614c <Cmd_SetStatus+0x48>) + 8006116: 681b ldr r3, [r3, #0] + 8006118: 2b00 cmp r3, #0 + 800611a: d003 beq.n 8006124 <Cmd_SetStatus+0x20> + { + StatusNotCallBackFunction( SHCI_TL_CmdBusy ); + 800611c: 4b0b ldr r3, [pc, #44] @ (800614c <Cmd_SetStatus+0x48>) + 800611e: 681b ldr r3, [r3, #0] + 8006120: 2000 movs r0, #0 + 8006122: 4798 blx r3 + } + SHCICmdStatus = SHCI_TL_CmdBusy; + 8006124: 4b0a ldr r3, [pc, #40] @ (8006150 <Cmd_SetStatus+0x4c>) + 8006126: 2200 movs r2, #0 + 8006128: 701a strb r2, [r3, #0] + { + StatusNotCallBackFunction( SHCI_TL_CmdAvailable ); + } + } + + return; + 800612a: e00b b.n 8006144 <Cmd_SetStatus+0x40> + SHCICmdStatus = SHCI_TL_CmdAvailable; + 800612c: 4b08 ldr r3, [pc, #32] @ (8006150 <Cmd_SetStatus+0x4c>) + 800612e: 2201 movs r2, #1 + 8006130: 701a strb r2, [r3, #0] + if(StatusNotCallBackFunction != 0) + 8006132: 4b06 ldr r3, [pc, #24] @ (800614c <Cmd_SetStatus+0x48>) + 8006134: 681b ldr r3, [r3, #0] + 8006136: 2b00 cmp r3, #0 + 8006138: d004 beq.n 8006144 <Cmd_SetStatus+0x40> + StatusNotCallBackFunction( SHCI_TL_CmdAvailable ); + 800613a: 4b04 ldr r3, [pc, #16] @ (800614c <Cmd_SetStatus+0x48>) + 800613c: 681b ldr r3, [r3, #0] + 800613e: 2001 movs r0, #1 + 8006140: 4798 blx r3 + return; + 8006142: bf00 nop + 8006144: bf00 nop +} + 8006146: 3708 adds r7, #8 + 8006148: 46bd mov sp, r7 + 800614a: bd80 pop {r7, pc} + 800614c: 20000244 .word 0x20000244 + 8006150: 20000074 .word 0x20000074 + +08006154 <TlCmdEvtReceived>: + +static void TlCmdEvtReceived(TL_EvtPacket_t *shcievt) +{ + 8006154: b580 push {r7, lr} + 8006156: b082 sub sp, #8 + 8006158: af00 add r7, sp, #0 + 800615a: 6078 str r0, [r7, #4] + (void)(shcievt); + shci_cmd_resp_release(0); /**< Notify the application the Cmd response has been received */ + 800615c: 2000 movs r0, #0 + 800615e: f7fa fa64 bl 800062a <shci_cmd_resp_release> + + return; + 8006162: bf00 nop +} + 8006164: 3708 adds r7, #8 + 8006166: 46bd mov sp, r7 + 8006168: bd80 pop {r7, pc} + ... + +0800616c <TlUserEvtReceived>: + +static void TlUserEvtReceived(TL_EvtPacket_t *shcievt) +{ + 800616c: b580 push {r7, lr} + 800616e: b082 sub sp, #8 + 8006170: af00 add r7, sp, #0 + 8006172: 6078 str r0, [r7, #4] + LST_insert_tail(&SHciAsynchEventQueue, (tListNode *)shcievt); + 8006174: 6879 ldr r1, [r7, #4] + 8006176: 4805 ldr r0, [pc, #20] @ (800618c <TlUserEvtReceived+0x20>) + 8006178: f000 faf2 bl 8006760 <LST_insert_tail> + shci_notify_asynch_evt((void*) &SHciAsynchEventQueue); /**< Notify the application a full HCI event has been received */ + 800617c: 4803 ldr r0, [pc, #12] @ (800618c <TlUserEvtReceived+0x20>) + 800617e: f7fa fa48 bl 8000612 <shci_notify_asynch_evt> + + return; + 8006182: bf00 nop +} + 8006184: 3708 adds r7, #8 + 8006186: 46bd mov sp, r7 + 8006188: bd80 pop {r7, pc} + 800618a: bf00 nop + 800618c: 2000006c .word 0x2000006c + +08006190 <shci_register_io_bus>: +#include "shci_tl.h" +#include "tl.h" + + +void shci_register_io_bus(tSHciIO* fops) +{ + 8006190: b480 push {r7} + 8006192: b083 sub sp, #12 + 8006194: af00 add r7, sp, #0 + 8006196: 6078 str r0, [r7, #4] + /* Register IO bus services */ + fops->Init = TL_SYS_Init; + 8006198: 687b ldr r3, [r7, #4] + 800619a: 4a05 ldr r2, [pc, #20] @ (80061b0 <shci_register_io_bus+0x20>) + 800619c: 601a str r2, [r3, #0] + fops->Send = TL_SYS_SendCmd; + 800619e: 687b ldr r3, [r7, #4] + 80061a0: 4a04 ldr r2, [pc, #16] @ (80061b4 <shci_register_io_bus+0x24>) + 80061a2: 611a str r2, [r3, #16] + + return; + 80061a4: bf00 nop +} + 80061a6: 370c adds r7, #12 + 80061a8: 46bd mov sp, r7 + 80061aa: f85d 7b04 ldr.w r7, [sp], #4 + 80061ae: 4770 bx lr + 80061b0: 08006355 .word 0x08006355 + 80061b4: 080063a9 .word 0x080063a9 + +080061b8 <TL_Enable>: + +/****************************************************************************** + * GENERAL - refer to AN5289 for functions description. + ******************************************************************************/ +void TL_Enable( void ) +{ + 80061b8: b580 push {r7, lr} + 80061ba: af00 add r7, sp, #0 + HW_IPCC_Enable(); + 80061bc: f001 f856 bl 800726c <HW_IPCC_Enable> + + return; + 80061c0: bf00 nop +} + 80061c2: bd80 pop {r7, pc} + +080061c4 <TL_Init>: + + +void TL_Init( void ) +{ + 80061c4: b580 push {r7, lr} + 80061c6: af00 add r7, sp, #0 + TL_RefTable.p_device_info_table = &TL_DeviceInfoTable; + 80061c8: 4b10 ldr r3, [pc, #64] @ (800620c <TL_Init+0x48>) + 80061ca: 4a11 ldr r2, [pc, #68] @ (8006210 <TL_Init+0x4c>) + 80061cc: 601a str r2, [r3, #0] + TL_RefTable.p_ble_table = &TL_BleTable; + 80061ce: 4b0f ldr r3, [pc, #60] @ (800620c <TL_Init+0x48>) + 80061d0: 4a10 ldr r2, [pc, #64] @ (8006214 <TL_Init+0x50>) + 80061d2: 605a str r2, [r3, #4] + TL_RefTable.p_thread_table = &TL_ThreadTable; + 80061d4: 4b0d ldr r3, [pc, #52] @ (800620c <TL_Init+0x48>) + 80061d6: 4a10 ldr r2, [pc, #64] @ (8006218 <TL_Init+0x54>) + 80061d8: 609a str r2, [r3, #8] + TL_RefTable.p_lld_tests_table = &TL_LldTestsTable; + 80061da: 4b0c ldr r3, [pc, #48] @ (800620c <TL_Init+0x48>) + 80061dc: 4a0f ldr r2, [pc, #60] @ (800621c <TL_Init+0x58>) + 80061de: 621a str r2, [r3, #32] + TL_RefTable.p_ble_lld_table = &TL_BleLldTable; + 80061e0: 4b0a ldr r3, [pc, #40] @ (800620c <TL_Init+0x48>) + 80061e2: 4a0f ldr r2, [pc, #60] @ (8006220 <TL_Init+0x5c>) + 80061e4: 625a str r2, [r3, #36] @ 0x24 + TL_RefTable.p_sys_table = &TL_SysTable; + 80061e6: 4b09 ldr r3, [pc, #36] @ (800620c <TL_Init+0x48>) + 80061e8: 4a0e ldr r2, [pc, #56] @ (8006224 <TL_Init+0x60>) + 80061ea: 60da str r2, [r3, #12] + TL_RefTable.p_mem_manager_table = &TL_MemManagerTable; + 80061ec: 4b07 ldr r3, [pc, #28] @ (800620c <TL_Init+0x48>) + 80061ee: 4a0e ldr r2, [pc, #56] @ (8006228 <TL_Init+0x64>) + 80061f0: 611a str r2, [r3, #16] + TL_RefTable.p_traces_table = &TL_TracesTable; + 80061f2: 4b06 ldr r3, [pc, #24] @ (800620c <TL_Init+0x48>) + 80061f4: 4a0d ldr r2, [pc, #52] @ (800622c <TL_Init+0x68>) + 80061f6: 615a str r2, [r3, #20] + TL_RefTable.p_mac_802_15_4_table = &TL_Mac_802_15_4_Table; + 80061f8: 4b04 ldr r3, [pc, #16] @ (800620c <TL_Init+0x48>) + 80061fa: 4a0d ldr r2, [pc, #52] @ (8006230 <TL_Init+0x6c>) + 80061fc: 619a str r2, [r3, #24] + TL_RefTable.p_zigbee_table = &TL_Zigbee_Table; + 80061fe: 4b03 ldr r3, [pc, #12] @ (800620c <TL_Init+0x48>) + 8006200: 4a0c ldr r2, [pc, #48] @ (8006234 <TL_Init+0x70>) + 8006202: 61da str r2, [r3, #28] + HW_IPCC_Init(); + 8006204: f001 f846 bl 8007294 <HW_IPCC_Init> + + return; + 8006208: bf00 nop +} + 800620a: bd80 pop {r7, pc} + 800620c: 20030000 .word 0x20030000 + 8006210: 20030028 .word 0x20030028 + 8006214: 20030048 .word 0x20030048 + 8006218: 20030058 .word 0x20030058 + 800621c: 20030068 .word 0x20030068 + 8006220: 20030070 .word 0x20030070 + 8006224: 20030078 .word 0x20030078 + 8006228: 20030080 .word 0x20030080 + 800622c: 2003009c .word 0x2003009c + 8006230: 200300a0 .word 0x200300a0 + 8006234: 200300ac .word 0x200300ac + +08006238 <TL_BLE_Init>: + +/****************************************************************************** + * BLE + ******************************************************************************/ +int32_t TL_BLE_Init( void* pConf ) +{ + 8006238: b580 push {r7, lr} + 800623a: b084 sub sp, #16 + 800623c: af00 add r7, sp, #0 + 800623e: 6078 str r0, [r7, #4] + MB_BleTable_t * p_bletable; + + TL_BLE_InitConf_t *pInitHciConf = (TL_BLE_InitConf_t *) pConf; + 8006240: 687b ldr r3, [r7, #4] + 8006242: 60fb str r3, [r7, #12] + + LST_init_head (&EvtQueue); + 8006244: 4811 ldr r0, [pc, #68] @ (800628c <TL_BLE_Init+0x54>) + 8006246: f000 fa33 bl 80066b0 <LST_init_head> + + p_bletable = TL_RefTable.p_ble_table; + 800624a: 4b11 ldr r3, [pc, #68] @ (8006290 <TL_BLE_Init+0x58>) + 800624c: 685b ldr r3, [r3, #4] + 800624e: 60bb str r3, [r7, #8] + + p_bletable->pcmd_buffer = pInitHciConf->p_cmdbuffer; + 8006250: 68fb ldr r3, [r7, #12] + 8006252: 689a ldr r2, [r3, #8] + 8006254: 68bb ldr r3, [r7, #8] + 8006256: 601a str r2, [r3, #0] + p_bletable->phci_acl_data_buffer = pInitHciConf->p_AclDataBuffer; + 8006258: 68fb ldr r3, [r7, #12] + 800625a: 68da ldr r2, [r3, #12] + 800625c: 68bb ldr r3, [r7, #8] + 800625e: 60da str r2, [r3, #12] + p_bletable->pcs_buffer = (uint8_t*)CsBuffer; + 8006260: 68bb ldr r3, [r7, #8] + 8006262: 4a0c ldr r2, [pc, #48] @ (8006294 <TL_BLE_Init+0x5c>) + 8006264: 605a str r2, [r3, #4] + p_bletable->pevt_queue = (uint8_t*)&EvtQueue; + 8006266: 68bb ldr r3, [r7, #8] + 8006268: 4a08 ldr r2, [pc, #32] @ (800628c <TL_BLE_Init+0x54>) + 800626a: 609a str r2, [r3, #8] + + HW_IPCC_BLE_Init(); + 800626c: f001 f828 bl 80072c0 <HW_IPCC_BLE_Init> + + BLE_IoBusEvtCallBackFunction = pInitHciConf->IoBusEvtCallBack; + 8006270: 68fb ldr r3, [r7, #12] + 8006272: 681b ldr r3, [r3, #0] + 8006274: 4a08 ldr r2, [pc, #32] @ (8006298 <TL_BLE_Init+0x60>) + 8006276: 6013 str r3, [r2, #0] + BLE_IoBusAclDataTxAck = pInitHciConf->IoBusAclDataTxAck; + 8006278: 68fb ldr r3, [r7, #12] + 800627a: 685b ldr r3, [r3, #4] + 800627c: 4a07 ldr r2, [pc, #28] @ (800629c <TL_BLE_Init+0x64>) + 800627e: 6013 str r3, [r2, #0] + + return 0; + 8006280: 2300 movs r3, #0 +} + 8006282: 4618 mov r0, r3 + 8006284: 3710 adds r7, #16 + 8006286: 46bd mov sp, r7 + 8006288: bd80 pop {r7, pc} + 800628a: bf00 nop + 800628c: 200300c8 .word 0x200300c8 + 8006290: 20030000 .word 0x20030000 + 8006294: 20030a58 .word 0x20030a58 + 8006298: 20000254 .word 0x20000254 + 800629c: 20000258 .word 0x20000258 + +080062a0 <TL_BLE_SendCmd>: + +int32_t TL_BLE_SendCmd( uint8_t* buffer, uint16_t size ) +{ + 80062a0: b580 push {r7, lr} + 80062a2: b082 sub sp, #8 + 80062a4: af00 add r7, sp, #0 + 80062a6: 6078 str r0, [r7, #4] + 80062a8: 460b mov r3, r1 + 80062aa: 807b strh r3, [r7, #2] + (void)(buffer); + (void)(size); + + ((TL_CmdPacket_t*)(TL_RefTable.p_ble_table->pcmd_buffer))->cmdserial.type = TL_BLECMD_PKT_TYPE; + 80062ac: 4b09 ldr r3, [pc, #36] @ (80062d4 <TL_BLE_SendCmd+0x34>) + 80062ae: 685b ldr r3, [r3, #4] + 80062b0: 681b ldr r3, [r3, #0] + 80062b2: 2201 movs r2, #1 + 80062b4: 721a strb r2, [r3, #8] + + OutputDbgTrace(TL_MB_BLE_CMD, TL_RefTable.p_ble_table->pcmd_buffer); + 80062b6: 4b07 ldr r3, [pc, #28] @ (80062d4 <TL_BLE_SendCmd+0x34>) + 80062b8: 685b ldr r3, [r3, #4] + 80062ba: 681b ldr r3, [r3, #0] + 80062bc: 4619 mov r1, r3 + 80062be: 2001 movs r0, #1 + 80062c0: f000 f970 bl 80065a4 <OutputDbgTrace> + + HW_IPCC_BLE_SendCmd(); + 80062c4: f001 f816 bl 80072f4 <HW_IPCC_BLE_SendCmd> + + return 0; + 80062c8: 2300 movs r3, #0 +} + 80062ca: 4618 mov r0, r3 + 80062cc: 3708 adds r7, #8 + 80062ce: 46bd mov sp, r7 + 80062d0: bd80 pop {r7, pc} + 80062d2: bf00 nop + 80062d4: 20030000 .word 0x20030000 + +080062d8 <HW_IPCC_BLE_RxEvtNot>: + +void HW_IPCC_BLE_RxEvtNot(void) +{ + 80062d8: b580 push {r7, lr} + 80062da: b082 sub sp, #8 + 80062dc: af00 add r7, sp, #0 + TL_EvtPacket_t *phcievt; + + while(LST_is_empty(&EvtQueue) == FALSE) + 80062de: e01c b.n 800631a <HW_IPCC_BLE_RxEvtNot+0x42> + { + LST_remove_head (&EvtQueue, (tListNode **)&phcievt); + 80062e0: 1d3b adds r3, r7, #4 + 80062e2: 4619 mov r1, r3 + 80062e4: 4812 ldr r0, [pc, #72] @ (8006330 <HW_IPCC_BLE_RxEvtNot+0x58>) + 80062e6: f000 fa82 bl 80067ee <LST_remove_head> + + if ( ((phcievt->evtserial.evt.evtcode) == TL_BLEEVT_CS_OPCODE) || ((phcievt->evtserial.evt.evtcode) == TL_BLEEVT_CC_OPCODE ) ) + 80062ea: 687b ldr r3, [r7, #4] + 80062ec: 7a5b ldrb r3, [r3, #9] + 80062ee: 2b0f cmp r3, #15 + 80062f0: d003 beq.n 80062fa <HW_IPCC_BLE_RxEvtNot+0x22> + 80062f2: 687b ldr r3, [r7, #4] + 80062f4: 7a5b ldrb r3, [r3, #9] + 80062f6: 2b0e cmp r3, #14 + 80062f8: d105 bne.n 8006306 <HW_IPCC_BLE_RxEvtNot+0x2e> + { + OutputDbgTrace(TL_MB_BLE_CMD_RSP, (uint8_t*)phcievt); + 80062fa: 687b ldr r3, [r7, #4] + 80062fc: 4619 mov r1, r3 + 80062fe: 2002 movs r0, #2 + 8006300: f000 f950 bl 80065a4 <OutputDbgTrace> + 8006304: e004 b.n 8006310 <HW_IPCC_BLE_RxEvtNot+0x38> + } + else + { + OutputDbgTrace(TL_MB_BLE_ASYNCH_EVT, (uint8_t*)phcievt); + 8006306: 687b ldr r3, [r7, #4] + 8006308: 4619 mov r1, r3 + 800630a: 2005 movs r0, #5 + 800630c: f000 f94a bl 80065a4 <OutputDbgTrace> + } + + BLE_IoBusEvtCallBackFunction(phcievt); + 8006310: 4b08 ldr r3, [pc, #32] @ (8006334 <HW_IPCC_BLE_RxEvtNot+0x5c>) + 8006312: 681b ldr r3, [r3, #0] + 8006314: 687a ldr r2, [r7, #4] + 8006316: 4610 mov r0, r2 + 8006318: 4798 blx r3 + while(LST_is_empty(&EvtQueue) == FALSE) + 800631a: 4805 ldr r0, [pc, #20] @ (8006330 <HW_IPCC_BLE_RxEvtNot+0x58>) + 800631c: f000 f9d8 bl 80066d0 <LST_is_empty> + 8006320: 4603 mov r3, r0 + 8006322: 2b00 cmp r3, #0 + 8006324: d0dc beq.n 80062e0 <HW_IPCC_BLE_RxEvtNot+0x8> + } + + return; + 8006326: bf00 nop +} + 8006328: 3708 adds r7, #8 + 800632a: 46bd mov sp, r7 + 800632c: bd80 pop {r7, pc} + 800632e: bf00 nop + 8006330: 200300c8 .word 0x200300c8 + 8006334: 20000254 .word 0x20000254 + +08006338 <HW_IPCC_BLE_AclDataAckNot>: + + return 0; +} + +void HW_IPCC_BLE_AclDataAckNot(void) +{ + 8006338: b580 push {r7, lr} + 800633a: af00 add r7, sp, #0 + OutputDbgTrace(TL_MB_ACL_DATA_RSP, (uint8_t*)NULL); + 800633c: 2100 movs r1, #0 + 800633e: 2004 movs r0, #4 + 8006340: f000 f930 bl 80065a4 <OutputDbgTrace> + + BLE_IoBusAclDataTxAck( ); + 8006344: 4b02 ldr r3, [pc, #8] @ (8006350 <HW_IPCC_BLE_AclDataAckNot+0x18>) + 8006346: 681b ldr r3, [r3, #0] + 8006348: 4798 blx r3 + + return; + 800634a: bf00 nop +} + 800634c: bd80 pop {r7, pc} + 800634e: bf00 nop + 8006350: 20000258 .word 0x20000258 + +08006354 <TL_SYS_Init>: + +/****************************************************************************** + * SYSTEM + ******************************************************************************/ +int32_t TL_SYS_Init( void* pConf ) +{ + 8006354: b580 push {r7, lr} + 8006356: b084 sub sp, #16 + 8006358: af00 add r7, sp, #0 + 800635a: 6078 str r0, [r7, #4] + MB_SysTable_t * p_systable; + + TL_SYS_InitConf_t *pInitHciConf = (TL_SYS_InitConf_t *) pConf; + 800635c: 687b ldr r3, [r7, #4] + 800635e: 60fb str r3, [r7, #12] + + LST_init_head (&SystemEvtQueue); + 8006360: 480d ldr r0, [pc, #52] @ (8006398 <TL_SYS_Init+0x44>) + 8006362: f000 f9a5 bl 80066b0 <LST_init_head> + p_systable = TL_RefTable.p_sys_table; + 8006366: 4b0d ldr r3, [pc, #52] @ (800639c <TL_SYS_Init+0x48>) + 8006368: 68db ldr r3, [r3, #12] + 800636a: 60bb str r3, [r7, #8] + p_systable->pcmd_buffer = pInitHciConf->p_cmdbuffer; + 800636c: 68fb ldr r3, [r7, #12] + 800636e: 689a ldr r2, [r3, #8] + 8006370: 68bb ldr r3, [r7, #8] + 8006372: 601a str r2, [r3, #0] + p_systable->sys_queue = (uint8_t*)&SystemEvtQueue; + 8006374: 68bb ldr r3, [r7, #8] + 8006376: 4a08 ldr r2, [pc, #32] @ (8006398 <TL_SYS_Init+0x44>) + 8006378: 605a str r2, [r3, #4] + + HW_IPCC_SYS_Init(); + 800637a: f000 ffed bl 8007358 <HW_IPCC_SYS_Init> + + SYS_CMD_IoBusCallBackFunction = pInitHciConf->IoBusCallBackCmdEvt; + 800637e: 68fb ldr r3, [r7, #12] + 8006380: 681b ldr r3, [r3, #0] + 8006382: 4a07 ldr r2, [pc, #28] @ (80063a0 <TL_SYS_Init+0x4c>) + 8006384: 6013 str r3, [r2, #0] + SYS_EVT_IoBusCallBackFunction = pInitHciConf->IoBusCallBackUserEvt; + 8006386: 68fb ldr r3, [r7, #12] + 8006388: 685b ldr r3, [r3, #4] + 800638a: 4a06 ldr r2, [pc, #24] @ (80063a4 <TL_SYS_Init+0x50>) + 800638c: 6013 str r3, [r2, #0] + + return 0; + 800638e: 2300 movs r3, #0 +} + 8006390: 4618 mov r0, r3 + 8006392: 3710 adds r7, #16 + 8006394: 46bd mov sp, r7 + 8006396: bd80 pop {r7, pc} + 8006398: 200300d0 .word 0x200300d0 + 800639c: 20030000 .word 0x20030000 + 80063a0: 2000025c .word 0x2000025c + 80063a4: 20000260 .word 0x20000260 + +080063a8 <TL_SYS_SendCmd>: + +int32_t TL_SYS_SendCmd( uint8_t* buffer, uint16_t size ) +{ + 80063a8: b580 push {r7, lr} + 80063aa: b082 sub sp, #8 + 80063ac: af00 add r7, sp, #0 + 80063ae: 6078 str r0, [r7, #4] + 80063b0: 460b mov r3, r1 + 80063b2: 807b strh r3, [r7, #2] + (void)(buffer); + (void)(size); + + ((TL_CmdPacket_t *)(TL_RefTable.p_sys_table->pcmd_buffer))->cmdserial.type = TL_SYSCMD_PKT_TYPE; + 80063b4: 4b09 ldr r3, [pc, #36] @ (80063dc <TL_SYS_SendCmd+0x34>) + 80063b6: 68db ldr r3, [r3, #12] + 80063b8: 681b ldr r3, [r3, #0] + 80063ba: 2210 movs r2, #16 + 80063bc: 721a strb r2, [r3, #8] + + OutputDbgTrace(TL_MB_SYS_CMD, TL_RefTable.p_sys_table->pcmd_buffer); + 80063be: 4b07 ldr r3, [pc, #28] @ (80063dc <TL_SYS_SendCmd+0x34>) + 80063c0: 68db ldr r3, [r3, #12] + 80063c2: 681b ldr r3, [r3, #0] + 80063c4: 4619 mov r1, r3 + 80063c6: 2006 movs r0, #6 + 80063c8: f000 f8ec bl 80065a4 <OutputDbgTrace> + + HW_IPCC_SYS_SendCmd(); + 80063cc: f000 ffde bl 800738c <HW_IPCC_SYS_SendCmd> + + return 0; + 80063d0: 2300 movs r3, #0 +} + 80063d2: 4618 mov r0, r3 + 80063d4: 3708 adds r7, #8 + 80063d6: 46bd mov sp, r7 + 80063d8: bd80 pop {r7, pc} + 80063da: bf00 nop + 80063dc: 20030000 .word 0x20030000 + +080063e0 <HW_IPCC_SYS_CmdEvtNot>: + +void HW_IPCC_SYS_CmdEvtNot(void) +{ + 80063e0: b580 push {r7, lr} + 80063e2: af00 add r7, sp, #0 + OutputDbgTrace(TL_MB_SYS_CMD_RSP, (uint8_t*)(TL_RefTable.p_sys_table->pcmd_buffer) ); + 80063e4: 4b07 ldr r3, [pc, #28] @ (8006404 <HW_IPCC_SYS_CmdEvtNot+0x24>) + 80063e6: 68db ldr r3, [r3, #12] + 80063e8: 681b ldr r3, [r3, #0] + 80063ea: 4619 mov r1, r3 + 80063ec: 2007 movs r0, #7 + 80063ee: f000 f8d9 bl 80065a4 <OutputDbgTrace> + + SYS_CMD_IoBusCallBackFunction( (TL_EvtPacket_t*)(TL_RefTable.p_sys_table->pcmd_buffer) ); + 80063f2: 4b05 ldr r3, [pc, #20] @ (8006408 <HW_IPCC_SYS_CmdEvtNot+0x28>) + 80063f4: 681b ldr r3, [r3, #0] + 80063f6: 4a03 ldr r2, [pc, #12] @ (8006404 <HW_IPCC_SYS_CmdEvtNot+0x24>) + 80063f8: 68d2 ldr r2, [r2, #12] + 80063fa: 6812 ldr r2, [r2, #0] + 80063fc: 4610 mov r0, r2 + 80063fe: 4798 blx r3 + + return; + 8006400: bf00 nop +} + 8006402: bd80 pop {r7, pc} + 8006404: 20030000 .word 0x20030000 + 8006408: 2000025c .word 0x2000025c + +0800640c <HW_IPCC_SYS_EvtNot>: + +void HW_IPCC_SYS_EvtNot( void ) +{ + 800640c: b580 push {r7, lr} + 800640e: b082 sub sp, #8 + 8006410: af00 add r7, sp, #0 + TL_EvtPacket_t *p_evt; + + while(LST_is_empty(&SystemEvtQueue) == FALSE) + 8006412: e00e b.n 8006432 <HW_IPCC_SYS_EvtNot+0x26> + { + LST_remove_head (&SystemEvtQueue, (tListNode **)&p_evt); + 8006414: 1d3b adds r3, r7, #4 + 8006416: 4619 mov r1, r3 + 8006418: 480b ldr r0, [pc, #44] @ (8006448 <HW_IPCC_SYS_EvtNot+0x3c>) + 800641a: f000 f9e8 bl 80067ee <LST_remove_head> + + OutputDbgTrace(TL_MB_SYS_ASYNCH_EVT, (uint8_t*)p_evt ); + 800641e: 687b ldr r3, [r7, #4] + 8006420: 4619 mov r1, r3 + 8006422: 2008 movs r0, #8 + 8006424: f000 f8be bl 80065a4 <OutputDbgTrace> + + SYS_EVT_IoBusCallBackFunction( p_evt ); + 8006428: 4b08 ldr r3, [pc, #32] @ (800644c <HW_IPCC_SYS_EvtNot+0x40>) + 800642a: 681b ldr r3, [r3, #0] + 800642c: 687a ldr r2, [r7, #4] + 800642e: 4610 mov r0, r2 + 8006430: 4798 blx r3 + while(LST_is_empty(&SystemEvtQueue) == FALSE) + 8006432: 4805 ldr r0, [pc, #20] @ (8006448 <HW_IPCC_SYS_EvtNot+0x3c>) + 8006434: f000 f94c bl 80066d0 <LST_is_empty> + 8006438: 4603 mov r3, r0 + 800643a: 2b00 cmp r3, #0 + 800643c: d0ea beq.n 8006414 <HW_IPCC_SYS_EvtNot+0x8> + } + + return; + 800643e: bf00 nop +} + 8006440: 3708 adds r7, #8 + 8006442: 46bd mov sp, r7 + 8006444: bd80 pop {r7, pc} + 8006446: bf00 nop + 8006448: 200300d0 .word 0x200300d0 + 800644c: 20000260 .word 0x20000260 + +08006450 <TL_MM_Init>: + +/****************************************************************************** + * MEMORY MANAGER + ******************************************************************************/ +void TL_MM_Init( TL_MM_Config_t *p_Config ) +{ + 8006450: b580 push {r7, lr} + 8006452: b082 sub sp, #8 + 8006454: af00 add r7, sp, #0 + 8006456: 6078 str r0, [r7, #4] + static MB_MemManagerTable_t * p_mem_manager_table; + + LST_init_head (&FreeBufQueue); + 8006458: 4817 ldr r0, [pc, #92] @ (80064b8 <TL_MM_Init+0x68>) + 800645a: f000 f929 bl 80066b0 <LST_init_head> + LST_init_head (&LocalFreeBufQueue); + 800645e: 4817 ldr r0, [pc, #92] @ (80064bc <TL_MM_Init+0x6c>) + 8006460: f000 f926 bl 80066b0 <LST_init_head> + + p_mem_manager_table = TL_RefTable.p_mem_manager_table; + 8006464: 4b16 ldr r3, [pc, #88] @ (80064c0 <TL_MM_Init+0x70>) + 8006466: 691b ldr r3, [r3, #16] + 8006468: 4a16 ldr r2, [pc, #88] @ (80064c4 <TL_MM_Init+0x74>) + 800646a: 6013 str r3, [r2, #0] + + p_mem_manager_table->blepool = p_Config->p_AsynchEvtPool; + 800646c: 4b15 ldr r3, [pc, #84] @ (80064c4 <TL_MM_Init+0x74>) + 800646e: 681b ldr r3, [r3, #0] + 8006470: 687a ldr r2, [r7, #4] + 8006472: 6892 ldr r2, [r2, #8] + 8006474: 609a str r2, [r3, #8] + p_mem_manager_table->blepoolsize = p_Config->AsynchEvtPoolSize; + 8006476: 4b13 ldr r3, [pc, #76] @ (80064c4 <TL_MM_Init+0x74>) + 8006478: 681b ldr r3, [r3, #0] + 800647a: 687a ldr r2, [r7, #4] + 800647c: 68d2 ldr r2, [r2, #12] + 800647e: 60da str r2, [r3, #12] + p_mem_manager_table->pevt_free_buffer_queue = (uint8_t*)&FreeBufQueue; + 8006480: 4b10 ldr r3, [pc, #64] @ (80064c4 <TL_MM_Init+0x74>) + 8006482: 681b ldr r3, [r3, #0] + 8006484: 4a0c ldr r2, [pc, #48] @ (80064b8 <TL_MM_Init+0x68>) + 8006486: 611a str r2, [r3, #16] + p_mem_manager_table->spare_ble_buffer = p_Config->p_BleSpareEvtBuffer; + 8006488: 4b0e ldr r3, [pc, #56] @ (80064c4 <TL_MM_Init+0x74>) + 800648a: 681b ldr r3, [r3, #0] + 800648c: 687a ldr r2, [r7, #4] + 800648e: 6812 ldr r2, [r2, #0] + 8006490: 601a str r2, [r3, #0] + p_mem_manager_table->spare_sys_buffer = p_Config->p_SystemSpareEvtBuffer; + 8006492: 4b0c ldr r3, [pc, #48] @ (80064c4 <TL_MM_Init+0x74>) + 8006494: 681b ldr r3, [r3, #0] + 8006496: 687a ldr r2, [r7, #4] + 8006498: 6852 ldr r2, [r2, #4] + 800649a: 605a str r2, [r3, #4] + p_mem_manager_table->traces_evt_pool = p_Config->p_TracesEvtPool; + 800649c: 4b09 ldr r3, [pc, #36] @ (80064c4 <TL_MM_Init+0x74>) + 800649e: 681b ldr r3, [r3, #0] + 80064a0: 687a ldr r2, [r7, #4] + 80064a2: 6912 ldr r2, [r2, #16] + 80064a4: 615a str r2, [r3, #20] + p_mem_manager_table->tracespoolsize = p_Config->TracesEvtPoolSize; + 80064a6: 4b07 ldr r3, [pc, #28] @ (80064c4 <TL_MM_Init+0x74>) + 80064a8: 681b ldr r3, [r3, #0] + 80064aa: 687a ldr r2, [r7, #4] + 80064ac: 6952 ldr r2, [r2, #20] + 80064ae: 619a str r2, [r3, #24] + + return; + 80064b0: bf00 nop +} + 80064b2: 3708 adds r7, #8 + 80064b4: 46bd mov sp, r7 + 80064b6: bd80 pop {r7, pc} + 80064b8: 200300b8 .word 0x200300b8 + 80064bc: 2000024c .word 0x2000024c + 80064c0: 20030000 .word 0x20030000 + 80064c4: 20000264 .word 0x20000264 + +080064c8 <TL_MM_EvtDone>: + +void TL_MM_EvtDone(TL_EvtPacket_t * phcievt) +{ + 80064c8: b580 push {r7, lr} + 80064ca: b082 sub sp, #8 + 80064cc: af00 add r7, sp, #0 + 80064ce: 6078 str r0, [r7, #4] + LST_insert_tail(&LocalFreeBufQueue, (tListNode *)phcievt); + 80064d0: 6879 ldr r1, [r7, #4] + 80064d2: 4807 ldr r0, [pc, #28] @ (80064f0 <TL_MM_EvtDone+0x28>) + 80064d4: f000 f944 bl 8006760 <LST_insert_tail> + + OutputDbgTrace(TL_MB_MM_RELEASE_BUFFER, (uint8_t*)phcievt); + 80064d8: 6879 ldr r1, [r7, #4] + 80064da: 2000 movs r0, #0 + 80064dc: f000 f862 bl 80065a4 <OutputDbgTrace> + + HW_IPCC_MM_SendFreeBuf( SendFreeBuf ); + 80064e0: 4804 ldr r0, [pc, #16] @ (80064f4 <TL_MM_EvtDone+0x2c>) + 80064e2: f000 ff99 bl 8007418 <HW_IPCC_MM_SendFreeBuf> + + return; + 80064e6: bf00 nop +} + 80064e8: 3708 adds r7, #8 + 80064ea: 46bd mov sp, r7 + 80064ec: bd80 pop {r7, pc} + 80064ee: bf00 nop + 80064f0: 2000024c .word 0x2000024c + 80064f4: 080064f9 .word 0x080064f9 + +080064f8 <SendFreeBuf>: + +static void SendFreeBuf( void ) +{ + 80064f8: b580 push {r7, lr} + 80064fa: b082 sub sp, #8 + 80064fc: af00 add r7, sp, #0 + tListNode *p_node; + + while ( FALSE == LST_is_empty (&LocalFreeBufQueue) ) + 80064fe: e00c b.n 800651a <SendFreeBuf+0x22> + { + LST_remove_head( &LocalFreeBufQueue, (tListNode **)&p_node ); + 8006500: 1d3b adds r3, r7, #4 + 8006502: 4619 mov r1, r3 + 8006504: 480a ldr r0, [pc, #40] @ (8006530 <SendFreeBuf+0x38>) + 8006506: f000 f972 bl 80067ee <LST_remove_head> + LST_insert_tail( (tListNode*)(TL_RefTable.p_mem_manager_table->pevt_free_buffer_queue), p_node ); + 800650a: 4b0a ldr r3, [pc, #40] @ (8006534 <SendFreeBuf+0x3c>) + 800650c: 691b ldr r3, [r3, #16] + 800650e: 691b ldr r3, [r3, #16] + 8006510: 687a ldr r2, [r7, #4] + 8006512: 4611 mov r1, r2 + 8006514: 4618 mov r0, r3 + 8006516: f000 f923 bl 8006760 <LST_insert_tail> + while ( FALSE == LST_is_empty (&LocalFreeBufQueue) ) + 800651a: 4805 ldr r0, [pc, #20] @ (8006530 <SendFreeBuf+0x38>) + 800651c: f000 f8d8 bl 80066d0 <LST_is_empty> + 8006520: 4603 mov r3, r0 + 8006522: 2b00 cmp r3, #0 + 8006524: d0ec beq.n 8006500 <SendFreeBuf+0x8> + } + + return; + 8006526: bf00 nop +} + 8006528: 3708 adds r7, #8 + 800652a: 46bd mov sp, r7 + 800652c: bd80 pop {r7, pc} + 800652e: bf00 nop + 8006530: 2000024c .word 0x2000024c + 8006534: 20030000 .word 0x20030000 + +08006538 <TL_TRACES_Init>: + +/****************************************************************************** + * TRACES + ******************************************************************************/ +void TL_TRACES_Init( void ) +{ + 8006538: b580 push {r7, lr} + 800653a: af00 add r7, sp, #0 + LST_init_head (&TracesEvtQueue); + 800653c: 4805 ldr r0, [pc, #20] @ (8006554 <TL_TRACES_Init+0x1c>) + 800653e: f000 f8b7 bl 80066b0 <LST_init_head> + + TL_RefTable.p_traces_table->traces_queue = (uint8_t*)&TracesEvtQueue; + 8006542: 4b05 ldr r3, [pc, #20] @ (8006558 <TL_TRACES_Init+0x20>) + 8006544: 695b ldr r3, [r3, #20] + 8006546: 4a03 ldr r2, [pc, #12] @ (8006554 <TL_TRACES_Init+0x1c>) + 8006548: 601a str r2, [r3, #0] + + HW_IPCC_TRACES_Init(); + 800654a: f000 ffb7 bl 80074bc <HW_IPCC_TRACES_Init> + + return; + 800654e: bf00 nop +} + 8006550: bd80 pop {r7, pc} + 8006552: bf00 nop + 8006554: 200300c0 .word 0x200300c0 + 8006558: 20030000 .word 0x20030000 + +0800655c <HW_IPCC_TRACES_EvtNot>: + +void HW_IPCC_TRACES_EvtNot(void) +{ + 800655c: b580 push {r7, lr} + 800655e: b082 sub sp, #8 + 8006560: af00 add r7, sp, #0 + TL_EvtPacket_t *phcievt; + + while(LST_is_empty(&TracesEvtQueue) == FALSE) + 8006562: e008 b.n 8006576 <HW_IPCC_TRACES_EvtNot+0x1a> + { + LST_remove_head (&TracesEvtQueue, (tListNode **)&phcievt); + 8006564: 1d3b adds r3, r7, #4 + 8006566: 4619 mov r1, r3 + 8006568: 4808 ldr r0, [pc, #32] @ (800658c <HW_IPCC_TRACES_EvtNot+0x30>) + 800656a: f000 f940 bl 80067ee <LST_remove_head> + TL_TRACES_EvtReceived( phcievt ); + 800656e: 687b ldr r3, [r7, #4] + 8006570: 4618 mov r0, r3 + 8006572: f000 f80d bl 8006590 <TL_TRACES_EvtReceived> + while(LST_is_empty(&TracesEvtQueue) == FALSE) + 8006576: 4805 ldr r0, [pc, #20] @ (800658c <HW_IPCC_TRACES_EvtNot+0x30>) + 8006578: f000 f8aa bl 80066d0 <LST_is_empty> + 800657c: 4603 mov r3, r0 + 800657e: 2b00 cmp r3, #0 + 8006580: d0f0 beq.n 8006564 <HW_IPCC_TRACES_EvtNot+0x8> + } + + return; + 8006582: bf00 nop +} + 8006584: 3708 adds r7, #8 + 8006586: 46bd mov sp, r7 + 8006588: bd80 pop {r7, pc} + 800658a: bf00 nop + 800658c: 200300c0 .word 0x200300c0 + +08006590 <TL_TRACES_EvtReceived>: + +__WEAK void TL_TRACES_EvtReceived( TL_EvtPacket_t * hcievt ) +{ + 8006590: b480 push {r7} + 8006592: b083 sub sp, #12 + 8006594: af00 add r7, sp, #0 + 8006596: 6078 str r0, [r7, #4] + (void)(hcievt); +} + 8006598: bf00 nop + 800659a: 370c adds r7, #12 + 800659c: 46bd mov sp, r7 + 800659e: f85d 7b04 ldr.w r7, [sp], #4 + 80065a2: 4770 bx lr + +080065a4 <OutputDbgTrace>: + +/****************************************************************************** +* DEBUG INFORMATION +******************************************************************************/ +static void OutputDbgTrace(TL_MB_PacketType_t packet_type, uint8_t* buffer) +{ + 80065a4: b480 push {r7} + 80065a6: b087 sub sp, #28 + 80065a8: af00 add r7, sp, #0 + 80065aa: 4603 mov r3, r0 + 80065ac: 6039 str r1, [r7, #0] + 80065ae: 71fb strb r3, [r7, #7] + TL_EvtPacket_t *p_evt_packet; + TL_CmdPacket_t *p_cmd_packet; + TL_AclDataPacket_t *p_acldata_packet; + TL_EvtSerial_t *p_cmd_rsp_packet; + + switch(packet_type) + 80065b0: 79fb ldrb r3, [r7, #7] + 80065b2: 2b08 cmp r3, #8 + 80065b4: d84c bhi.n 8006650 <OutputDbgTrace+0xac> + 80065b6: a201 add r2, pc, #4 @ (adr r2, 80065bc <OutputDbgTrace+0x18>) + 80065b8: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80065bc: 080065e1 .word 0x080065e1 + 80065c0: 08006605 .word 0x08006605 + 80065c4: 08006611 .word 0x08006611 + 80065c8: 0800660b .word 0x0800660b + 80065cc: 08006651 .word 0x08006651 + 80065d0: 08006625 .word 0x08006625 + 80065d4: 08006631 .word 0x08006631 + 80065d8: 08006637 .word 0x08006637 + 80065dc: 08006645 .word 0x08006645 + { + case TL_MB_MM_RELEASE_BUFFER: + p_evt_packet = (TL_EvtPacket_t*)buffer; + 80065e0: 683b ldr r3, [r7, #0] + 80065e2: 617b str r3, [r7, #20] + switch(p_evt_packet->evtserial.evt.evtcode) + 80065e4: 697b ldr r3, [r7, #20] + 80065e6: 7a5b ldrb r3, [r3, #9] + 80065e8: 2bff cmp r3, #255 @ 0xff + 80065ea: d005 beq.n 80065f8 <OutputDbgTrace+0x54> + 80065ec: 2bff cmp r3, #255 @ 0xff + 80065ee: dc05 bgt.n 80065fc <OutputDbgTrace+0x58> + 80065f0: 2b0e cmp r3, #14 + 80065f2: d005 beq.n 8006600 <OutputDbgTrace+0x5c> + 80065f4: 2b0f cmp r3, #15 + break; + + default: + TL_MM_DBG_MSG("mm evt released: 0x%02X", p_evt_packet->evtserial.evt.evtcode); + TL_MM_DBG_MSG(" buffer addr: 0x%08X", p_evt_packet); + break; + 80065f6: e001 b.n 80065fc <OutputDbgTrace+0x58> + break; + 80065f8: bf00 nop + 80065fa: e02a b.n 8006652 <OutputDbgTrace+0xae> + break; + 80065fc: bf00 nop + 80065fe: e028 b.n 8006652 <OutputDbgTrace+0xae> + break; + 8006600: bf00 nop + } + + TL_MM_DBG_MSG("\r\n"); + break; + 8006602: e026 b.n 8006652 <OutputDbgTrace+0xae> + + case TL_MB_BLE_CMD: + p_cmd_packet = (TL_CmdPacket_t*)buffer; + 8006604: 683b ldr r3, [r7, #0] + 8006606: 60fb str r3, [r7, #12] + TL_HCI_CMD_DBG_BUF(p_cmd_packet->cmdserial.cmd.payload, p_cmd_packet->cmdserial.cmd.plen, ""); + } + TL_HCI_CMD_DBG_MSG("\r\n"); + + TL_HCI_CMD_DBG_RAW(&p_cmd_packet->cmdserial, p_cmd_packet->cmdserial.cmd.plen+TL_CMD_HDR_SIZE); + break; + 8006608: e023 b.n 8006652 <OutputDbgTrace+0xae> + + case TL_MB_ACL_DATA: + (void)p_acldata_packet; + p_acldata_packet = (TL_AclDataPacket_t*)buffer; + 800660a: 683b ldr r3, [r7, #0] + 800660c: 60bb str r3, [r7, #8] + TL_HCI_CMD_DBG_MSG(" payload:"); + TL_HCI_CMD_DBG_BUF(p_acldata_packet->AclDataSerial.acl_data, p_acldata_packet->AclDataSerial.length, ""); + }*/ + TL_HCI_CMD_DBG_MSG("\r\n"); + /*TL_HCI_CMD_DBG_RAW(&p_acldata_packet->AclDataSerial, p_acldata_packet->AclDataSerial.length+TL_CMD_HDR_SIZE);*/ + break; + 800660e: e020 b.n 8006652 <OutputDbgTrace+0xae> + TL_HCI_CMD_DBG_MSG(" ACL Data Tx Ack received") + TL_HCI_CMD_DBG_MSG("\r\n"); + break; + + case TL_MB_BLE_CMD_RSP: + p_evt_packet = (TL_EvtPacket_t*)buffer; + 8006610: 683b ldr r3, [r7, #0] + 8006612: 617b str r3, [r7, #20] + switch(p_evt_packet->evtserial.evt.evtcode) + 8006614: 697b ldr r3, [r7, #20] + 8006616: 7a5b ldrb r3, [r3, #9] + 8006618: 2b0e cmp r3, #14 + 800661a: d001 beq.n 8006620 <OutputDbgTrace+0x7c> + 800661c: 2b0f cmp r3, #15 + } + break; + + default: + TL_HCI_CMD_DBG_MSG("unknown ble rsp received: %02X", p_evt_packet->evtserial.evt.evtcode); + break; + 800661e: e000 b.n 8006622 <OutputDbgTrace+0x7e> + break; + 8006620: bf00 nop + } + + TL_HCI_CMD_DBG_MSG("\r\n"); + + TL_HCI_CMD_DBG_RAW(&p_evt_packet->evtserial, p_evt_packet->evtserial.evt.plen+TL_EVT_HDR_SIZE); + break; + 8006622: e016 b.n 8006652 <OutputDbgTrace+0xae> + + case TL_MB_BLE_ASYNCH_EVT: + p_evt_packet = (TL_EvtPacket_t*)buffer; + 8006624: 683b ldr r3, [r7, #0] + 8006626: 617b str r3, [r7, #20] + if(p_evt_packet->evtserial.evt.evtcode != TL_BLEEVT_VS_OPCODE) + 8006628: 697b ldr r3, [r7, #20] + 800662a: 7a5b ldrb r3, [r3, #9] + 800662c: 2bff cmp r3, #255 @ 0xff + } + + TL_HCI_EVT_DBG_MSG("\r\n"); + + TL_HCI_EVT_DBG_RAW(&p_evt_packet->evtserial, p_evt_packet->evtserial.evt.plen+TL_EVT_HDR_SIZE); + break; + 800662e: e010 b.n 8006652 <OutputDbgTrace+0xae> + + case TL_MB_SYS_CMD: + p_cmd_packet = (TL_CmdPacket_t*)buffer; + 8006630: 683b ldr r3, [r7, #0] + 8006632: 60fb str r3, [r7, #12] + TL_SHCI_CMD_DBG_BUF(p_cmd_packet->cmdserial.cmd.payload, p_cmd_packet->cmdserial.cmd.plen, ""); + } + TL_SHCI_CMD_DBG_MSG("\r\n"); + + TL_SHCI_CMD_DBG_RAW(&p_cmd_packet->cmdserial, p_cmd_packet->cmdserial.cmd.plen+TL_CMD_HDR_SIZE); + break; + 8006634: e00d b.n 8006652 <OutputDbgTrace+0xae> + + case TL_MB_SYS_CMD_RSP: + p_cmd_rsp_packet = (TL_EvtSerial_t*)buffer; + 8006636: 683b ldr r3, [r7, #0] + 8006638: 613b str r3, [r7, #16] + switch(p_cmd_rsp_packet->evt.evtcode) + 800663a: 693b ldr r3, [r7, #16] + 800663c: 785b ldrb r3, [r3, #1] + 800663e: 2b0e cmp r3, #14 + } + break; + + default: + TL_SHCI_CMD_DBG_MSG("unknown sys rsp received: %02X", p_cmd_rsp_packet->evt.evtcode); + break; + 8006640: bf00 nop + } + + TL_SHCI_CMD_DBG_MSG("\r\n"); + + TL_SHCI_CMD_DBG_RAW(&p_cmd_rsp_packet->evt, p_cmd_rsp_packet->evt.plen+TL_EVT_HDR_SIZE); + break; + 8006642: e006 b.n 8006652 <OutputDbgTrace+0xae> + + case TL_MB_SYS_ASYNCH_EVT: + p_evt_packet = (TL_EvtPacket_t*)buffer; + 8006644: 683b ldr r3, [r7, #0] + 8006646: 617b str r3, [r7, #20] + if(p_evt_packet->evtserial.evt.evtcode != TL_BLEEVT_VS_OPCODE) + 8006648: 697b ldr r3, [r7, #20] + 800664a: 7a5b ldrb r3, [r3, #9] + 800664c: 2bff cmp r3, #255 @ 0xff + } + + TL_SHCI_EVT_DBG_MSG("\r\n"); + + TL_SHCI_EVT_DBG_RAW(&p_evt_packet->evtserial, p_evt_packet->evtserial.evt.plen+TL_EVT_HDR_SIZE); + break; + 800664e: e000 b.n 8006652 <OutputDbgTrace+0xae> + + default: + break; + 8006650: bf00 nop + } + + return; + 8006652: bf00 nop +} + 8006654: 371c adds r7, #28 + 8006656: 46bd mov sp, r7 + 8006658: f85d 7b04 ldr.w r7, [sp], #4 + 800665c: 4770 bx lr + 800665e: bf00 nop + +08006660 <OTP_Read>: +/* Global variables ----------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Functions Definition ------------------------------------------------------*/ + +uint8_t * OTP_Read( uint8_t id ) +{ + 8006660: b480 push {r7} + 8006662: b085 sub sp, #20 + 8006664: af00 add r7, sp, #0 + 8006666: 4603 mov r3, r0 + 8006668: 71fb strb r3, [r7, #7] + uint8_t *p_id; + + p_id = (uint8_t*)(CFG_OTP_END_ADRESS - 7) ; + 800666a: 4b0f ldr r3, [pc, #60] @ (80066a8 <OTP_Read+0x48>) + 800666c: 60fb str r3, [r7, #12] + + while( ((*( p_id + 7 )) != id) && ( p_id != (uint8_t*)CFG_OTP_BASE_ADDRESS) ) + 800666e: e002 b.n 8006676 <OTP_Read+0x16> + { + p_id -= 8 ; + 8006670: 68fb ldr r3, [r7, #12] + 8006672: 3b08 subs r3, #8 + 8006674: 60fb str r3, [r7, #12] + while( ((*( p_id + 7 )) != id) && ( p_id != (uint8_t*)CFG_OTP_BASE_ADDRESS) ) + 8006676: 68fb ldr r3, [r7, #12] + 8006678: 3307 adds r3, #7 + 800667a: 781b ldrb r3, [r3, #0] + 800667c: 79fa ldrb r2, [r7, #7] + 800667e: 429a cmp r2, r3 + 8006680: d003 beq.n 800668a <OTP_Read+0x2a> + 8006682: 68fb ldr r3, [r7, #12] + 8006684: 4a09 ldr r2, [pc, #36] @ (80066ac <OTP_Read+0x4c>) + 8006686: 4293 cmp r3, r2 + 8006688: d1f2 bne.n 8006670 <OTP_Read+0x10> + } + + if((*( p_id + 7 )) != id) + 800668a: 68fb ldr r3, [r7, #12] + 800668c: 3307 adds r3, #7 + 800668e: 781b ldrb r3, [r3, #0] + 8006690: 79fa ldrb r2, [r7, #7] + 8006692: 429a cmp r2, r3 + 8006694: d001 beq.n 800669a <OTP_Read+0x3a> + { + p_id = 0 ; + 8006696: 2300 movs r3, #0 + 8006698: 60fb str r3, [r7, #12] + } + + return p_id ; + 800669a: 68fb ldr r3, [r7, #12] +} + 800669c: 4618 mov r0, r3 + 800669e: 3714 adds r7, #20 + 80066a0: 46bd mov sp, r7 + 80066a2: f85d 7b04 ldr.w r7, [sp], #4 + 80066a6: 4770 bx lr + 80066a8: 1fff73f8 .word 0x1fff73f8 + 80066ac: 1fff7000 .word 0x1fff7000 + +080066b0 <LST_init_head>: + +/****************************************************************************** + * Function Definitions + ******************************************************************************/ +void LST_init_head (tListNode * listHead) +{ + 80066b0: b480 push {r7} + 80066b2: b083 sub sp, #12 + 80066b4: af00 add r7, sp, #0 + 80066b6: 6078 str r0, [r7, #4] + listHead->next = listHead; + 80066b8: 687b ldr r3, [r7, #4] + 80066ba: 687a ldr r2, [r7, #4] + 80066bc: 601a str r2, [r3, #0] + listHead->prev = listHead; + 80066be: 687b ldr r3, [r7, #4] + 80066c0: 687a ldr r2, [r7, #4] + 80066c2: 605a str r2, [r3, #4] +} + 80066c4: bf00 nop + 80066c6: 370c adds r7, #12 + 80066c8: 46bd mov sp, r7 + 80066ca: f85d 7b04 ldr.w r7, [sp], #4 + 80066ce: 4770 bx lr + +080066d0 <LST_is_empty>: + +uint8_t LST_is_empty (tListNode * listHead) +{ + 80066d0: b480 push {r7} + 80066d2: b087 sub sp, #28 + 80066d4: af00 add r7, sp, #0 + 80066d6: 6078 str r0, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 80066d8: f3ef 8310 mrs r3, PRIMASK + 80066dc: 60fb str r3, [r7, #12] + return(result); + 80066de: 68fb ldr r3, [r7, #12] + uint32_t primask_bit; + uint8_t return_value; + + primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ + 80066e0: 613b str r3, [r7, #16] + __ASM volatile ("cpsid i" : : : "memory"); + 80066e2: b672 cpsid i +} + 80066e4: bf00 nop + __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ + if(listHead->next == listHead) + 80066e6: 687b ldr r3, [r7, #4] + 80066e8: 681b ldr r3, [r3, #0] + 80066ea: 687a ldr r2, [r7, #4] + 80066ec: 429a cmp r2, r3 + 80066ee: d102 bne.n 80066f6 <LST_is_empty+0x26> + { + return_value = TRUE; + 80066f0: 2301 movs r3, #1 + 80066f2: 75fb strb r3, [r7, #23] + 80066f4: e001 b.n 80066fa <LST_is_empty+0x2a> + } + else + { + return_value = FALSE; + 80066f6: 2300 movs r3, #0 + 80066f8: 75fb strb r3, [r7, #23] + 80066fa: 693b ldr r3, [r7, #16] + 80066fc: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80066fe: 68bb ldr r3, [r7, #8] + 8006700: f383 8810 msr PRIMASK, r3 +} + 8006704: bf00 nop + } + __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ + + return return_value; + 8006706: 7dfb ldrb r3, [r7, #23] +} + 8006708: 4618 mov r0, r3 + 800670a: 371c adds r7, #28 + 800670c: 46bd mov sp, r7 + 800670e: f85d 7b04 ldr.w r7, [sp], #4 + 8006712: 4770 bx lr + +08006714 <LST_insert_head>: + +void LST_insert_head (tListNode * listHead, tListNode * node) +{ + 8006714: b480 push {r7} + 8006716: b087 sub sp, #28 + 8006718: af00 add r7, sp, #0 + 800671a: 6078 str r0, [r7, #4] + 800671c: 6039 str r1, [r7, #0] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800671e: f3ef 8310 mrs r3, PRIMASK + 8006722: 60fb str r3, [r7, #12] + return(result); + 8006724: 68fb ldr r3, [r7, #12] + uint32_t primask_bit; + + primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ + 8006726: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 8006728: b672 cpsid i +} + 800672a: bf00 nop + __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ + + node->next = listHead->next; + 800672c: 687b ldr r3, [r7, #4] + 800672e: 681a ldr r2, [r3, #0] + 8006730: 683b ldr r3, [r7, #0] + 8006732: 601a str r2, [r3, #0] + node->prev = listHead; + 8006734: 683b ldr r3, [r7, #0] + 8006736: 687a ldr r2, [r7, #4] + 8006738: 605a str r2, [r3, #4] + listHead->next = node; + 800673a: 687b ldr r3, [r7, #4] + 800673c: 683a ldr r2, [r7, #0] + 800673e: 601a str r2, [r3, #0] + (node->next)->prev = node; + 8006740: 683b ldr r3, [r7, #0] + 8006742: 681b ldr r3, [r3, #0] + 8006744: 683a ldr r2, [r7, #0] + 8006746: 605a str r2, [r3, #4] + 8006748: 697b ldr r3, [r7, #20] + 800674a: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800674c: 693b ldr r3, [r7, #16] + 800674e: f383 8810 msr PRIMASK, r3 +} + 8006752: bf00 nop + + __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ +} + 8006754: bf00 nop + 8006756: 371c adds r7, #28 + 8006758: 46bd mov sp, r7 + 800675a: f85d 7b04 ldr.w r7, [sp], #4 + 800675e: 4770 bx lr + +08006760 <LST_insert_tail>: + + +void LST_insert_tail (tListNode * listHead, tListNode * node) +{ + 8006760: b480 push {r7} + 8006762: b087 sub sp, #28 + 8006764: af00 add r7, sp, #0 + 8006766: 6078 str r0, [r7, #4] + 8006768: 6039 str r1, [r7, #0] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800676a: f3ef 8310 mrs r3, PRIMASK + 800676e: 60fb str r3, [r7, #12] + return(result); + 8006770: 68fb ldr r3, [r7, #12] + uint32_t primask_bit; + + primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ + 8006772: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 8006774: b672 cpsid i +} + 8006776: bf00 nop + __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ + + node->next = listHead; + 8006778: 683b ldr r3, [r7, #0] + 800677a: 687a ldr r2, [r7, #4] + 800677c: 601a str r2, [r3, #0] + node->prev = listHead->prev; + 800677e: 687b ldr r3, [r7, #4] + 8006780: 685a ldr r2, [r3, #4] + 8006782: 683b ldr r3, [r7, #0] + 8006784: 605a str r2, [r3, #4] + listHead->prev = node; + 8006786: 687b ldr r3, [r7, #4] + 8006788: 683a ldr r2, [r7, #0] + 800678a: 605a str r2, [r3, #4] + (node->prev)->next = node; + 800678c: 683b ldr r3, [r7, #0] + 800678e: 685b ldr r3, [r3, #4] + 8006790: 683a ldr r2, [r7, #0] + 8006792: 601a str r2, [r3, #0] + 8006794: 697b ldr r3, [r7, #20] + 8006796: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8006798: 693b ldr r3, [r7, #16] + 800679a: f383 8810 msr PRIMASK, r3 +} + 800679e: bf00 nop + + __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ +} + 80067a0: bf00 nop + 80067a2: 371c adds r7, #28 + 80067a4: 46bd mov sp, r7 + 80067a6: f85d 7b04 ldr.w r7, [sp], #4 + 80067aa: 4770 bx lr + +080067ac <LST_remove_node>: + + +void LST_remove_node (tListNode * node) +{ + 80067ac: b480 push {r7} + 80067ae: b087 sub sp, #28 + 80067b0: af00 add r7, sp, #0 + 80067b2: 6078 str r0, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 80067b4: f3ef 8310 mrs r3, PRIMASK + 80067b8: 60fb str r3, [r7, #12] + return(result); + 80067ba: 68fb ldr r3, [r7, #12] + uint32_t primask_bit; + + primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ + 80067bc: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 80067be: b672 cpsid i +} + 80067c0: bf00 nop + __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ + + (node->prev)->next = node->next; + 80067c2: 687b ldr r3, [r7, #4] + 80067c4: 685b ldr r3, [r3, #4] + 80067c6: 687a ldr r2, [r7, #4] + 80067c8: 6812 ldr r2, [r2, #0] + 80067ca: 601a str r2, [r3, #0] + (node->next)->prev = node->prev; + 80067cc: 687b ldr r3, [r7, #4] + 80067ce: 681b ldr r3, [r3, #0] + 80067d0: 687a ldr r2, [r7, #4] + 80067d2: 6852 ldr r2, [r2, #4] + 80067d4: 605a str r2, [r3, #4] + 80067d6: 697b ldr r3, [r7, #20] + 80067d8: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80067da: 693b ldr r3, [r7, #16] + 80067dc: f383 8810 msr PRIMASK, r3 +} + 80067e0: bf00 nop + + __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ +} + 80067e2: bf00 nop + 80067e4: 371c adds r7, #28 + 80067e6: 46bd mov sp, r7 + 80067e8: f85d 7b04 ldr.w r7, [sp], #4 + 80067ec: 4770 bx lr + +080067ee <LST_remove_head>: + + +void LST_remove_head (tListNode * listHead, tListNode ** node ) +{ + 80067ee: b580 push {r7, lr} + 80067f0: b086 sub sp, #24 + 80067f2: af00 add r7, sp, #0 + 80067f4: 6078 str r0, [r7, #4] + 80067f6: 6039 str r1, [r7, #0] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 80067f8: f3ef 8310 mrs r3, PRIMASK + 80067fc: 60fb str r3, [r7, #12] + return(result); + 80067fe: 68fb ldr r3, [r7, #12] + uint32_t primask_bit; + + primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ + 8006800: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 8006802: b672 cpsid i +} + 8006804: bf00 nop + __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ + + *node = listHead->next; + 8006806: 687b ldr r3, [r7, #4] + 8006808: 681a ldr r2, [r3, #0] + 800680a: 683b ldr r3, [r7, #0] + 800680c: 601a str r2, [r3, #0] + LST_remove_node (listHead->next); + 800680e: 687b ldr r3, [r7, #4] + 8006810: 681b ldr r3, [r3, #0] + 8006812: 4618 mov r0, r3 + 8006814: f7ff ffca bl 80067ac <LST_remove_node> + 8006818: 697b ldr r3, [r7, #20] + 800681a: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800681c: 693b ldr r3, [r7, #16] + 800681e: f383 8810 msr PRIMASK, r3 +} + 8006822: bf00 nop + + __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ +} + 8006824: bf00 nop + 8006826: 3718 adds r7, #24 + 8006828: 46bd mov sp, r7 + 800682a: bd80 pop {r7, pc} + +0800682c <LL_FLASH_GetUDN>: + * @note The 64-bit UID64 may be used by Firmware to derive BLE 48-bit Device Address EUI-48 or + * 802.15.4 64-bit Device Address EUI-64. + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_FLASH_GetUDN(void) +{ + 800682c: b480 push {r7} + 800682e: af00 add r7, sp, #0 + return (uint32_t)(READ_REG(*((uint32_t *)UID64_BASE))); + 8006830: 4b03 ldr r3, [pc, #12] @ (8006840 <LL_FLASH_GetUDN+0x14>) + 8006832: 681b ldr r3, [r3, #0] +} + 8006834: 4618 mov r0, r3 + 8006836: 46bd mov sp, r7 + 8006838: f85d 7b04 ldr.w r7, [sp], #4 + 800683c: 4770 bx lr + 800683e: bf00 nop + 8006840: 1fff7580 .word 0x1fff7580 + +08006844 <LL_FLASH_GetDeviceID>: + * 802.15.4 64-bit Device Address EUI-64. + * For STM32WBxxxx devices, the device ID is 0x26 + * @retval Values between Min_Data=0x00 and Max_Data=0xFF (ex: Device ID is 0x26 for STM32WB55x) + */ +__STATIC_INLINE uint32_t LL_FLASH_GetDeviceID(void) +{ + 8006844: b480 push {r7} + 8006846: af00 add r7, sp, #0 + return (uint32_t)((READ_REG(*((uint32_t *)UID64_BASE + 1U))) & 0x000000FFU); + 8006848: 4b03 ldr r3, [pc, #12] @ (8006858 <LL_FLASH_GetDeviceID+0x14>) + 800684a: 681b ldr r3, [r3, #0] + 800684c: b2db uxtb r3, r3 +} + 800684e: 4618 mov r0, r3 + 8006850: 46bd mov sp, r7 + 8006852: f85d 7b04 ldr.w r7, [sp], #4 + 8006856: 4770 bx lr + 8006858: 1fff7584 .word 0x1fff7584 + +0800685c <LL_FLASH_GetSTCompanyID>: + * 802.15.4 64-bit Device Address EUI-64. + * For STM32WBxxxx devices, the ST Company ID is 0x0080E1 + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFFFF (ex: ST Company ID is 0x0080E1) + */ +__STATIC_INLINE uint32_t LL_FLASH_GetSTCompanyID(void) +{ + 800685c: b480 push {r7} + 800685e: af00 add r7, sp, #0 + return (uint32_t)(((READ_REG(*((uint32_t *)UID64_BASE + 1U))) >> 8U) & 0x00FFFFFFU); + 8006860: 4b03 ldr r3, [pc, #12] @ (8006870 <LL_FLASH_GetSTCompanyID+0x14>) + 8006862: 681b ldr r3, [r3, #0] + 8006864: 0a1b lsrs r3, r3, #8 +} + 8006866: 4618 mov r0, r3 + 8006868: 46bd mov sp, r7 + 800686a: f85d 7b04 ldr.w r7, [sp], #4 + 800686e: 4770 bx lr + 8006870: 1fff7584 .word 0x1fff7584 + +08006874 <APP_BLE_Init>: + +/* USER CODE END EV */ + +/* Functions Definition ------------------------------------------------------*/ +void APP_BLE_Init(void) +{ + 8006874: b5b0 push {r4, r5, r7, lr} + 8006876: b090 sub sp, #64 @ 0x40 + 8006878: af00 add r7, sp, #0 + SHCI_CmdStatus_t status; +#if (RADIO_ACTIVITY_EVENT != 0) + tBleStatus ret = BLE_STATUS_INVALID_PARAMS; + 800687a: 2392 movs r3, #146 @ 0x92 + 800687c: f887 303f strb.w r3, [r7, #63] @ 0x3f +#endif /* RADIO_ACTIVITY_EVENT != 0 */ + /* USER CODE BEGIN APP_BLE_Init_1 */ + + /* USER CODE END APP_BLE_Init_1 */ + SHCI_C2_Ble_Init_Cmd_Packet_t ble_init_cmd_packet = + 8006880: 4b2f ldr r3, [pc, #188] @ (8006940 <APP_BLE_Init+0xcc>) + 8006882: 463c mov r4, r7 + 8006884: 461d mov r5, r3 + 8006886: cd0f ldmia r5!, {r0, r1, r2, r3} + 8006888: c40f stmia r4!, {r0, r1, r2, r3} + 800688a: cd0f ldmia r5!, {r0, r1, r2, r3} + 800688c: c40f stmia r4!, {r0, r1, r2, r3} + 800688e: cd0f ldmia r5!, {r0, r1, r2, r3} + 8006890: c40f stmia r4!, {r0, r1, r2, r3} + 8006892: e895 0007 ldmia.w r5, {r0, r1, r2} + 8006896: c403 stmia r4!, {r0, r1} + 8006898: 8022 strh r2, [r4, #0] + 800689a: 3402 adds r4, #2 + 800689c: 0c13 lsrs r3, r2, #16 + 800689e: 7023 strb r3, [r4, #0] + }; + + /** + * Initialize Ble Transport Layer + */ + Ble_Tl_Init(); + 80068a0: f000 f918 bl 8006ad4 <Ble_Tl_Init> + + /** + * Do not allow standby in the application + */ + UTIL_LPM_SetOffMode(1 << CFG_LPM_APP_BLE, UTIL_LPM_DISABLE); + 80068a4: 2101 movs r1, #1 + 80068a6: 2002 movs r0, #2 + 80068a8: f000 fe40 bl 800752c <UTIL_LPM_SetOffMode> + + /** + * Register the hci transport layer to handle BLE User Asynchronous Events + */ + UTIL_SEQ_RegTask(1<<CFG_TASK_HCI_ASYNCH_EVT_ID, UTIL_SEQ_RFU, hci_user_evt_proc); + 80068ac: 4a25 ldr r2, [pc, #148] @ (8006944 <APP_BLE_Init+0xd0>) + 80068ae: 2100 movs r1, #0 + 80068b0: 2002 movs r0, #2 + 80068b2: f000 ffed bl 8007890 <UTIL_SEQ_RegTask> + + /** + * Starts the BLE Stack on CPU2 + */ + status = SHCI_C2_BLE_Init(&ble_init_cmd_packet); + 80068b6: 463b mov r3, r7 + 80068b8: 4618 mov r0, r3 + 80068ba: f7ff f8b7 bl 8005a2c <SHCI_C2_BLE_Init> + 80068be: 4603 mov r3, r0 + 80068c0: f887 303e strb.w r3, [r7, #62] @ 0x3e + if (status != SHCI_Success) + 80068c4: f897 303e ldrb.w r3, [r7, #62] @ 0x3e + 80068c8: 2b00 cmp r3, #0 + 80068ca: d001 beq.n 80068d0 <APP_BLE_Init+0x5c> + { + APP_DBG_MSG(" Fail : SHCI_C2_BLE_Init command, result: 0x%02x\n\r", status); + /* if you are here, maybe CPU2 doesn't contain STM32WB_Copro_Wireless_Binaries, see Release_Notes.html */ + Error_Handler(); + 80068cc: f7fa fe26 bl 800151c <Error_Handler> + } + + /** + * Initialization of HCI & GATT & GAP layer + */ + Ble_Hci_Gap_Gatt_Init(); + 80068d0: f000 f916 bl 8006b00 <Ble_Hci_Gap_Gatt_Init> + + /** + * Initialization of the BLE Services + */ + SVCCTL_Init(); + 80068d4: f7ff f804 bl 80058e0 <SVCCTL_Init> + + /** + * Initialization of the BLE App Context + */ + BleApplicationContext.Device_Connection_Status = APP_BLE_IDLE; + 80068d8: 4b1b ldr r3, [pc, #108] @ (8006948 <APP_BLE_Init+0xd4>) + 80068da: 2200 movs r2, #0 + 80068dc: f883 2080 strb.w r2, [r3, #128] @ 0x80 + BleApplicationContext.BleApplicationContext_legacy.connectionHandle = 0xFFFF; + 80068e0: 4b19 ldr r3, [pc, #100] @ (8006948 <APP_BLE_Init+0xd4>) + 80068e2: f64f 72ff movw r2, #65535 @ 0xffff + 80068e6: 82da strh r2, [r3, #22] + + /** + * From here, all initialization are BLE application specific + */ + UTIL_SEQ_RegTask(1<<CFG_TASK_ADV_CANCEL_ID, UTIL_SEQ_RFU, Adv_Cancel); + 80068e8: 4a18 ldr r2, [pc, #96] @ (800694c <APP_BLE_Init+0xd8>) + 80068ea: 2100 movs r1, #0 + 80068ec: 2001 movs r0, #1 + 80068ee: f000 ffcf bl 8007890 <UTIL_SEQ_RegTask> +#if (BLE_CFG_OTA_REBOOT_CHAR != 0) + a_ManufData[sizeof(a_ManufData)-8] = CFG_FEATURE_OTA_REBOOT; +#endif /* BLE_CFG_OTA_REBOOT_CHAR != 0 */ + +#if (RADIO_ACTIVITY_EVENT != 0) + ret = aci_hal_set_radio_activity_mask(0x0006); + 80068f2: 2006 movs r0, #6 + 80068f4: f7fe fce4 bl 80052c0 <aci_hal_set_radio_activity_mask> + 80068f8: 4603 mov r3, r0 + 80068fa: f887 303f strb.w r3, [r7, #63] @ 0x3f +#endif /* L2CAP_REQUEST_NEW_CONN_PARAM != 0 */ + + /** + * Initialize P2P Server Application + */ + P2PS_APP_Init(); + 80068fe: f000 fb37 bl 8006f70 <P2PS_APP_Init> + /* USER CODE END APP_BLE_Init_3 */ + + /** + * Create timer to handle the Advertising Stop + */ + HW_TS_Create(CFG_TIM_PROC_ID_ISR, &(BleApplicationContext.Advertising_mgr_timer_Id), hw_ts_SingleShot, Adv_Cancel_Req); + 8006902: 4b13 ldr r3, [pc, #76] @ (8006950 <APP_BLE_Init+0xdc>) + 8006904: 2200 movs r2, #0 + 8006906: 4913 ldr r1, [pc, #76] @ (8006954 <APP_BLE_Init+0xe0>) + 8006908: 2000 movs r0, #0 + 800690a: f7fa facb bl 8000ea4 <HW_TS_Create> + /** + * Create timer to handle the Led Switch OFF + */ + HW_TS_Create(CFG_TIM_PROC_ID_ISR, &(BleApplicationContext.SwitchOffGPIO_timer_Id), hw_ts_SingleShot, Switch_OFF_GPIO); + 800690e: 4b12 ldr r3, [pc, #72] @ (8006958 <APP_BLE_Init+0xe4>) + 8006910: 2200 movs r2, #0 + 8006912: 4912 ldr r1, [pc, #72] @ (800695c <APP_BLE_Init+0xe8>) + 8006914: 2000 movs r0, #0 + 8006916: f7fa fac5 bl 8000ea4 <HW_TS_Create> + + /** + * Make device discoverable + */ + BleApplicationContext.BleApplicationContext_legacy.advtServUUID[0] = NULL; + 800691a: 4b0b ldr r3, [pc, #44] @ (8006948 <APP_BLE_Init+0xd4>) + 800691c: 2200 movs r2, #0 + 800691e: 765a strb r2, [r3, #25] + BleApplicationContext.BleApplicationContext_legacy.advtServUUIDlen = 0; + 8006920: 4b09 ldr r3, [pc, #36] @ (8006948 <APP_BLE_Init+0xd4>) + 8006922: 2200 movs r2, #0 + 8006924: 761a strb r2, [r3, #24] + + /* Initialize intervals for reconnexion without intervals update */ + AdvIntervalMin = CFG_FAST_CONN_ADV_INTERVAL_MIN; + 8006926: 4b0e ldr r3, [pc, #56] @ (8006960 <APP_BLE_Init+0xec>) + 8006928: 2280 movs r2, #128 @ 0x80 + 800692a: 801a strh r2, [r3, #0] + AdvIntervalMax = CFG_FAST_CONN_ADV_INTERVAL_MAX; + 800692c: 4b0d ldr r3, [pc, #52] @ (8006964 <APP_BLE_Init+0xf0>) + 800692e: 22a0 movs r2, #160 @ 0xa0 + 8006930: 801a strh r2, [r3, #0] + + /** + * Start to Advertise to be connected by P2P Client + */ + Adv_Request(APP_BLE_FAST_ADV); + 8006932: 2001 movs r0, #1 + 8006934: f000 f9b6 bl 8006ca4 <Adv_Request> + + /* USER CODE BEGIN APP_BLE_Init_2 */ + + /* USER CODE END APP_BLE_Init_2 */ + + return; + 8006938: bf00 nop +} + 800693a: 3740 adds r7, #64 @ 0x40 + 800693c: 46bd mov sp, r7 + 800693e: bdb0 pop {r4, r5, r7, pc} + 8006940: 08007bfc .word 0x08007bfc + 8006944: 08005c49 .word 0x08005c49 + 8006948: 20000270 .word 0x20000270 + 800694c: 08006e0d .word 0x08006e0d + 8006950: 08006e41 .word 0x08006e41 + 8006954: 200002f1 .word 0x200002f1 + 8006958: 08006e51 .word 0x08006e51 + 800695c: 200002f2 .word 0x200002f2 + 8006960: 200002f4 .word 0x200002f4 + 8006964: 200002f6 .word 0x200002f6 + +08006968 <SVCCTL_App_Notification>: + +SVCCTL_UserEvtFlowStatus_t SVCCTL_App_Notification(void *p_Pckt) +{ + 8006968: b580 push {r7, lr} + 800696a: b08a sub sp, #40 @ 0x28 + 800696c: af00 add r7, sp, #0 + 800696e: 6078 str r0, [r7, #4] + hci_event_pckt *p_event_pckt; + evt_le_meta_event *p_meta_evt; + evt_blecore_aci *p_blecore_evt; + uint8_t Tx_phy, Rx_phy; + tBleStatus ret = BLE_STATUS_INVALID_PARAMS; + 8006970: 2392 movs r3, #146 @ 0x92 + 8006972: f887 3027 strb.w r3, [r7, #39] @ 0x27 + + /* USER CODE BEGIN SVCCTL_App_Notification */ + + /* USER CODE END SVCCTL_App_Notification */ + + p_event_pckt = (hci_event_pckt*) ((hci_uart_pckt *) p_Pckt)->data; + 8006976: 687b ldr r3, [r7, #4] + 8006978: 3301 adds r3, #1 + 800697a: 623b str r3, [r7, #32] + + switch (p_event_pckt->evt) + 800697c: 6a3b ldr r3, [r7, #32] + 800697e: 781b ldrb r3, [r3, #0] + 8006980: 2bff cmp r3, #255 @ 0xff + 8006982: d076 beq.n 8006a72 <SVCCTL_App_Notification+0x10a> + 8006984: 2bff cmp r3, #255 @ 0xff + 8006986: f300 8098 bgt.w 8006aba <SVCCTL_App_Notification+0x152> + 800698a: 2b05 cmp r3, #5 + 800698c: d002 beq.n 8006994 <SVCCTL_App_Notification+0x2c> + 800698e: 2b3e cmp r3, #62 @ 0x3e + 8006990: d020 beq.n 80069d4 <SVCCTL_App_Notification+0x6c> + + default: + /* USER CODE BEGIN ECODE_DEFAULT*/ + + /* USER CODE END ECODE_DEFAULT*/ + break; + 8006992: e092 b.n 8006aba <SVCCTL_App_Notification+0x152> + p_disconnection_complete_event = (hci_disconnection_complete_event_rp0 *) p_event_pckt->data; + 8006994: 6a3b ldr r3, [r7, #32] + 8006996: 3302 adds r3, #2 + 8006998: 60fb str r3, [r7, #12] + if (p_disconnection_complete_event->Connection_Handle == BleApplicationContext.BleApplicationContext_legacy.connectionHandle) + 800699a: 68fb ldr r3, [r7, #12] + 800699c: f8b3 3001 ldrh.w r3, [r3, #1] + 80069a0: b29a uxth r2, r3 + 80069a2: 4b4a ldr r3, [pc, #296] @ (8006acc <SVCCTL_App_Notification+0x164>) + 80069a4: 8adb ldrh r3, [r3, #22] + 80069a6: 429a cmp r2, r3 + 80069a8: d106 bne.n 80069b8 <SVCCTL_App_Notification+0x50> + BleApplicationContext.BleApplicationContext_legacy.connectionHandle = 0; + 80069aa: 4b48 ldr r3, [pc, #288] @ (8006acc <SVCCTL_App_Notification+0x164>) + 80069ac: 2200 movs r2, #0 + 80069ae: 82da strh r2, [r3, #22] + BleApplicationContext.Device_Connection_Status = APP_BLE_IDLE; + 80069b0: 4b46 ldr r3, [pc, #280] @ (8006acc <SVCCTL_App_Notification+0x164>) + 80069b2: 2200 movs r2, #0 + 80069b4: f883 2080 strb.w r2, [r3, #128] @ 0x80 + Adv_Request(APP_BLE_FAST_ADV); + 80069b8: 2001 movs r0, #1 + 80069ba: f000 f973 bl 8006ca4 <Adv_Request> + HandleNotification.P2P_Evt_Opcode = PEER_DISCON_HANDLE_EVT; + 80069be: 4b44 ldr r3, [pc, #272] @ (8006ad0 <SVCCTL_App_Notification+0x168>) + 80069c0: 2201 movs r2, #1 + 80069c2: 701a strb r2, [r3, #0] + HandleNotification.ConnectionHandle = BleApplicationContext.BleApplicationContext_legacy.connectionHandle; + 80069c4: 4b41 ldr r3, [pc, #260] @ (8006acc <SVCCTL_App_Notification+0x164>) + 80069c6: 8ada ldrh r2, [r3, #22] + 80069c8: 4b41 ldr r3, [pc, #260] @ (8006ad0 <SVCCTL_App_Notification+0x168>) + 80069ca: 805a strh r2, [r3, #2] + P2PS_APP_Notification(&HandleNotification); + 80069cc: 4840 ldr r0, [pc, #256] @ (8006ad0 <SVCCTL_App_Notification+0x168>) + 80069ce: f000 fabb bl 8006f48 <P2PS_APP_Notification> + break; /* HCI_DISCONNECTION_COMPLETE_EVT_CODE */ + 80069d2: e075 b.n 8006ac0 <SVCCTL_App_Notification+0x158> + p_meta_evt = (evt_le_meta_event*) p_event_pckt->data; + 80069d4: 6a3b ldr r3, [r7, #32] + 80069d6: 3302 adds r3, #2 + 80069d8: 61bb str r3, [r7, #24] + switch (p_meta_evt->subevent) + 80069da: 69bb ldr r3, [r7, #24] + 80069dc: 781b ldrb r3, [r3, #0] + 80069de: 2b0c cmp r3, #12 + 80069e0: d005 beq.n 80069ee <SVCCTL_App_Notification+0x86> + 80069e2: 2b0c cmp r3, #12 + 80069e4: dc41 bgt.n 8006a6a <SVCCTL_App_Notification+0x102> + 80069e6: 2b01 cmp r3, #1 + 80069e8: d017 beq.n 8006a1a <SVCCTL_App_Notification+0xb2> + 80069ea: 2b03 cmp r3, #3 + break; + 80069ec: e03d b.n 8006a6a <SVCCTL_App_Notification+0x102> + p_evt_le_phy_update_complete = (hci_le_phy_update_complete_event_rp0*)p_meta_evt->data; + 80069ee: 69bb ldr r3, [r7, #24] + 80069f0: 3301 adds r3, #1 + 80069f2: 617b str r3, [r7, #20] + ret = hci_le_read_phy(BleApplicationContext.BleApplicationContext_legacy.connectionHandle, &Tx_phy, &Rx_phy); + 80069f4: 4b35 ldr r3, [pc, #212] @ (8006acc <SVCCTL_App_Notification+0x164>) + 80069f6: 8adb ldrh r3, [r3, #22] + 80069f8: f107 020a add.w r2, r7, #10 + 80069fc: f107 010b add.w r1, r7, #11 + 8006a00: 4618 mov r0, r3 + 8006a02: f7fe fcd5 bl 80053b0 <hci_le_read_phy> + 8006a06: 4603 mov r3, r0 + 8006a08: f887 3027 strb.w r3, [r7, #39] @ 0x27 + if (ret != BLE_STATUS_SUCCESS) + 8006a0c: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 8006a10: 2b00 cmp r3, #0 + 8006a12: d12c bne.n 8006a6e <SVCCTL_App_Notification+0x106> + if ((Tx_phy == TX_2M) && (Rx_phy == RX_2M)) + 8006a14: 7afb ldrb r3, [r7, #11] + 8006a16: 2b02 cmp r3, #2 + break; + 8006a18: e029 b.n 8006a6e <SVCCTL_App_Notification+0x106> + p_connection_complete_event = (hci_le_connection_complete_event_rp0 *) p_meta_evt->data; + 8006a1a: 69bb ldr r3, [r7, #24] + 8006a1c: 3301 adds r3, #1 + 8006a1e: 613b str r3, [r7, #16] + HW_TS_Stop(BleApplicationContext.Advertising_mgr_timer_Id); + 8006a20: 4b2a ldr r3, [pc, #168] @ (8006acc <SVCCTL_App_Notification+0x164>) + 8006a22: f893 3081 ldrb.w r3, [r3, #129] @ 0x81 + 8006a26: 4618 mov r0, r3 + 8006a28: f7fa fab6 bl 8000f98 <HW_TS_Stop> + if (BleApplicationContext.Device_Connection_Status == APP_BLE_LP_CONNECTING) + 8006a2c: 4b27 ldr r3, [pc, #156] @ (8006acc <SVCCTL_App_Notification+0x164>) + 8006a2e: f893 3080 ldrb.w r3, [r3, #128] @ 0x80 + 8006a32: 2b04 cmp r3, #4 + 8006a34: d104 bne.n 8006a40 <SVCCTL_App_Notification+0xd8> + BleApplicationContext.Device_Connection_Status = APP_BLE_CONNECTED_CLIENT; + 8006a36: 4b25 ldr r3, [pc, #148] @ (8006acc <SVCCTL_App_Notification+0x164>) + 8006a38: 2206 movs r2, #6 + 8006a3a: f883 2080 strb.w r2, [r3, #128] @ 0x80 + 8006a3e: e003 b.n 8006a48 <SVCCTL_App_Notification+0xe0> + BleApplicationContext.Device_Connection_Status = APP_BLE_CONNECTED_SERVER; + 8006a40: 4b22 ldr r3, [pc, #136] @ (8006acc <SVCCTL_App_Notification+0x164>) + 8006a42: 2205 movs r2, #5 + 8006a44: f883 2080 strb.w r2, [r3, #128] @ 0x80 + BleApplicationContext.BleApplicationContext_legacy.connectionHandle = p_connection_complete_event->Connection_Handle; + 8006a48: 693b ldr r3, [r7, #16] + 8006a4a: f8b3 3001 ldrh.w r3, [r3, #1] + 8006a4e: b29a uxth r2, r3 + 8006a50: 4b1e ldr r3, [pc, #120] @ (8006acc <SVCCTL_App_Notification+0x164>) + 8006a52: 82da strh r2, [r3, #22] + HandleNotification.P2P_Evt_Opcode = PEER_CONN_HANDLE_EVT; + 8006a54: 4b1e ldr r3, [pc, #120] @ (8006ad0 <SVCCTL_App_Notification+0x168>) + 8006a56: 2200 movs r2, #0 + 8006a58: 701a strb r2, [r3, #0] + HandleNotification.ConnectionHandle = BleApplicationContext.BleApplicationContext_legacy.connectionHandle; + 8006a5a: 4b1c ldr r3, [pc, #112] @ (8006acc <SVCCTL_App_Notification+0x164>) + 8006a5c: 8ada ldrh r2, [r3, #22] + 8006a5e: 4b1c ldr r3, [pc, #112] @ (8006ad0 <SVCCTL_App_Notification+0x168>) + 8006a60: 805a strh r2, [r3, #2] + P2PS_APP_Notification(&HandleNotification); + 8006a62: 481b ldr r0, [pc, #108] @ (8006ad0 <SVCCTL_App_Notification+0x168>) + 8006a64: f000 fa70 bl 8006f48 <P2PS_APP_Notification> + break; /* HCI_LE_CONNECTION_COMPLETE_SUBEVT_CODE */ + 8006a68: e002 b.n 8006a70 <SVCCTL_App_Notification+0x108> + break; + 8006a6a: bf00 nop + 8006a6c: e028 b.n 8006ac0 <SVCCTL_App_Notification+0x158> + break; + 8006a6e: bf00 nop + break; /* HCI_LE_META_EVT_CODE */ + 8006a70: e026 b.n 8006ac0 <SVCCTL_App_Notification+0x158> + p_blecore_evt = (evt_blecore_aci*) p_event_pckt->data; + 8006a72: 6a3b ldr r3, [r7, #32] + 8006a74: 3302 adds r3, #2 + 8006a76: 61fb str r3, [r7, #28] + switch (p_blecore_evt->ecode) + 8006a78: 69fb ldr r3, [r7, #28] + 8006a7a: 881b ldrh r3, [r3, #0] + 8006a7c: b29b uxth r3, r3 + 8006a7e: f640 420e movw r2, #3086 @ 0xc0e + 8006a82: 4293 cmp r3, r2 + 8006a84: d00f beq.n 8006aa6 <SVCCTL_App_Notification+0x13e> + 8006a86: f640 420e movw r2, #3086 @ 0xc0e + 8006a8a: 4293 cmp r3, r2 + 8006a8c: dc17 bgt.n 8006abe <SVCCTL_App_Notification+0x156> + 8006a8e: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8006a92: d00e beq.n 8006ab2 <SVCCTL_App_Notification+0x14a> + 8006a94: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8006a98: dc11 bgt.n 8006abe <SVCCTL_App_Notification+0x156> + 8006a9a: 2b04 cmp r3, #4 + 8006a9c: d00b beq.n 8006ab6 <SVCCTL_App_Notification+0x14e> + 8006a9e: f240 4207 movw r2, #1031 @ 0x407 + 8006aa2: 4293 cmp r3, r2 + break; /* ACI_GAP_PROC_COMPLETE_VSEVT_CODE */ + 8006aa4: e008 b.n 8006ab8 <SVCCTL_App_Notification+0x150> + aci_gatt_confirm_indication(BleApplicationContext.BleApplicationContext_legacy.connectionHandle); + 8006aa6: 4b09 ldr r3, [pc, #36] @ (8006acc <SVCCTL_App_Notification+0x164>) + 8006aa8: 8adb ldrh r3, [r3, #22] + 8006aaa: 4618 mov r0, r3 + 8006aac: f7fe fac7 bl 800503e <aci_gatt_confirm_indication> + break; + 8006ab0: e002 b.n 8006ab8 <SVCCTL_App_Notification+0x150> + break; + 8006ab2: bf00 nop + 8006ab4: e003 b.n 8006abe <SVCCTL_App_Notification+0x156> + break; /* ACI_HAL_END_OF_RADIO_ACTIVITY_VSEVT_CODE */ + 8006ab6: bf00 nop + break; /* HCI_VENDOR_SPECIFIC_DEBUG_EVT_CODE */ + 8006ab8: e001 b.n 8006abe <SVCCTL_App_Notification+0x156> + break; + 8006aba: bf00 nop + 8006abc: e000 b.n 8006ac0 <SVCCTL_App_Notification+0x158> + break; /* HCI_VENDOR_SPECIFIC_DEBUG_EVT_CODE */ + 8006abe: bf00 nop + } + + return (SVCCTL_UserEvtFlowEnable); + 8006ac0: 2301 movs r3, #1 +} + 8006ac2: 4618 mov r0, r3 + 8006ac4: 3728 adds r7, #40 @ 0x28 + 8006ac6: 46bd mov sp, r7 + 8006ac8: bd80 pop {r7, pc} + 8006aca: bf00 nop + 8006acc: 20000270 .word 0x20000270 + 8006ad0: 200002f8 .word 0x200002f8 + +08006ad4 <Ble_Tl_Init>: + * + * LOCAL FUNCTIONS + * + *************************************************************/ +static void Ble_Tl_Init(void) +{ + 8006ad4: b580 push {r7, lr} + 8006ad6: b082 sub sp, #8 + 8006ad8: af00 add r7, sp, #0 + HCI_TL_HciInitConf_t Hci_Tl_Init_Conf; + + Hci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&BleCmdBuffer; + 8006ada: 4b06 ldr r3, [pc, #24] @ (8006af4 <Ble_Tl_Init+0x20>) + 8006adc: 603b str r3, [r7, #0] + Hci_Tl_Init_Conf.StatusNotCallBack = BLE_StatusNot; + 8006ade: 4b06 ldr r3, [pc, #24] @ (8006af8 <Ble_Tl_Init+0x24>) + 8006ae0: 607b str r3, [r7, #4] + hci_init(BLE_UserEvtRx, (void*) &Hci_Tl_Init_Conf); + 8006ae2: 463b mov r3, r7 + 8006ae4: 4619 mov r1, r3 + 8006ae6: 4805 ldr r0, [pc, #20] @ (8006afc <Ble_Tl_Init+0x28>) + 8006ae8: f7ff f892 bl 8005c10 <hci_init> + + return; + 8006aec: bf00 nop +} + 8006aee: 3708 adds r7, #8 + 8006af0: 46bd mov sp, r7 + 8006af2: bd80 pop {r7, pc} + 8006af4: 200300d8 .word 0x200300d8 + 8006af8: 08006edb .word 0x08006edb + 8006afc: 08006ea3 .word 0x08006ea3 + +08006b00 <Ble_Hci_Gap_Gatt_Init>: + +static void Ble_Hci_Gap_Gatt_Init(void) +{ + 8006b00: b5f0 push {r4, r5, r6, r7, lr} + 8006b02: b08d sub sp, #52 @ 0x34 + 8006b04: af06 add r7, sp, #24 + uint8_t role; + uint16_t gap_service_handle, gap_dev_name_char_handle, gap_appearance_char_handle; + const uint8_t *p_bd_addr; + uint16_t a_appearance[1] = {BLE_CFG_GAP_APPEARANCE}; + 8006b06: 2300 movs r3, #0 + 8006b08: 803b strh r3, [r7, #0] + tBleStatus ret = BLE_STATUS_INVALID_PARAMS; + 8006b0a: 2392 movs r3, #146 @ 0x92 + 8006b0c: 75fb strb r3, [r7, #23] + + /** + * Initialize HCI layer + */ + /*HCI Reset to synchronise BLE Stack*/ + ret = hci_reset(); + 8006b0e: f7fe fc2b bl 8005368 <hci_reset> + 8006b12: 4603 mov r3, r0 + 8006b14: 75fb strb r3, [r7, #23] + } + + /** + * Write the BD Address + */ + p_bd_addr = BleGetBdAddress(); + 8006b16: f000 f935 bl 8006d84 <BleGetBdAddress> + 8006b1a: 6138 str r0, [r7, #16] + ret = aci_hal_write_config_data(CONFIG_DATA_PUBLIC_ADDRESS_OFFSET, CONFIG_DATA_PUBLIC_ADDRESS_LEN, (uint8_t*) p_bd_addr); + 8006b1c: 693a ldr r2, [r7, #16] + 8006b1e: 2106 movs r1, #6 + 8006b20: 2000 movs r0, #0 + 8006b22: f7fe fae1 bl 80050e8 <aci_hal_write_config_data> + 8006b26: 4603 mov r3, r0 + 8006b28: 75fb strb r3, [r7, #23] + APP_DBG_MSG(" Public Bluetooth Address: %02x:%02x:%02x:%02x:%02x:%02x\n",p_bd_addr[5],p_bd_addr[4],p_bd_addr[3],p_bd_addr[2],p_bd_addr[1],p_bd_addr[0]); + } + +#if (CFG_BLE_ADDRESS_TYPE == GAP_PUBLIC_ADDR) + /* BLE MAC in ADV Packet */ + a_ManufData[ sizeof(a_ManufData)-6] = p_bd_addr[5]; + 8006b2a: 693b ldr r3, [r7, #16] + 8006b2c: 3305 adds r3, #5 + 8006b2e: 781a ldrb r2, [r3, #0] + 8006b30: 4b56 ldr r3, [pc, #344] @ (8006c8c <Ble_Hci_Gap_Gatt_Init+0x18c>) + 8006b32: 721a strb r2, [r3, #8] + a_ManufData[ sizeof(a_ManufData)-5] = p_bd_addr[4]; + 8006b34: 693b ldr r3, [r7, #16] + 8006b36: 3304 adds r3, #4 + 8006b38: 781a ldrb r2, [r3, #0] + 8006b3a: 4b54 ldr r3, [pc, #336] @ (8006c8c <Ble_Hci_Gap_Gatt_Init+0x18c>) + 8006b3c: 725a strb r2, [r3, #9] + a_ManufData[ sizeof(a_ManufData)-4] = p_bd_addr[3]; + 8006b3e: 693b ldr r3, [r7, #16] + 8006b40: 3303 adds r3, #3 + 8006b42: 781a ldrb r2, [r3, #0] + 8006b44: 4b51 ldr r3, [pc, #324] @ (8006c8c <Ble_Hci_Gap_Gatt_Init+0x18c>) + 8006b46: 729a strb r2, [r3, #10] + a_ManufData[ sizeof(a_ManufData)-3] = p_bd_addr[2]; + 8006b48: 693b ldr r3, [r7, #16] + 8006b4a: 3302 adds r3, #2 + 8006b4c: 781a ldrb r2, [r3, #0] + 8006b4e: 4b4f ldr r3, [pc, #316] @ (8006c8c <Ble_Hci_Gap_Gatt_Init+0x18c>) + 8006b50: 72da strb r2, [r3, #11] + a_ManufData[ sizeof(a_ManufData)-2] = p_bd_addr[1]; + 8006b52: 693b ldr r3, [r7, #16] + 8006b54: 3301 adds r3, #1 + 8006b56: 781a ldrb r2, [r3, #0] + 8006b58: 4b4c ldr r3, [pc, #304] @ (8006c8c <Ble_Hci_Gap_Gatt_Init+0x18c>) + 8006b5a: 731a strb r2, [r3, #12] + a_ManufData[ sizeof(a_ManufData)-1] = p_bd_addr[0]; + 8006b5c: 693b ldr r3, [r7, #16] + 8006b5e: 781a ldrb r2, [r3, #0] + 8006b60: 4b4a ldr r3, [pc, #296] @ (8006c8c <Ble_Hci_Gap_Gatt_Init+0x18c>) + 8006b62: 735a strb r2, [r3, #13] +#endif /* CFG_BLE_ADDRESS_TYPE != GAP_PUBLIC_ADDR */ + + /** + * Write Identity root key used to derive IRK and DHK(Legacy) + */ + ret = aci_hal_write_config_data(CONFIG_DATA_IR_OFFSET, CONFIG_DATA_IR_LEN, (uint8_t*)a_BLE_CfgIrValue); + 8006b64: 4a4a ldr r2, [pc, #296] @ (8006c90 <Ble_Hci_Gap_Gatt_Init+0x190>) + 8006b66: 2110 movs r1, #16 + 8006b68: 2018 movs r0, #24 + 8006b6a: f7fe fabd bl 80050e8 <aci_hal_write_config_data> + 8006b6e: 4603 mov r3, r0 + 8006b70: 75fb strb r3, [r7, #23] + } + + /** + * Write Encryption root key used to derive LTK and CSRK + */ + ret = aci_hal_write_config_data(CONFIG_DATA_ER_OFFSET, CONFIG_DATA_ER_LEN, (uint8_t*)a_BLE_CfgErValue); + 8006b72: 4a48 ldr r2, [pc, #288] @ (8006c94 <Ble_Hci_Gap_Gatt_Init+0x194>) + 8006b74: 2110 movs r1, #16 + 8006b76: 2008 movs r0, #8 + 8006b78: f7fe fab6 bl 80050e8 <aci_hal_write_config_data> + 8006b7c: 4603 mov r3, r0 + 8006b7e: 75fb strb r3, [r7, #23] + } + + /** + * Set TX Power. + */ + ret = aci_hal_set_tx_power_level(1, CFG_TX_POWER); + 8006b80: 2118 movs r1, #24 + 8006b82: 2001 movs r0, #1 + 8006b84: f7fe fb35 bl 80051f2 <aci_hal_set_tx_power_level> + 8006b88: 4603 mov r3, r0 + 8006b8a: 75fb strb r3, [r7, #23] + } + + /** + * Initialize GATT interface + */ + ret = aci_gatt_init(); + 8006b8c: f7fd ffab bl 8004ae6 <aci_gatt_init> + 8006b90: 4603 mov r3, r0 + 8006b92: 75fb strb r3, [r7, #23] + } + + /** + * Initialize GAP interface + */ + role = 0; + 8006b94: 2300 movs r3, #0 + 8006b96: 73fb strb r3, [r7, #15] + +#if (BLE_CFG_PERIPHERAL == 1) + role |= GAP_PERIPHERAL_ROLE; + 8006b98: 7bfb ldrb r3, [r7, #15] + 8006b9a: f043 0301 orr.w r3, r3, #1 + 8006b9e: 73fb strb r3, [r7, #15] + +/* USER CODE BEGIN Role_Mngt*/ + +/* USER CODE END Role_Mngt */ + + if (role > 0) + 8006ba0: 7bfb ldrb r3, [r7, #15] + 8006ba2: 2b00 cmp r3, #0 + 8006ba4: d01f beq.n 8006be6 <Ble_Hci_Gap_Gatt_Init+0xe6> + { + const char *name = "P2PSRV1"; + 8006ba6: 4b3c ldr r3, [pc, #240] @ (8006c98 <Ble_Hci_Gap_Gatt_Init+0x198>) + 8006ba8: 60bb str r3, [r7, #8] + ret = aci_gap_init(role, + 8006baa: 1dba adds r2, r7, #6 + 8006bac: 7bf8 ldrb r0, [r7, #15] + 8006bae: 1cbb adds r3, r7, #2 + 8006bb0: 9301 str r3, [sp, #4] + 8006bb2: 1d3b adds r3, r7, #4 + 8006bb4: 9300 str r3, [sp, #0] + 8006bb6: 4613 mov r3, r2 + 8006bb8: 2207 movs r2, #7 + 8006bba: 2100 movs r1, #0 + 8006bbc: f7fd fe50 bl 8004860 <aci_gap_init> + 8006bc0: 4603 mov r3, r0 + 8006bc2: 75fb strb r3, [r7, #23] + else + { + APP_DBG_MSG(" Success: aci_gap_init command\n"); + } + + ret = aci_gatt_update_char_value(gap_service_handle, gap_dev_name_char_handle, 0, strlen(name), (uint8_t *) name); + 8006bc4: 88fc ldrh r4, [r7, #6] + 8006bc6: 88bd ldrh r5, [r7, #4] + 8006bc8: 68b8 ldr r0, [r7, #8] + 8006bca: f7f9 fad7 bl 800017c <strlen> + 8006bce: 4603 mov r3, r0 + 8006bd0: b2da uxtb r2, r3 + 8006bd2: 68bb ldr r3, [r7, #8] + 8006bd4: 9300 str r3, [sp, #0] + 8006bd6: 4613 mov r3, r2 + 8006bd8: 2200 movs r2, #0 + 8006bda: 4629 mov r1, r5 + 8006bdc: 4620 mov r0, r4 + 8006bde: f7fe f985 bl 8004eec <aci_gatt_update_char_value> + 8006be2: 4603 mov r3, r0 + 8006be4: 75fb strb r3, [r7, #23] + { + BLE_DBG_SVCCTL_MSG(" Success: aci_gatt_update_char_value - Device Name\n"); + } + } + + ret = aci_gatt_update_char_value(gap_service_handle, + 8006be6: 88f8 ldrh r0, [r7, #6] + 8006be8: 8879 ldrh r1, [r7, #2] + 8006bea: 463b mov r3, r7 + 8006bec: 9300 str r3, [sp, #0] + 8006bee: 2302 movs r3, #2 + 8006bf0: 2200 movs r2, #0 + 8006bf2: f7fe f97b bl 8004eec <aci_gatt_update_char_value> + 8006bf6: 4603 mov r3, r0 + 8006bf8: 75fb strb r3, [r7, #23] + } + + /** + * Initialize Default PHY + */ + ret = hci_le_set_default_phy(ALL_PHYS_PREFERENCE,TX_2M_PREFERRED,RX_2M_PREFERRED); + 8006bfa: 2202 movs r2, #2 + 8006bfc: 2102 movs r1, #2 + 8006bfe: 2000 movs r0, #0 + 8006c00: f7fe fc54 bl 80054ac <hci_le_set_default_phy> + 8006c04: 4603 mov r3, r0 + 8006c06: 75fb strb r3, [r7, #23] + } + + /** + * Initialize IO capability + */ + BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.ioCapability = CFG_IO_CAPABILITY; + 8006c08: 4b24 ldr r3, [pc, #144] @ (8006c9c <Ble_Hci_Gap_Gatt_Init+0x19c>) + 8006c0a: 2201 movs r2, #1 + 8006c0c: 701a strb r2, [r3, #0] + ret = aci_gap_set_io_capability(BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.ioCapability); + 8006c0e: 4b23 ldr r3, [pc, #140] @ (8006c9c <Ble_Hci_Gap_Gatt_Init+0x19c>) + 8006c10: 781b ldrb r3, [r3, #0] + 8006c12: 4618 mov r0, r3 + 8006c14: f7fd fd0c bl 8004630 <aci_gap_set_io_capability> + 8006c18: 4603 mov r3, r0 + 8006c1a: 75fb strb r3, [r7, #23] + } + + /** + * Initialize authentication + */ + BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.mitm_mode = CFG_MITM_PROTECTION; + 8006c1c: 4b1f ldr r3, [pc, #124] @ (8006c9c <Ble_Hci_Gap_Gatt_Init+0x19c>) + 8006c1e: 2201 movs r2, #1 + 8006c20: 705a strb r2, [r3, #1] + BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMin = CFG_ENCRYPTION_KEY_SIZE_MIN; + 8006c22: 4b1e ldr r3, [pc, #120] @ (8006c9c <Ble_Hci_Gap_Gatt_Init+0x19c>) + 8006c24: 2208 movs r2, #8 + 8006c26: 711a strb r2, [r3, #4] + BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.encryptionKeySizeMax = CFG_ENCRYPTION_KEY_SIZE_MAX; + 8006c28: 4b1c ldr r3, [pc, #112] @ (8006c9c <Ble_Hci_Gap_Gatt_Init+0x19c>) + 8006c2a: 2210 movs r2, #16 + 8006c2c: 715a strb r2, [r3, #5] + BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Use_Fixed_Pin = CFG_USED_FIXED_PIN; + 8006c2e: 4b1b ldr r3, [pc, #108] @ (8006c9c <Ble_Hci_Gap_Gatt_Init+0x19c>) + 8006c30: 2200 movs r2, #0 + 8006c32: 70da strb r2, [r3, #3] + BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.Fixed_Pin = CFG_FIXED_PIN; + 8006c34: 4b19 ldr r3, [pc, #100] @ (8006c9c <Ble_Hci_Gap_Gatt_Init+0x19c>) + 8006c36: 4a1a ldr r2, [pc, #104] @ (8006ca0 <Ble_Hci_Gap_Gatt_Init+0x1a0>) + 8006c38: 609a str r2, [r3, #8] + BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode = CFG_BONDING_MODE; + 8006c3a: 4b18 ldr r3, [pc, #96] @ (8006c9c <Ble_Hci_Gap_Gatt_Init+0x19c>) + 8006c3c: 2201 movs r2, #1 + 8006c3e: 709a strb r2, [r3, #2] + /* USER CODE BEGIN Ble_Hci_Gap_Gatt_Init_1*/ + + /* USER CODE END Ble_Hci_Gap_Gatt_Init_1*/ + + ret = aci_gap_set_authentication_requirement(BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode, + 8006c40: 4b16 ldr r3, [pc, #88] @ (8006c9c <Ble_Hci_Gap_Gatt_Init+0x19c>) + 8006c42: 789c ldrb r4, [r3, #2] + 8006c44: 4b15 ldr r3, [pc, #84] @ (8006c9c <Ble_Hci_Gap_Gatt_Init+0x19c>) + 8006c46: 785d ldrb r5, [r3, #1] + 8006c48: 4b14 ldr r3, [pc, #80] @ (8006c9c <Ble_Hci_Gap_Gatt_Init+0x19c>) + 8006c4a: 791b ldrb r3, [r3, #4] + 8006c4c: 4a13 ldr r2, [pc, #76] @ (8006c9c <Ble_Hci_Gap_Gatt_Init+0x19c>) + 8006c4e: 7952 ldrb r2, [r2, #5] + 8006c50: 4912 ldr r1, [pc, #72] @ (8006c9c <Ble_Hci_Gap_Gatt_Init+0x19c>) + 8006c52: 78c9 ldrb r1, [r1, #3] + 8006c54: 4811 ldr r0, [pc, #68] @ (8006c9c <Ble_Hci_Gap_Gatt_Init+0x19c>) + 8006c56: 6880 ldr r0, [r0, #8] + 8006c58: 2600 movs r6, #0 + 8006c5a: 9604 str r6, [sp, #16] + 8006c5c: 9003 str r0, [sp, #12] + 8006c5e: 9102 str r1, [sp, #8] + 8006c60: 9201 str r2, [sp, #4] + 8006c62: 9300 str r3, [sp, #0] + 8006c64: 2300 movs r3, #0 + 8006c66: 2201 movs r2, #1 + 8006c68: 4629 mov r1, r5 + 8006c6a: 4620 mov r0, r4 + 8006c6c: f7fd fd34 bl 80046d8 <aci_gap_set_authentication_requirement> + 8006c70: 4603 mov r3, r0 + 8006c72: 75fb strb r3, [r7, #23] + } + + /** + * Initialize whitelist + */ + if (BleApplicationContext.BleApplicationContext_legacy.bleSecurityParam.bonding_mode) + 8006c74: 4b09 ldr r3, [pc, #36] @ (8006c9c <Ble_Hci_Gap_Gatt_Init+0x19c>) + 8006c76: 789b ldrb r3, [r3, #2] + 8006c78: 2b00 cmp r3, #0 + 8006c7a: d003 beq.n 8006c84 <Ble_Hci_Gap_Gatt_Init+0x184> + { + ret = aci_gap_configure_whitelist(); + 8006c7c: f7fd ff0f bl 8004a9e <aci_gap_configure_filter_accept_list> + 8006c80: 4603 mov r3, r0 + 8006c82: 75fb strb r3, [r7, #23] + { + APP_DBG_MSG(" Success: aci_gap_configure_whitelist command\n"); + } + } + APP_DBG_MSG("==>> End Ble_Hci_Gap_Gatt_Init function\n\r"); +} + 8006c84: bf00 nop + 8006c86: 371c adds r7, #28 + 8006c88: 46bd mov sp, r7 + 8006c8a: bdf0 pop {r4, r5, r6, r7, pc} + 8006c8c: 20000014 .word 0x20000014 + 8006c90: 08007df8 .word 0x08007df8 + 8006c94: 08007e08 .word 0x08007e08 + 8006c98: 08007c38 .word 0x08007c38 + 8006c9c: 20000270 .word 0x20000270 + 8006ca0: 0001b207 .word 0x0001b207 + +08006ca4 <Adv_Request>: + +static void Adv_Request(APP_BLE_ConnStatus_t NewStatus) +{ + 8006ca4: b580 push {r7, lr} + 8006ca6: b08c sub sp, #48 @ 0x30 + 8006ca8: af08 add r7, sp, #32 + 8006caa: 4603 mov r3, r0 + 8006cac: 71fb strb r3, [r7, #7] + tBleStatus ret = BLE_STATUS_INVALID_PARAMS; + 8006cae: 2392 movs r3, #146 @ 0x92 + 8006cb0: 72fb strb r3, [r7, #11] + uint16_t Min_Inter, Max_Inter; + + if (NewStatus == APP_BLE_FAST_ADV) + 8006cb2: 79fb ldrb r3, [r7, #7] + 8006cb4: 2b01 cmp r3, #1 + 8006cb6: d106 bne.n 8006cc6 <Adv_Request+0x22> + { + Min_Inter = AdvIntervalMin; + 8006cb8: 4b2b ldr r3, [pc, #172] @ (8006d68 <Adv_Request+0xc4>) + 8006cba: 881b ldrh r3, [r3, #0] + 8006cbc: 81fb strh r3, [r7, #14] + Max_Inter = AdvIntervalMax; + 8006cbe: 4b2b ldr r3, [pc, #172] @ (8006d6c <Adv_Request+0xc8>) + 8006cc0: 881b ldrh r3, [r3, #0] + 8006cc2: 81bb strh r3, [r7, #12] + 8006cc4: e005 b.n 8006cd2 <Adv_Request+0x2e> + } + else + { + Min_Inter = CFG_LP_CONN_ADV_INTERVAL_MIN; + 8006cc6: f44f 63c8 mov.w r3, #1600 @ 0x640 + 8006cca: 81fb strh r3, [r7, #14] + Max_Inter = CFG_LP_CONN_ADV_INTERVAL_MAX; + 8006ccc: f44f 637a mov.w r3, #4000 @ 0xfa0 + 8006cd0: 81bb strh r3, [r7, #12] + + /** + * Stop the timer, it will be restarted for a new shot + * It does not hurt if the timer was not running + */ + HW_TS_Stop(BleApplicationContext.Advertising_mgr_timer_Id); + 8006cd2: 4b27 ldr r3, [pc, #156] @ (8006d70 <Adv_Request+0xcc>) + 8006cd4: f893 3081 ldrb.w r3, [r3, #129] @ 0x81 + 8006cd8: 4618 mov r0, r3 + 8006cda: f7fa f95d bl 8000f98 <HW_TS_Stop> + + if ((NewStatus == APP_BLE_LP_ADV) + 8006cde: 79fb ldrb r3, [r7, #7] + 8006ce0: 2b02 cmp r3, #2 + 8006ce2: d10d bne.n 8006d00 <Adv_Request+0x5c> + && ((BleApplicationContext.Device_Connection_Status == APP_BLE_FAST_ADV) + 8006ce4: 4b22 ldr r3, [pc, #136] @ (8006d70 <Adv_Request+0xcc>) + 8006ce6: f893 3080 ldrb.w r3, [r3, #128] @ 0x80 + 8006cea: 2b01 cmp r3, #1 + 8006cec: d004 beq.n 8006cf8 <Adv_Request+0x54> + || (BleApplicationContext.Device_Connection_Status == APP_BLE_LP_ADV))) + 8006cee: 4b20 ldr r3, [pc, #128] @ (8006d70 <Adv_Request+0xcc>) + 8006cf0: f893 3080 ldrb.w r3, [r3, #128] @ 0x80 + 8006cf4: 2b02 cmp r3, #2 + 8006cf6: d103 bne.n 8006d00 <Adv_Request+0x5c> + { + /* Connection in ADVERTISE mode have to stop the current advertising */ + ret = aci_gap_set_non_discoverable(); + 8006cf8: f7fd fb7c bl 80043f4 <aci_gap_set_non_discoverable> + 8006cfc: 4603 mov r3, r0 + 8006cfe: 72fb strb r3, [r7, #11] + { + APP_DBG_MSG("==>> aci_gap_set_non_discoverable - Successfully Stopped Advertising \n"); + } + } + + BleApplicationContext.Device_Connection_Status = NewStatus; + 8006d00: 4a1b ldr r2, [pc, #108] @ (8006d70 <Adv_Request+0xcc>) + 8006d02: 79fb ldrb r3, [r7, #7] + 8006d04: f882 3080 strb.w r3, [r2, #128] @ 0x80 + /* Start Fast or Low Power Advertising */ + ret = aci_gap_set_discoverable(ADV_IND, + 8006d08: 4b19 ldr r3, [pc, #100] @ (8006d70 <Adv_Request+0xcc>) + 8006d0a: 7e1b ldrb r3, [r3, #24] + 8006d0c: 89ba ldrh r2, [r7, #12] + 8006d0e: 89f9 ldrh r1, [r7, #14] + 8006d10: 2000 movs r0, #0 + 8006d12: 9006 str r0, [sp, #24] + 8006d14: 2000 movs r0, #0 + 8006d16: 9005 str r0, [sp, #20] + 8006d18: 4816 ldr r0, [pc, #88] @ (8006d74 <Adv_Request+0xd0>) + 8006d1a: 9004 str r0, [sp, #16] + 8006d1c: 9303 str r3, [sp, #12] + 8006d1e: 4b16 ldr r3, [pc, #88] @ (8006d78 <Adv_Request+0xd4>) + 8006d20: 9302 str r3, [sp, #8] + 8006d22: 2308 movs r3, #8 + 8006d24: 9301 str r3, [sp, #4] + 8006d26: 2300 movs r3, #0 + 8006d28: 9300 str r3, [sp, #0] + 8006d2a: 2300 movs r3, #0 + 8006d2c: 2000 movs r0, #0 + 8006d2e: f7fd fb85 bl 800443c <aci_gap_set_discoverable> + 8006d32: 4603 mov r3, r0 + 8006d34: 72fb strb r3, [r7, #11] + { + APP_DBG_MSG("==>> aci_gap_set_discoverable - Success\n"); + } + + /* Update Advertising data */ + ret = aci_gap_update_adv_data(sizeof(a_ManufData), (uint8_t*) a_ManufData); + 8006d36: 4911 ldr r1, [pc, #68] @ (8006d7c <Adv_Request+0xd8>) + 8006d38: 200e movs r0, #14 + 8006d3a: f7fd fe3e bl 80049ba <aci_gap_update_adv_data> + 8006d3e: 4603 mov r3, r0 + 8006d40: 72fb strb r3, [r7, #11] + if (ret != BLE_STATUS_SUCCESS) + 8006d42: 7afb ldrb r3, [r7, #11] + 8006d44: 2b00 cmp r3, #0 + 8006d46: d10a bne.n 8006d5e <Adv_Request+0xba> + APP_DBG_MSG("==>> Start Low Power Advertising Failed , result: %d \n\r", ret); + } + } + else + { + if (NewStatus == APP_BLE_FAST_ADV) + 8006d48: 79fb ldrb r3, [r7, #7] + 8006d4a: 2b01 cmp r3, #1 + 8006d4c: d107 bne.n 8006d5e <Adv_Request+0xba> + { + APP_DBG_MSG("==>> Success: Start Fast Advertising \n\r"); + /* Start Timer to STOP ADV - TIMEOUT - and next Restart Low Power Advertising */ + HW_TS_Start(BleApplicationContext.Advertising_mgr_timer_Id, INITIAL_ADV_TIMEOUT); + 8006d4e: 4b08 ldr r3, [pc, #32] @ (8006d70 <Adv_Request+0xcc>) + 8006d50: f893 3081 ldrb.w r3, [r3, #129] @ 0x81 + 8006d54: 490a ldr r1, [pc, #40] @ (8006d80 <Adv_Request+0xdc>) + 8006d56: 4618 mov r0, r3 + 8006d58: f7fa f9a2 bl 80010a0 <HW_TS_Start> + { + APP_DBG_MSG("==>> Success: Start Low Power Advertising \n\r"); + } + } + + return; + 8006d5c: bf00 nop + 8006d5e: bf00 nop +} + 8006d60: 3710 adds r7, #16 + 8006d62: 46bd mov sp, r7 + 8006d64: bd80 pop {r7, pc} + 8006d66: bf00 nop + 8006d68: 200002f4 .word 0x200002f4 + 8006d6c: 200002f6 .word 0x200002f6 + 8006d70: 20000270 .word 0x20000270 + 8006d74: 20000289 .word 0x20000289 + 8006d78: 08007e18 .word 0x08007e18 + 8006d7c: 20000014 .word 0x20000014 + 8006d80: 0001e046 .word 0x0001e046 + +08006d84 <BleGetBdAddress>: + +const uint8_t* BleGetBdAddress(void) +{ + 8006d84: b580 push {r7, lr} + 8006d86: b086 sub sp, #24 + 8006d88: af00 add r7, sp, #0 + const uint8_t *p_bd_addr; + uint32_t udn; + uint32_t company_id; + uint32_t device_id; + + udn = LL_FLASH_GetUDN(); + 8006d8a: f7ff fd4f bl 800682c <LL_FLASH_GetUDN> + 8006d8e: 6138 str r0, [r7, #16] + + if (udn != 0xFFFFFFFF) + 8006d90: 693b ldr r3, [r7, #16] + 8006d92: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8006d96: d023 beq.n 8006de0 <BleGetBdAddress+0x5c> + { + company_id = LL_FLASH_GetSTCompanyID(); + 8006d98: f7ff fd60 bl 800685c <LL_FLASH_GetSTCompanyID> + 8006d9c: 60b8 str r0, [r7, #8] + device_id = LL_FLASH_GetDeviceID(); + 8006d9e: f7ff fd51 bl 8006844 <LL_FLASH_GetDeviceID> + 8006da2: 6078 str r0, [r7, #4] + * bit[23:16] : Device ID. + * bit[15:0] : The last 16bits from the UDN + * Note: In order to use the Public Address in a final product, a dedicated + * 24bits company ID (OUI) shall be bought. + */ + a_BdAddrUdn[0] = (uint8_t)(udn & 0x000000FF); + 8006da4: 693b ldr r3, [r7, #16] + 8006da6: b2da uxtb r2, r3 + 8006da8: 4b16 ldr r3, [pc, #88] @ (8006e04 <BleGetBdAddress+0x80>) + 8006daa: 701a strb r2, [r3, #0] + a_BdAddrUdn[1] = (uint8_t)((udn & 0x0000FF00) >> 8); + 8006dac: 693b ldr r3, [r7, #16] + 8006dae: 0a1b lsrs r3, r3, #8 + 8006db0: b2da uxtb r2, r3 + 8006db2: 4b14 ldr r3, [pc, #80] @ (8006e04 <BleGetBdAddress+0x80>) + 8006db4: 705a strb r2, [r3, #1] + a_BdAddrUdn[2] = (uint8_t)device_id; + 8006db6: 687b ldr r3, [r7, #4] + 8006db8: b2da uxtb r2, r3 + 8006dba: 4b12 ldr r3, [pc, #72] @ (8006e04 <BleGetBdAddress+0x80>) + 8006dbc: 709a strb r2, [r3, #2] + a_BdAddrUdn[3] = (uint8_t)(company_id & 0x000000FF); + 8006dbe: 68bb ldr r3, [r7, #8] + 8006dc0: b2da uxtb r2, r3 + 8006dc2: 4b10 ldr r3, [pc, #64] @ (8006e04 <BleGetBdAddress+0x80>) + 8006dc4: 70da strb r2, [r3, #3] + a_BdAddrUdn[4] = (uint8_t)((company_id & 0x0000FF00) >> 8); + 8006dc6: 68bb ldr r3, [r7, #8] + 8006dc8: 0a1b lsrs r3, r3, #8 + 8006dca: b2da uxtb r2, r3 + 8006dcc: 4b0d ldr r3, [pc, #52] @ (8006e04 <BleGetBdAddress+0x80>) + 8006dce: 711a strb r2, [r3, #4] + a_BdAddrUdn[5] = (uint8_t)((company_id & 0x00FF0000) >> 16); + 8006dd0: 68bb ldr r3, [r7, #8] + 8006dd2: 0c1b lsrs r3, r3, #16 + 8006dd4: b2da uxtb r2, r3 + 8006dd6: 4b0b ldr r3, [pc, #44] @ (8006e04 <BleGetBdAddress+0x80>) + 8006dd8: 715a strb r2, [r3, #5] + + p_bd_addr = (const uint8_t *)a_BdAddrUdn; + 8006dda: 4b0a ldr r3, [pc, #40] @ (8006e04 <BleGetBdAddress+0x80>) + 8006ddc: 617b str r3, [r7, #20] + 8006dde: e00b b.n 8006df8 <BleGetBdAddress+0x74> + } + else + { + p_otp_addr = OTP_Read(0); + 8006de0: 2000 movs r0, #0 + 8006de2: f7ff fc3d bl 8006660 <OTP_Read> + 8006de6: 60f8 str r0, [r7, #12] + if (p_otp_addr) + 8006de8: 68fb ldr r3, [r7, #12] + 8006dea: 2b00 cmp r3, #0 + 8006dec: d002 beq.n 8006df4 <BleGetBdAddress+0x70> + { + p_bd_addr = ((OTP_ID0_t*)p_otp_addr)->bd_address; + 8006dee: 68fb ldr r3, [r7, #12] + 8006df0: 617b str r3, [r7, #20] + 8006df2: e001 b.n 8006df8 <BleGetBdAddress+0x74> + } + else + { + p_bd_addr = a_MBdAddr; + 8006df4: 4b04 ldr r3, [pc, #16] @ (8006e08 <BleGetBdAddress+0x84>) + 8006df6: 617b str r3, [r7, #20] + } + } + + return p_bd_addr; + 8006df8: 697b ldr r3, [r7, #20] +} + 8006dfa: 4618 mov r0, r3 + 8006dfc: 3718 adds r7, #24 + 8006dfe: 46bd mov sp, r7 + 8006e00: bd80 pop {r7, pc} + 8006e02: bf00 nop + 8006e04: 20000268 .word 0x20000268 + 8006e08: 08007df0 .word 0x08007df0 + +08006e0c <Adv_Cancel>: + * + * SPECIFIC FUNCTIONS FOR P2P SERVER + * + *************************************************************/ +static void Adv_Cancel(void) +{ + 8006e0c: b580 push {r7, lr} + 8006e0e: b082 sub sp, #8 + 8006e10: af00 add r7, sp, #0 + /* USER CODE BEGIN Adv_Cancel_1 */ + + /* USER CODE END Adv_Cancel_1 */ + + if (BleApplicationContext.Device_Connection_Status != APP_BLE_CONNECTED_SERVER) + 8006e12: 4b0a ldr r3, [pc, #40] @ (8006e3c <Adv_Cancel+0x30>) + 8006e14: f893 3080 ldrb.w r3, [r3, #128] @ 0x80 + 8006e18: 2b05 cmp r3, #5 + 8006e1a: d00a beq.n 8006e32 <Adv_Cancel+0x26> + { + tBleStatus ret = BLE_STATUS_INVALID_PARAMS; + 8006e1c: 2392 movs r3, #146 @ 0x92 + 8006e1e: 71fb strb r3, [r7, #7] + + ret = aci_gap_set_non_discoverable(); + 8006e20: f7fd fae8 bl 80043f4 <aci_gap_set_non_discoverable> + 8006e24: 4603 mov r3, r0 + 8006e26: 71fb strb r3, [r7, #7] + + BleApplicationContext.Device_Connection_Status = APP_BLE_IDLE; + 8006e28: 4b04 ldr r3, [pc, #16] @ (8006e3c <Adv_Cancel+0x30>) + 8006e2a: 2200 movs r2, #0 + 8006e2c: f883 2080 strb.w r2, [r3, #128] @ 0x80 + + /* USER CODE BEGIN Adv_Cancel_2 */ + + /* USER CODE END Adv_Cancel_2 */ + + return; + 8006e30: bf00 nop + 8006e32: bf00 nop +} + 8006e34: 3708 adds r7, #8 + 8006e36: 46bd mov sp, r7 + 8006e38: bd80 pop {r7, pc} + 8006e3a: bf00 nop + 8006e3c: 20000270 .word 0x20000270 + +08006e40 <Adv_Cancel_Req>: + +static void Adv_Cancel_Req(void) +{ + 8006e40: b580 push {r7, lr} + 8006e42: af00 add r7, sp, #0 + /* USER CODE BEGIN Adv_Cancel_Req_1 */ + + /* USER CODE END Adv_Cancel_Req_1 */ + + UTIL_SEQ_SetTask(1 << CFG_TASK_ADV_CANCEL_ID, CFG_SCH_PRIO_0); + 8006e44: 2100 movs r1, #0 + 8006e46: 2001 movs r0, #1 + 8006e48: f000 fd44 bl 80078d4 <UTIL_SEQ_SetTask> + + /* USER CODE BEGIN Adv_Cancel_Req_2 */ + + /* USER CODE END Adv_Cancel_Req_2 */ + + return; + 8006e4c: bf00 nop +} + 8006e4e: bd80 pop {r7, pc} + +08006e50 <Switch_OFF_GPIO>: + +static void Switch_OFF_GPIO() +{ + 8006e50: b480 push {r7} + 8006e52: af00 add r7, sp, #0 + /* USER CODE BEGIN Switch_OFF_GPIO */ + + /* USER CODE END Switch_OFF_GPIO */ +} + 8006e54: bf00 nop + 8006e56: 46bd mov sp, r7 + 8006e58: f85d 7b04 ldr.w r7, [sp], #4 + 8006e5c: 4770 bx lr + +08006e5e <hci_notify_asynch_evt>: + * + * WRAP FUNCTIONS + * + *************************************************************/ +void hci_notify_asynch_evt(void* p_Data) +{ + 8006e5e: b580 push {r7, lr} + 8006e60: b082 sub sp, #8 + 8006e62: af00 add r7, sp, #0 + 8006e64: 6078 str r0, [r7, #4] + UTIL_SEQ_SetTask(1 << CFG_TASK_HCI_ASYNCH_EVT_ID, CFG_SCH_PRIO_0); + 8006e66: 2100 movs r1, #0 + 8006e68: 2002 movs r0, #2 + 8006e6a: f000 fd33 bl 80078d4 <UTIL_SEQ_SetTask> + + return; + 8006e6e: bf00 nop +} + 8006e70: 3708 adds r7, #8 + 8006e72: 46bd mov sp, r7 + 8006e74: bd80 pop {r7, pc} + +08006e76 <hci_cmd_resp_release>: + +void hci_cmd_resp_release(uint32_t Flag) +{ + 8006e76: b580 push {r7, lr} + 8006e78: b082 sub sp, #8 + 8006e7a: af00 add r7, sp, #0 + 8006e7c: 6078 str r0, [r7, #4] + UTIL_SEQ_SetEvt(1 << CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID); + 8006e7e: 2001 movs r0, #1 + 8006e80: f000 fd94 bl 80079ac <UTIL_SEQ_SetEvt> + + return; + 8006e84: bf00 nop +} + 8006e86: 3708 adds r7, #8 + 8006e88: 46bd mov sp, r7 + 8006e8a: bd80 pop {r7, pc} + +08006e8c <hci_cmd_resp_wait>: + +void hci_cmd_resp_wait(uint32_t Timeout) +{ + 8006e8c: b580 push {r7, lr} + 8006e8e: b082 sub sp, #8 + 8006e90: af00 add r7, sp, #0 + 8006e92: 6078 str r0, [r7, #4] + UTIL_SEQ_WaitEvt(1 << CFG_IDLEEVT_HCI_CMD_EVT_RSP_ID); + 8006e94: 2001 movs r0, #1 + 8006e96: f000 fda9 bl 80079ec <UTIL_SEQ_WaitEvt> + + return; + 8006e9a: bf00 nop +} + 8006e9c: 3708 adds r7, #8 + 8006e9e: 46bd mov sp, r7 + 8006ea0: bd80 pop {r7, pc} + +08006ea2 <BLE_UserEvtRx>: + +static void BLE_UserEvtRx(void *p_Payload) +{ + 8006ea2: b580 push {r7, lr} + 8006ea4: b084 sub sp, #16 + 8006ea6: af00 add r7, sp, #0 + 8006ea8: 6078 str r0, [r7, #4] + SVCCTL_UserEvtFlowStatus_t svctl_return_status; + tHCI_UserEvtRxParam *p_param; + + p_param = (tHCI_UserEvtRxParam *)p_Payload; + 8006eaa: 687b ldr r3, [r7, #4] + 8006eac: 60fb str r3, [r7, #12] + + svctl_return_status = SVCCTL_UserEvtRx((void *)&(p_param->pckt->evtserial)); + 8006eae: 68fb ldr r3, [r7, #12] + 8006eb0: 685b ldr r3, [r3, #4] + 8006eb2: 3308 adds r3, #8 + 8006eb4: 4618 mov r0, r3 + 8006eb6: f7fe fd65 bl 8005984 <SVCCTL_UserEvtRx> + 8006eba: 4603 mov r3, r0 + 8006ebc: 72fb strb r3, [r7, #11] + if (svctl_return_status != SVCCTL_UserEvtFlowDisable) + 8006ebe: 7afb ldrb r3, [r7, #11] + 8006ec0: 2b00 cmp r3, #0 + 8006ec2: d003 beq.n 8006ecc <BLE_UserEvtRx+0x2a> + { + p_param->status = HCI_TL_UserEventFlow_Enable; + 8006ec4: 68fb ldr r3, [r7, #12] + 8006ec6: 2201 movs r2, #1 + 8006ec8: 701a strb r2, [r3, #0] + else + { + p_param->status = HCI_TL_UserEventFlow_Disable; + } + + return; + 8006eca: e003 b.n 8006ed4 <BLE_UserEvtRx+0x32> + p_param->status = HCI_TL_UserEventFlow_Disable; + 8006ecc: 68fb ldr r3, [r7, #12] + 8006ece: 2200 movs r2, #0 + 8006ed0: 701a strb r2, [r3, #0] + return; + 8006ed2: bf00 nop +} + 8006ed4: 3710 adds r7, #16 + 8006ed6: 46bd mov sp, r7 + 8006ed8: bd80 pop {r7, pc} + +08006eda <BLE_StatusNot>: + +static void BLE_StatusNot(HCI_TL_CmdStatus_t Status) +{ + 8006eda: b580 push {r7, lr} + 8006edc: b084 sub sp, #16 + 8006ede: af00 add r7, sp, #0 + 8006ee0: 4603 mov r3, r0 + 8006ee2: 71fb strb r3, [r7, #7] + uint32_t task_id_list; + switch (Status) + 8006ee4: 79fb ldrb r3, [r7, #7] + 8006ee6: 2b00 cmp r3, #0 + 8006ee8: d002 beq.n 8006ef0 <BLE_StatusNot+0x16> + 8006eea: 2b01 cmp r3, #1 + 8006eec: d006 beq.n 8006efc <BLE_StatusNot+0x22> + + default: + /* USER CODE BEGIN Status */ + + /* USER CODE END Status */ + break; + 8006eee: e00b b.n 8006f08 <BLE_StatusNot+0x2e> + task_id_list = (1 << CFG_LAST_TASK_ID_WITH_HCICMD) - 1; + 8006ef0: 2303 movs r3, #3 + 8006ef2: 60fb str r3, [r7, #12] + UTIL_SEQ_PauseTask(task_id_list); + 8006ef4: 68f8 ldr r0, [r7, #12] + 8006ef6: f000 fd19 bl 800792c <UTIL_SEQ_PauseTask> + break; + 8006efa: e005 b.n 8006f08 <BLE_StatusNot+0x2e> + task_id_list = (1 << CFG_LAST_TASK_ID_WITH_HCICMD) - 1; + 8006efc: 2303 movs r3, #3 + 8006efe: 60fb str r3, [r7, #12] + UTIL_SEQ_ResumeTask(task_id_list); + 8006f00: 68f8 ldr r0, [r7, #12] + 8006f02: f000 fd33 bl 800796c <UTIL_SEQ_ResumeTask> + break; + 8006f06: bf00 nop + } + + return; + 8006f08: bf00 nop +} + 8006f0a: 3710 adds r7, #16 + 8006f0c: 46bd mov sp, r7 + 8006f0e: bd80 pop {r7, pc} + +08006f10 <P2PS_STM_App_Notification>: + +/* USER CODE END PFP */ + +/* Functions Definition ------------------------------------------------------*/ +void P2PS_STM_App_Notification(P2PS_STM_App_Notification_evt_t *pNotification) +{ + 8006f10: b480 push {r7} + 8006f12: b083 sub sp, #12 + 8006f14: af00 add r7, sp, #0 + 8006f16: 6078 str r0, [r7, #4] +/* USER CODE BEGIN P2PS_STM_App_Notification_1 */ + +/* USER CODE END P2PS_STM_App_Notification_1 */ + switch(pNotification->P2P_Evt_Opcode) + 8006f18: 687b ldr r3, [r7, #4] + 8006f1a: 781b ldrb r3, [r3, #0] + 8006f1c: 2b03 cmp r3, #3 + 8006f1e: d006 beq.n 8006f2e <P2PS_STM_App_Notification+0x1e> + 8006f20: 2b03 cmp r3, #3 + 8006f22: dc06 bgt.n 8006f32 <P2PS_STM_App_Notification+0x22> + 8006f24: 2b00 cmp r3, #0 + 8006f26: d006 beq.n 8006f36 <P2PS_STM_App_Notification+0x26> + 8006f28: 2b01 cmp r3, #1 + 8006f2a: d006 beq.n 8006f3a <P2PS_STM_App_Notification+0x2a> + + default: +/* USER CODE BEGIN P2PS_STM_App_Notification_default */ + +/* USER CODE END P2PS_STM_App_Notification_default */ + break; + 8006f2c: e001 b.n 8006f32 <P2PS_STM_App_Notification+0x22> + break; + 8006f2e: bf00 nop + 8006f30: e004 b.n 8006f3c <P2PS_STM_App_Notification+0x2c> + break; + 8006f32: bf00 nop + 8006f34: e002 b.n 8006f3c <P2PS_STM_App_Notification+0x2c> + break; + 8006f36: bf00 nop + 8006f38: e000 b.n 8006f3c <P2PS_STM_App_Notification+0x2c> + break; + 8006f3a: bf00 nop + } +/* USER CODE BEGIN P2PS_STM_App_Notification_2 */ + +/* USER CODE END P2PS_STM_App_Notification_2 */ + return; + 8006f3c: bf00 nop +} + 8006f3e: 370c adds r7, #12 + 8006f40: 46bd mov sp, r7 + 8006f42: f85d 7b04 ldr.w r7, [sp], #4 + 8006f46: 4770 bx lr + +08006f48 <P2PS_APP_Notification>: + +void P2PS_APP_Notification(P2PS_APP_ConnHandle_Not_evt_t *pNotification) +{ + 8006f48: b480 push {r7} + 8006f4a: b083 sub sp, #12 + 8006f4c: af00 add r7, sp, #0 + 8006f4e: 6078 str r0, [r7, #4] +/* USER CODE BEGIN P2PS_APP_Notification_1 */ + +/* USER CODE END P2PS_APP_Notification_1 */ + switch(pNotification->P2P_Evt_Opcode) + 8006f50: 687b ldr r3, [r7, #4] + 8006f52: 781b ldrb r3, [r3, #0] + 8006f54: 2b00 cmp r3, #0 + 8006f56: d002 beq.n 8006f5e <P2PS_APP_Notification+0x16> + 8006f58: 2b01 cmp r3, #1 + 8006f5a: d002 beq.n 8006f62 <P2PS_APP_Notification+0x1a> + + default: +/* USER CODE BEGIN P2PS_APP_Notification_default */ + +/* USER CODE END P2PS_APP_Notification_default */ + break; + 8006f5c: e002 b.n 8006f64 <P2PS_APP_Notification+0x1c> + break; + 8006f5e: bf00 nop + 8006f60: e000 b.n 8006f64 <P2PS_APP_Notification+0x1c> + break; + 8006f62: bf00 nop + } +/* USER CODE BEGIN P2PS_APP_Notification_2 */ + +/* USER CODE END P2PS_APP_Notification_2 */ + return; + 8006f64: bf00 nop +} + 8006f66: 370c adds r7, #12 + 8006f68: 46bd mov sp, r7 + 8006f6a: f85d 7b04 ldr.w r7, [sp], #4 + 8006f6e: 4770 bx lr + +08006f70 <P2PS_APP_Init>: + +void P2PS_APP_Init(void) +{ + 8006f70: b480 push {r7} + 8006f72: af00 add r7, sp, #0 +/* USER CODE BEGIN P2PS_APP_Init */ + +/* USER CODE END P2PS_APP_Init */ + return; + 8006f74: bf00 nop +} + 8006f76: 46bd mov sp, r7 + 8006f78: f85d 7b04 ldr.w r7, [sp], #4 + 8006f7c: 4770 bx lr + ... + +08006f80 <LL_PWR_EnableBootC2>: +{ + 8006f80: b480 push {r7} + 8006f82: af00 add r7, sp, #0 + SET_BIT(PWR->CR4, PWR_CR4_C2BOOT); + 8006f84: 4b05 ldr r3, [pc, #20] @ (8006f9c <LL_PWR_EnableBootC2+0x1c>) + 8006f86: 68db ldr r3, [r3, #12] + 8006f88: 4a04 ldr r2, [pc, #16] @ (8006f9c <LL_PWR_EnableBootC2+0x1c>) + 8006f8a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 + 8006f8e: 60d3 str r3, [r2, #12] +} + 8006f90: bf00 nop + 8006f92: 46bd mov sp, r7 + 8006f94: f85d 7b04 ldr.w r7, [sp], #4 + 8006f98: 4770 bx lr + 8006f9a: bf00 nop + 8006f9c: 58000400 .word 0x58000400 + +08006fa0 <LL_C2_EXTI_EnableEvent_32_63>: +{ + 8006fa0: b480 push {r7} + 8006fa2: b083 sub sp, #12 + 8006fa4: af00 add r7, sp, #0 + 8006fa6: 6078 str r0, [r7, #4] + SET_BIT(EXTI->C2EMR2, ExtiLine); + 8006fa8: 4b06 ldr r3, [pc, #24] @ (8006fc4 <LL_C2_EXTI_EnableEvent_32_63+0x24>) + 8006faa: f8d3 20d4 ldr.w r2, [r3, #212] @ 0xd4 + 8006fae: 4905 ldr r1, [pc, #20] @ (8006fc4 <LL_C2_EXTI_EnableEvent_32_63+0x24>) + 8006fb0: 687b ldr r3, [r7, #4] + 8006fb2: 4313 orrs r3, r2 + 8006fb4: f8c1 30d4 str.w r3, [r1, #212] @ 0xd4 +} + 8006fb8: bf00 nop + 8006fba: 370c adds r7, #12 + 8006fbc: 46bd mov sp, r7 + 8006fbe: f85d 7b04 ldr.w r7, [sp], #4 + 8006fc2: 4770 bx lr + 8006fc4: 58000800 .word 0x58000800 + +08006fc8 <LL_EXTI_EnableRisingTrig_32_63>: + * @arg @ref LL_EXTI_LINE_41 + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) +{ + 8006fc8: b480 push {r7} + 8006fca: b083 sub sp, #12 + 8006fcc: af00 add r7, sp, #0 + 8006fce: 6078 str r0, [r7, #4] + SET_BIT(EXTI->RTSR2, ExtiLine); + 8006fd0: 4b05 ldr r3, [pc, #20] @ (8006fe8 <LL_EXTI_EnableRisingTrig_32_63+0x20>) + 8006fd2: 6a1a ldr r2, [r3, #32] + 8006fd4: 4904 ldr r1, [pc, #16] @ (8006fe8 <LL_EXTI_EnableRisingTrig_32_63+0x20>) + 8006fd6: 687b ldr r3, [r7, #4] + 8006fd8: 4313 orrs r3, r2 + 8006fda: 620b str r3, [r1, #32] +} + 8006fdc: bf00 nop + 8006fde: 370c adds r7, #12 + 8006fe0: 46bd mov sp, r7 + 8006fe2: f85d 7b04 ldr.w r7, [sp], #4 + 8006fe6: 4770 bx lr + 8006fe8: 58000800 .word 0x58000800 + +08006fec <LL_AHB3_GRP1_EnableClock>: +{ + 8006fec: b480 push {r7} + 8006fee: b085 sub sp, #20 + 8006ff0: af00 add r7, sp, #0 + 8006ff2: 6078 str r0, [r7, #4] + SET_BIT(RCC->AHB3ENR, Periphs); + 8006ff4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8006ff8: 6d1a ldr r2, [r3, #80] @ 0x50 + 8006ffa: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8006ffe: 687b ldr r3, [r7, #4] + 8007000: 4313 orrs r3, r2 + 8007002: 650b str r3, [r1, #80] @ 0x50 + tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); + 8007004: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8007008: 6d1a ldr r2, [r3, #80] @ 0x50 + 800700a: 687b ldr r3, [r7, #4] + 800700c: 4013 ands r3, r2 + 800700e: 60fb str r3, [r7, #12] + (void)tmpreg; + 8007010: 68fb ldr r3, [r7, #12] +} + 8007012: bf00 nop + 8007014: 3714 adds r7, #20 + 8007016: 46bd mov sp, r7 + 8007018: f85d 7b04 ldr.w r7, [sp], #4 + 800701c: 4770 bx lr + +0800701e <LL_C2_AHB3_GRP1_EnableClock>: + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC + * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH + * @retval None + */ +__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + 800701e: b480 push {r7} + 8007020: b085 sub sp, #20 + 8007022: af00 add r7, sp, #0 + 8007024: 6078 str r0, [r7, #4] + __IO uint32_t tmpreg; + SET_BIT(RCC->C2AHB3ENR, Periphs); + 8007026: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800702a: f8d3 2150 ldr.w r2, [r3, #336] @ 0x150 + 800702e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8007032: 687b ldr r3, [r7, #4] + 8007034: 4313 orrs r3, r2 + 8007036: f8c1 3150 str.w r3, [r1, #336] @ 0x150 + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->C2AHB3ENR, Periphs); + 800703a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800703e: f8d3 2150 ldr.w r2, [r3, #336] @ 0x150 + 8007042: 687b ldr r3, [r7, #4] + 8007044: 4013 ands r3, r2 + 8007046: 60fb str r3, [r7, #12] + (void)tmpreg; + 8007048: 68fb ldr r3, [r7, #12] +} + 800704a: bf00 nop + 800704c: 3714 adds r7, #20 + 800704e: 46bd mov sp, r7 + 8007050: f85d 7b04 ldr.w r7, [sp], #4 + 8007054: 4770 bx lr + +08007056 <LL_C1_IPCC_EnableIT_TXF>: + * @rmtoll C1CR TXFIE LL_C1_IPCC_EnableIT_TXF + * @param IPCCx IPCC Instance. + * @retval None + */ +__STATIC_INLINE void LL_C1_IPCC_EnableIT_TXF(IPCC_TypeDef *IPCCx) +{ + 8007056: b480 push {r7} + 8007058: b083 sub sp, #12 + 800705a: af00 add r7, sp, #0 + 800705c: 6078 str r0, [r7, #4] + SET_BIT(IPCCx->C1CR, IPCC_C1CR_TXFIE); + 800705e: 687b ldr r3, [r7, #4] + 8007060: 681b ldr r3, [r3, #0] + 8007062: f443 3280 orr.w r2, r3, #65536 @ 0x10000 + 8007066: 687b ldr r3, [r7, #4] + 8007068: 601a str r2, [r3, #0] +} + 800706a: bf00 nop + 800706c: 370c adds r7, #12 + 800706e: 46bd mov sp, r7 + 8007070: f85d 7b04 ldr.w r7, [sp], #4 + 8007074: 4770 bx lr + +08007076 <LL_C1_IPCC_EnableIT_RXO>: + * @rmtoll C1CR RXOIE LL_C1_IPCC_EnableIT_RXO + * @param IPCCx IPCC Instance. + * @retval None + */ +__STATIC_INLINE void LL_C1_IPCC_EnableIT_RXO(IPCC_TypeDef *IPCCx) +{ + 8007076: b480 push {r7} + 8007078: b083 sub sp, #12 + 800707a: af00 add r7, sp, #0 + 800707c: 6078 str r0, [r7, #4] + SET_BIT(IPCCx->C1CR, IPCC_C1CR_RXOIE); + 800707e: 687b ldr r3, [r7, #4] + 8007080: 681b ldr r3, [r3, #0] + 8007082: f043 0201 orr.w r2, r3, #1 + 8007086: 687b ldr r3, [r7, #4] + 8007088: 601a str r2, [r3, #0] +} + 800708a: bf00 nop + 800708c: 370c adds r7, #12 + 800708e: 46bd mov sp, r7 + 8007090: f85d 7b04 ldr.w r7, [sp], #4 + 8007094: 4770 bx lr + +08007096 <LL_C1_IPCC_EnableTransmitChannel>: + * @arg @ref LL_IPCC_CHANNEL_5 + * @arg @ref LL_IPCC_CHANNEL_6 + * @retval None + */ +__STATIC_INLINE void LL_C1_IPCC_EnableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel) +{ + 8007096: b480 push {r7} + 8007098: b083 sub sp, #12 + 800709a: af00 add r7, sp, #0 + 800709c: 6078 str r0, [r7, #4] + 800709e: 6039 str r1, [r7, #0] + CLEAR_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos); + 80070a0: 687b ldr r3, [r7, #4] + 80070a2: 685a ldr r2, [r3, #4] + 80070a4: 683b ldr r3, [r7, #0] + 80070a6: 041b lsls r3, r3, #16 + 80070a8: 43db mvns r3, r3 + 80070aa: 401a ands r2, r3 + 80070ac: 687b ldr r3, [r7, #4] + 80070ae: 605a str r2, [r3, #4] +} + 80070b0: bf00 nop + 80070b2: 370c adds r7, #12 + 80070b4: 46bd mov sp, r7 + 80070b6: f85d 7b04 ldr.w r7, [sp], #4 + 80070ba: 4770 bx lr + +080070bc <LL_C1_IPCC_DisableTransmitChannel>: + * @arg @ref LL_IPCC_CHANNEL_5 + * @arg @ref LL_IPCC_CHANNEL_6 + * @retval None + */ +__STATIC_INLINE void LL_C1_IPCC_DisableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel) +{ + 80070bc: b480 push {r7} + 80070be: b083 sub sp, #12 + 80070c0: af00 add r7, sp, #0 + 80070c2: 6078 str r0, [r7, #4] + 80070c4: 6039 str r1, [r7, #0] + SET_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos); + 80070c6: 687b ldr r3, [r7, #4] + 80070c8: 685a ldr r2, [r3, #4] + 80070ca: 683b ldr r3, [r7, #0] + 80070cc: 041b lsls r3, r3, #16 + 80070ce: 431a orrs r2, r3 + 80070d0: 687b ldr r3, [r7, #4] + 80070d2: 605a str r2, [r3, #4] +} + 80070d4: bf00 nop + 80070d6: 370c adds r7, #12 + 80070d8: 46bd mov sp, r7 + 80070da: f85d 7b04 ldr.w r7, [sp], #4 + 80070de: 4770 bx lr + +080070e0 <LL_C1_IPCC_EnableReceiveChannel>: + * @arg @ref LL_IPCC_CHANNEL_5 + * @arg @ref LL_IPCC_CHANNEL_6 + * @retval None + */ +__STATIC_INLINE void LL_C1_IPCC_EnableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel) +{ + 80070e0: b480 push {r7} + 80070e2: b083 sub sp, #12 + 80070e4: af00 add r7, sp, #0 + 80070e6: 6078 str r0, [r7, #4] + 80070e8: 6039 str r1, [r7, #0] + CLEAR_BIT(IPCCx->C1MR, Channel); + 80070ea: 687b ldr r3, [r7, #4] + 80070ec: 685a ldr r2, [r3, #4] + 80070ee: 683b ldr r3, [r7, #0] + 80070f0: 43db mvns r3, r3 + 80070f2: 401a ands r2, r3 + 80070f4: 687b ldr r3, [r7, #4] + 80070f6: 605a str r2, [r3, #4] +} + 80070f8: bf00 nop + 80070fa: 370c adds r7, #12 + 80070fc: 46bd mov sp, r7 + 80070fe: f85d 7b04 ldr.w r7, [sp], #4 + 8007102: 4770 bx lr + +08007104 <LL_C1_IPCC_ClearFlag_CHx>: + * @arg @ref LL_IPCC_CHANNEL_5 + * @arg @ref LL_IPCC_CHANNEL_6 + * @retval None + */ +__STATIC_INLINE void LL_C1_IPCC_ClearFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel) +{ + 8007104: b480 push {r7} + 8007106: b083 sub sp, #12 + 8007108: af00 add r7, sp, #0 + 800710a: 6078 str r0, [r7, #4] + 800710c: 6039 str r1, [r7, #0] + WRITE_REG(IPCCx->C1SCR, Channel); + 800710e: 687b ldr r3, [r7, #4] + 8007110: 683a ldr r2, [r7, #0] + 8007112: 609a str r2, [r3, #8] +} + 8007114: bf00 nop + 8007116: 370c adds r7, #12 + 8007118: 46bd mov sp, r7 + 800711a: f85d 7b04 ldr.w r7, [sp], #4 + 800711e: 4770 bx lr + +08007120 <LL_C1_IPCC_SetFlag_CHx>: + * @arg @ref LL_IPCC_CHANNEL_5 + * @arg @ref LL_IPCC_CHANNEL_6 + * @retval None + */ +__STATIC_INLINE void LL_C1_IPCC_SetFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel) +{ + 8007120: b480 push {r7} + 8007122: b083 sub sp, #12 + 8007124: af00 add r7, sp, #0 + 8007126: 6078 str r0, [r7, #4] + 8007128: 6039 str r1, [r7, #0] + WRITE_REG(IPCCx->C1SCR, Channel << IPCC_C1SCR_CH1S_Pos); + 800712a: 683b ldr r3, [r7, #0] + 800712c: 041a lsls r2, r3, #16 + 800712e: 687b ldr r3, [r7, #4] + 8007130: 609a str r2, [r3, #8] +} + 8007132: bf00 nop + 8007134: 370c adds r7, #12 + 8007136: 46bd mov sp, r7 + 8007138: f85d 7b04 ldr.w r7, [sp], #4 + 800713c: 4770 bx lr + +0800713e <LL_C1_IPCC_IsActiveFlag_CHx>: + * @arg @ref LL_IPCC_CHANNEL_5 + * @arg @ref LL_IPCC_CHANNEL_6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const *const IPCCx, uint32_t Channel) +{ + 800713e: b480 push {r7} + 8007140: b083 sub sp, #12 + 8007142: af00 add r7, sp, #0 + 8007144: 6078 str r0, [r7, #4] + 8007146: 6039 str r1, [r7, #0] + return ((READ_BIT(IPCCx->C1TOC2SR, Channel) == (Channel)) ? 1UL : 0UL); + 8007148: 687b ldr r3, [r7, #4] + 800714a: 68da ldr r2, [r3, #12] + 800714c: 683b ldr r3, [r7, #0] + 800714e: 4013 ands r3, r2 + 8007150: 683a ldr r2, [r7, #0] + 8007152: 429a cmp r2, r3 + 8007154: d101 bne.n 800715a <LL_C1_IPCC_IsActiveFlag_CHx+0x1c> + 8007156: 2301 movs r3, #1 + 8007158: e000 b.n 800715c <LL_C1_IPCC_IsActiveFlag_CHx+0x1e> + 800715a: 2300 movs r3, #0 +} + 800715c: 4618 mov r0, r3 + 800715e: 370c adds r7, #12 + 8007160: 46bd mov sp, r7 + 8007162: f85d 7b04 ldr.w r7, [sp], #4 + 8007166: 4770 bx lr + +08007168 <LL_C2_IPCC_IsActiveFlag_CHx>: + * @arg @ref LL_IPCC_CHANNEL_5 + * @arg @ref LL_IPCC_CHANNEL_6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const *const IPCCx, uint32_t Channel) +{ + 8007168: b480 push {r7} + 800716a: b083 sub sp, #12 + 800716c: af00 add r7, sp, #0 + 800716e: 6078 str r0, [r7, #4] + 8007170: 6039 str r1, [r7, #0] + return ((READ_BIT(IPCCx->C2TOC1SR, Channel) == (Channel)) ? 1UL : 0UL); + 8007172: 687b ldr r3, [r7, #4] + 8007174: 69da ldr r2, [r3, #28] + 8007176: 683b ldr r3, [r7, #0] + 8007178: 4013 ands r3, r2 + 800717a: 683a ldr r2, [r7, #0] + 800717c: 429a cmp r2, r3 + 800717e: d101 bne.n 8007184 <LL_C2_IPCC_IsActiveFlag_CHx+0x1c> + 8007180: 2301 movs r3, #1 + 8007182: e000 b.n 8007186 <LL_C2_IPCC_IsActiveFlag_CHx+0x1e> + 8007184: 2300 movs r3, #0 +} + 8007186: 4618 mov r0, r3 + 8007188: 370c adds r7, #12 + 800718a: 46bd mov sp, r7 + 800718c: f85d 7b04 ldr.w r7, [sp], #4 + 8007190: 4770 bx lr + ... + +08007194 <HW_IPCC_Rx_Handler>: + +/****************************************************************************** + * INTERRUPT HANDLER + ******************************************************************************/ +void HW_IPCC_Rx_Handler( void ) +{ + 8007194: b580 push {r7, lr} + 8007196: af00 add r7, sp, #0 + if (HW_IPCC_RX_PENDING( HW_IPCC_SYSTEM_EVENT_CHANNEL )) + 8007198: 2102 movs r1, #2 + 800719a: 4818 ldr r0, [pc, #96] @ (80071fc <HW_IPCC_Rx_Handler+0x68>) + 800719c: f7ff ffe4 bl 8007168 <LL_C2_IPCC_IsActiveFlag_CHx> + 80071a0: 4603 mov r3, r0 + 80071a2: 2b00 cmp r3, #0 + 80071a4: d008 beq.n 80071b8 <HW_IPCC_Rx_Handler+0x24> + 80071a6: 4b15 ldr r3, [pc, #84] @ (80071fc <HW_IPCC_Rx_Handler+0x68>) + 80071a8: 685b ldr r3, [r3, #4] + 80071aa: f003 0302 and.w r3, r3, #2 + 80071ae: 2b00 cmp r3, #0 + 80071b0: d102 bne.n 80071b8 <HW_IPCC_Rx_Handler+0x24> + { + HW_IPCC_SYS_EvtHandler(); + 80071b2: f000 f925 bl 8007400 <HW_IPCC_SYS_EvtHandler> + 80071b6: e01e b.n 80071f6 <HW_IPCC_Rx_Handler+0x62> + else if (HW_IPCC_RX_PENDING( HW_IPCC_ZIGBEE_M0_REQUEST_CHANNEL )) + { + HW_IPCC_ZIGBEE_StackM0RequestHandler(); + } +#endif /* ZIGBEE_WB */ + else if (HW_IPCC_RX_PENDING( HW_IPCC_BLE_EVENT_CHANNEL )) + 80071b8: 2101 movs r1, #1 + 80071ba: 4810 ldr r0, [pc, #64] @ (80071fc <HW_IPCC_Rx_Handler+0x68>) + 80071bc: f7ff ffd4 bl 8007168 <LL_C2_IPCC_IsActiveFlag_CHx> + 80071c0: 4603 mov r3, r0 + 80071c2: 2b00 cmp r3, #0 + 80071c4: d008 beq.n 80071d8 <HW_IPCC_Rx_Handler+0x44> + 80071c6: 4b0d ldr r3, [pc, #52] @ (80071fc <HW_IPCC_Rx_Handler+0x68>) + 80071c8: 685b ldr r3, [r3, #4] + 80071ca: f003 0301 and.w r3, r3, #1 + 80071ce: 2b00 cmp r3, #0 + 80071d0: d102 bne.n 80071d8 <HW_IPCC_Rx_Handler+0x44> + { + HW_IPCC_BLE_EvtHandler(); + 80071d2: f000 f899 bl 8007308 <HW_IPCC_BLE_EvtHandler> + 80071d6: e00e b.n 80071f6 <HW_IPCC_Rx_Handler+0x62> + } + else if (HW_IPCC_RX_PENDING( HW_IPCC_TRACES_CHANNEL )) + 80071d8: 2108 movs r1, #8 + 80071da: 4808 ldr r0, [pc, #32] @ (80071fc <HW_IPCC_Rx_Handler+0x68>) + 80071dc: f7ff ffc4 bl 8007168 <LL_C2_IPCC_IsActiveFlag_CHx> + 80071e0: 4603 mov r3, r0 + 80071e2: 2b00 cmp r3, #0 + 80071e4: d008 beq.n 80071f8 <HW_IPCC_Rx_Handler+0x64> + 80071e6: 4b05 ldr r3, [pc, #20] @ (80071fc <HW_IPCC_Rx_Handler+0x68>) + 80071e8: 685b ldr r3, [r3, #4] + 80071ea: f003 0308 and.w r3, r3, #8 + 80071ee: 2b00 cmp r3, #0 + 80071f0: d102 bne.n 80071f8 <HW_IPCC_Rx_Handler+0x64> + { + HW_IPCC_TRACES_EvtHandler(); + 80071f2: f000 f97d bl 80074f0 <HW_IPCC_TRACES_EvtHandler> + } + + return; + 80071f6: bf00 nop + 80071f8: bf00 nop +} + 80071fa: bd80 pop {r7, pc} + 80071fc: 58000c00 .word 0x58000c00 + +08007200 <HW_IPCC_Tx_Handler>: + +void HW_IPCC_Tx_Handler( void ) +{ + 8007200: b580 push {r7, lr} + 8007202: af00 add r7, sp, #0 + if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL )) + 8007204: 2102 movs r1, #2 + 8007206: 4818 ldr r0, [pc, #96] @ (8007268 <HW_IPCC_Tx_Handler+0x68>) + 8007208: f7ff ff99 bl 800713e <LL_C1_IPCC_IsActiveFlag_CHx> + 800720c: 4603 mov r3, r0 + 800720e: 2b00 cmp r3, #0 + 8007210: d108 bne.n 8007224 <HW_IPCC_Tx_Handler+0x24> + 8007212: 4b15 ldr r3, [pc, #84] @ (8007268 <HW_IPCC_Tx_Handler+0x68>) + 8007214: 685b ldr r3, [r3, #4] + 8007216: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 800721a: 2b00 cmp r3, #0 + 800721c: d102 bne.n 8007224 <HW_IPCC_Tx_Handler+0x24> + { + HW_IPCC_SYS_CmdEvtHandler(); + 800721e: f000 f8d3 bl 80073c8 <HW_IPCC_SYS_CmdEvtHandler> + 8007222: e01e b.n 8007262 <HW_IPCC_Tx_Handler+0x62> + if (HW_IPCC_TX_PENDING( HW_IPCC_ZIGBEE_CMD_APPLI_CHANNEL )) + { + HW_IPCC_ZIGBEE_CmdEvtHandler(); + } +#endif /* ZIGBEE_WB */ + else if (HW_IPCC_TX_PENDING( HW_IPCC_MM_RELEASE_BUFFER_CHANNEL )) + 8007224: 2108 movs r1, #8 + 8007226: 4810 ldr r0, [pc, #64] @ (8007268 <HW_IPCC_Tx_Handler+0x68>) + 8007228: f7ff ff89 bl 800713e <LL_C1_IPCC_IsActiveFlag_CHx> + 800722c: 4603 mov r3, r0 + 800722e: 2b00 cmp r3, #0 + 8007230: d108 bne.n 8007244 <HW_IPCC_Tx_Handler+0x44> + 8007232: 4b0d ldr r3, [pc, #52] @ (8007268 <HW_IPCC_Tx_Handler+0x68>) + 8007234: 685b ldr r3, [r3, #4] + 8007236: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 800723a: 2b00 cmp r3, #0 + 800723c: d102 bne.n 8007244 <HW_IPCC_Tx_Handler+0x44> + { + HW_IPCC_MM_FreeBufHandler(); + 800723e: f000 f919 bl 8007474 <HW_IPCC_MM_FreeBufHandler> + 8007242: e00e b.n 8007262 <HW_IPCC_Tx_Handler+0x62> + } + else if (HW_IPCC_TX_PENDING( HW_IPCC_HCI_ACL_DATA_CHANNEL )) + 8007244: 2120 movs r1, #32 + 8007246: 4808 ldr r0, [pc, #32] @ (8007268 <HW_IPCC_Tx_Handler+0x68>) + 8007248: f7ff ff79 bl 800713e <LL_C1_IPCC_IsActiveFlag_CHx> + 800724c: 4603 mov r3, r0 + 800724e: 2b00 cmp r3, #0 + 8007250: d108 bne.n 8007264 <HW_IPCC_Tx_Handler+0x64> + 8007252: 4b05 ldr r3, [pc, #20] @ (8007268 <HW_IPCC_Tx_Handler+0x68>) + 8007254: 685b ldr r3, [r3, #4] + 8007256: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 800725a: 2b00 cmp r3, #0 + 800725c: d102 bne.n 8007264 <HW_IPCC_Tx_Handler+0x64> + { + HW_IPCC_BLE_AclDataEvtHandler(); + 800725e: f000 f85f bl 8007320 <HW_IPCC_BLE_AclDataEvtHandler> + } + + return; + 8007262: bf00 nop + 8007264: bf00 nop +} + 8007266: bd80 pop {r7, pc} + 8007268: 58000c00 .word 0x58000c00 + +0800726c <HW_IPCC_Enable>: +/****************************************************************************** + * GENERAL + ******************************************************************************/ +void HW_IPCC_Enable( void ) +{ + 800726c: b580 push {r7, lr} + 800726e: af00 add r7, sp, #0 + /** + * Such as IPCC IP available to the CPU2, it is required to keep the IPCC clock running + * when FUS is running on CPU2 and CPU1 enters deep sleep mode + */ + LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC); + 8007270: f44f 1080 mov.w r0, #1048576 @ 0x100000 + 8007274: f7ff fed3 bl 800701e <LL_C2_AHB3_GRP1_EnableClock> + + /** + * When the device is out of standby, it is required to use the EXTI mechanism to wakeup CPU2 + */ + LL_EXTI_EnableRisingTrig_32_63( LL_EXTI_LINE_41 ); + 8007278: f44f 7000 mov.w r0, #512 @ 0x200 + 800727c: f7ff fea4 bl 8006fc8 <LL_EXTI_EnableRisingTrig_32_63> + /* It is required to have at least a system clock cycle before a SEV after LL_EXTI_EnableRisingTrig_32_63() */ + LL_C2_EXTI_EnableEvent_32_63( LL_EXTI_LINE_41 ); + 8007280: f44f 7000 mov.w r0, #512 @ 0x200 + 8007284: f7ff fe8c bl 8006fa0 <LL_C2_EXTI_EnableEvent_32_63> + * When the CPU2 receives that command, it waits for its event input to be set to restart the CPU2 firmware. + * This is required because once C2BOOT has been set once, a clear/set on C2BOOT has no effect. + * When SHCI_C2_Reinit( ) is not called, generating an event to the CPU2 does not have any effect + * So, by default, the application shall both set the event flag and set the C2BOOT bit. + */ + __SEV( ); /* Set the internal event flag and send an event to the CPU2 */ + 8007288: bf40 sev + __WFE( ); /* Clear the internal event flag */ + 800728a: bf20 wfe + LL_PWR_EnableBootC2( ); + 800728c: f7ff fe78 bl 8006f80 <LL_PWR_EnableBootC2> + + return; + 8007290: bf00 nop +} + 8007292: bd80 pop {r7, pc} + +08007294 <HW_IPCC_Init>: + +void HW_IPCC_Init( void ) +{ + 8007294: b580 push {r7, lr} + 8007296: af00 add r7, sp, #0 + LL_AHB3_GRP1_EnableClock( LL_AHB3_GRP1_PERIPH_IPCC ); + 8007298: f44f 1080 mov.w r0, #1048576 @ 0x100000 + 800729c: f7ff fea6 bl 8006fec <LL_AHB3_GRP1_EnableClock> + + LL_C1_IPCC_EnableIT_RXO( IPCC ); + 80072a0: 4806 ldr r0, [pc, #24] @ (80072bc <HW_IPCC_Init+0x28>) + 80072a2: f7ff fee8 bl 8007076 <LL_C1_IPCC_EnableIT_RXO> + LL_C1_IPCC_EnableIT_TXF( IPCC ); + 80072a6: 4805 ldr r0, [pc, #20] @ (80072bc <HW_IPCC_Init+0x28>) + 80072a8: f7ff fed5 bl 8007056 <LL_C1_IPCC_EnableIT_TXF> + + HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn); + 80072ac: 202c movs r0, #44 @ 0x2c + 80072ae: f7fa fcf2 bl 8001c96 <HAL_NVIC_EnableIRQ> + HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn); + 80072b2: 202d movs r0, #45 @ 0x2d + 80072b4: f7fa fcef bl 8001c96 <HAL_NVIC_EnableIRQ> + + return; + 80072b8: bf00 nop +} + 80072ba: bd80 pop {r7, pc} + 80072bc: 58000c00 .word 0x58000c00 + +080072c0 <HW_IPCC_BLE_Init>: + +/****************************************************************************** + * BLE + ******************************************************************************/ +void HW_IPCC_BLE_Init( void ) +{ + 80072c0: b580 push {r7, lr} + 80072c2: b084 sub sp, #16 + 80072c4: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 80072c6: f3ef 8310 mrs r3, PRIMASK + 80072ca: 607b str r3, [r7, #4] + return(result); + 80072cc: 687b ldr r3, [r7, #4] + UTILS_ENTER_CRITICAL_SECTION(); + 80072ce: 60fb str r3, [r7, #12] + __ASM volatile ("cpsid i" : : : "memory"); + 80072d0: b672 cpsid i +} + 80072d2: bf00 nop + LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_BLE_EVENT_CHANNEL ); + 80072d4: 2101 movs r1, #1 + 80072d6: 4806 ldr r0, [pc, #24] @ (80072f0 <HW_IPCC_BLE_Init+0x30>) + 80072d8: f7ff ff02 bl 80070e0 <LL_C1_IPCC_EnableReceiveChannel> + 80072dc: 68fb ldr r3, [r7, #12] + 80072de: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80072e0: 68bb ldr r3, [r7, #8] + 80072e2: f383 8810 msr PRIMASK, r3 +} + 80072e6: bf00 nop + UTILS_EXIT_CRITICAL_SECTION(); + + return; + 80072e8: bf00 nop +} + 80072ea: 3710 adds r7, #16 + 80072ec: 46bd mov sp, r7 + 80072ee: bd80 pop {r7, pc} + 80072f0: 58000c00 .word 0x58000c00 + +080072f4 <HW_IPCC_BLE_SendCmd>: + +void HW_IPCC_BLE_SendCmd( void ) +{ + 80072f4: b580 push {r7, lr} + 80072f6: af00 add r7, sp, #0 + LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_BLE_CMD_CHANNEL ); + 80072f8: 2101 movs r1, #1 + 80072fa: 4802 ldr r0, [pc, #8] @ (8007304 <HW_IPCC_BLE_SendCmd+0x10>) + 80072fc: f7ff ff10 bl 8007120 <LL_C1_IPCC_SetFlag_CHx> + + return; + 8007300: bf00 nop +} + 8007302: bd80 pop {r7, pc} + 8007304: 58000c00 .word 0x58000c00 + +08007308 <HW_IPCC_BLE_EvtHandler>: + +static void HW_IPCC_BLE_EvtHandler( void ) +{ + 8007308: b580 push {r7, lr} + 800730a: af00 add r7, sp, #0 + HW_IPCC_BLE_RxEvtNot(); + 800730c: f7fe ffe4 bl 80062d8 <HW_IPCC_BLE_RxEvtNot> + + LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_BLE_EVENT_CHANNEL ); + 8007310: 2101 movs r1, #1 + 8007312: 4802 ldr r0, [pc, #8] @ (800731c <HW_IPCC_BLE_EvtHandler+0x14>) + 8007314: f7ff fef6 bl 8007104 <LL_C1_IPCC_ClearFlag_CHx> + + return; + 8007318: bf00 nop +} + 800731a: bd80 pop {r7, pc} + 800731c: 58000c00 .word 0x58000c00 + +08007320 <HW_IPCC_BLE_AclDataEvtHandler>: + + return; +} + +static void HW_IPCC_BLE_AclDataEvtHandler( void ) +{ + 8007320: b580 push {r7, lr} + 8007322: b084 sub sp, #16 + 8007324: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8007326: f3ef 8310 mrs r3, PRIMASK + 800732a: 607b str r3, [r7, #4] + return(result); + 800732c: 687b ldr r3, [r7, #4] + UTILS_ENTER_CRITICAL_SECTION(); + 800732e: 60fb str r3, [r7, #12] + __ASM volatile ("cpsid i" : : : "memory"); + 8007330: b672 cpsid i +} + 8007332: bf00 nop + LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL ); + 8007334: 2120 movs r1, #32 + 8007336: 4807 ldr r0, [pc, #28] @ (8007354 <HW_IPCC_BLE_AclDataEvtHandler+0x34>) + 8007338: f7ff fec0 bl 80070bc <LL_C1_IPCC_DisableTransmitChannel> + 800733c: 68fb ldr r3, [r7, #12] + 800733e: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8007340: 68bb ldr r3, [r7, #8] + 8007342: f383 8810 msr PRIMASK, r3 +} + 8007346: bf00 nop + UTILS_EXIT_CRITICAL_SECTION(); + + HW_IPCC_BLE_AclDataAckNot(); + 8007348: f7fe fff6 bl 8006338 <HW_IPCC_BLE_AclDataAckNot> + + return; + 800734c: bf00 nop +} + 800734e: 3710 adds r7, #16 + 8007350: 46bd mov sp, r7 + 8007352: bd80 pop {r7, pc} + 8007354: 58000c00 .word 0x58000c00 + +08007358 <HW_IPCC_SYS_Init>: + +/****************************************************************************** + * SYSTEM + ******************************************************************************/ +void HW_IPCC_SYS_Init( void ) +{ + 8007358: b580 push {r7, lr} + 800735a: b084 sub sp, #16 + 800735c: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800735e: f3ef 8310 mrs r3, PRIMASK + 8007362: 607b str r3, [r7, #4] + return(result); + 8007364: 687b ldr r3, [r7, #4] + UTILS_ENTER_CRITICAL_SECTION(); + 8007366: 60fb str r3, [r7, #12] + __ASM volatile ("cpsid i" : : : "memory"); + 8007368: b672 cpsid i +} + 800736a: bf00 nop + LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL ); + 800736c: 2102 movs r1, #2 + 800736e: 4806 ldr r0, [pc, #24] @ (8007388 <HW_IPCC_SYS_Init+0x30>) + 8007370: f7ff feb6 bl 80070e0 <LL_C1_IPCC_EnableReceiveChannel> + 8007374: 68fb ldr r3, [r7, #12] + 8007376: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8007378: 68bb ldr r3, [r7, #8] + 800737a: f383 8810 msr PRIMASK, r3 +} + 800737e: bf00 nop + UTILS_EXIT_CRITICAL_SECTION(); + + return; + 8007380: bf00 nop +} + 8007382: 3710 adds r7, #16 + 8007384: 46bd mov sp, r7 + 8007386: bd80 pop {r7, pc} + 8007388: 58000c00 .word 0x58000c00 + +0800738c <HW_IPCC_SYS_SendCmd>: + +void HW_IPCC_SYS_SendCmd( void ) +{ + 800738c: b580 push {r7, lr} + 800738e: b084 sub sp, #16 + 8007390: af00 add r7, sp, #0 + LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ); + 8007392: 2102 movs r1, #2 + 8007394: 480b ldr r0, [pc, #44] @ (80073c4 <HW_IPCC_SYS_SendCmd+0x38>) + 8007396: f7ff fec3 bl 8007120 <LL_C1_IPCC_SetFlag_CHx> + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800739a: f3ef 8310 mrs r3, PRIMASK + 800739e: 607b str r3, [r7, #4] + return(result); + 80073a0: 687b ldr r3, [r7, #4] + UTILS_ENTER_CRITICAL_SECTION(); + 80073a2: 60fb str r3, [r7, #12] + __ASM volatile ("cpsid i" : : : "memory"); + 80073a4: b672 cpsid i +} + 80073a6: bf00 nop + LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ); + 80073a8: 2102 movs r1, #2 + 80073aa: 4806 ldr r0, [pc, #24] @ (80073c4 <HW_IPCC_SYS_SendCmd+0x38>) + 80073ac: f7ff fe73 bl 8007096 <LL_C1_IPCC_EnableTransmitChannel> + 80073b0: 68fb ldr r3, [r7, #12] + 80073b2: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80073b4: 68bb ldr r3, [r7, #8] + 80073b6: f383 8810 msr PRIMASK, r3 +} + 80073ba: bf00 nop + UTILS_EXIT_CRITICAL_SECTION(); + + return; + 80073bc: bf00 nop +} + 80073be: 3710 adds r7, #16 + 80073c0: 46bd mov sp, r7 + 80073c2: bd80 pop {r7, pc} + 80073c4: 58000c00 .word 0x58000c00 + +080073c8 <HW_IPCC_SYS_CmdEvtHandler>: + +static void HW_IPCC_SYS_CmdEvtHandler( void ) +{ + 80073c8: b580 push {r7, lr} + 80073ca: b084 sub sp, #16 + 80073cc: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 80073ce: f3ef 8310 mrs r3, PRIMASK + 80073d2: 607b str r3, [r7, #4] + return(result); + 80073d4: 687b ldr r3, [r7, #4] + UTILS_ENTER_CRITICAL_SECTION(); + 80073d6: 60fb str r3, [r7, #12] + __ASM volatile ("cpsid i" : : : "memory"); + 80073d8: b672 cpsid i +} + 80073da: bf00 nop + LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ); + 80073dc: 2102 movs r1, #2 + 80073de: 4807 ldr r0, [pc, #28] @ (80073fc <HW_IPCC_SYS_CmdEvtHandler+0x34>) + 80073e0: f7ff fe6c bl 80070bc <LL_C1_IPCC_DisableTransmitChannel> + 80073e4: 68fb ldr r3, [r7, #12] + 80073e6: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80073e8: 68bb ldr r3, [r7, #8] + 80073ea: f383 8810 msr PRIMASK, r3 +} + 80073ee: bf00 nop + UTILS_EXIT_CRITICAL_SECTION(); + + HW_IPCC_SYS_CmdEvtNot(); + 80073f0: f7fe fff6 bl 80063e0 <HW_IPCC_SYS_CmdEvtNot> + + return; + 80073f4: bf00 nop +} + 80073f6: 3710 adds r7, #16 + 80073f8: 46bd mov sp, r7 + 80073fa: bd80 pop {r7, pc} + 80073fc: 58000c00 .word 0x58000c00 + +08007400 <HW_IPCC_SYS_EvtHandler>: + +static void HW_IPCC_SYS_EvtHandler( void ) +{ + 8007400: b580 push {r7, lr} + 8007402: af00 add r7, sp, #0 + HW_IPCC_SYS_EvtNot(); + 8007404: f7ff f802 bl 800640c <HW_IPCC_SYS_EvtNot> + + LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL ); + 8007408: 2102 movs r1, #2 + 800740a: 4802 ldr r0, [pc, #8] @ (8007414 <HW_IPCC_SYS_EvtHandler+0x14>) + 800740c: f7ff fe7a bl 8007104 <LL_C1_IPCC_ClearFlag_CHx> + + return; + 8007410: bf00 nop +} + 8007412: bd80 pop {r7, pc} + 8007414: 58000c00 .word 0x58000c00 + +08007418 <HW_IPCC_MM_SendFreeBuf>: + +/****************************************************************************** + * MEMORY MANAGER + ******************************************************************************/ +void HW_IPCC_MM_SendFreeBuf( void (*cb)( void ) ) +{ + 8007418: b580 push {r7, lr} + 800741a: b086 sub sp, #24 + 800741c: af00 add r7, sp, #0 + 800741e: 6078 str r0, [r7, #4] + if ( LL_C1_IPCC_IsActiveFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ) ) + 8007420: 2108 movs r1, #8 + 8007422: 4812 ldr r0, [pc, #72] @ (800746c <HW_IPCC_MM_SendFreeBuf+0x54>) + 8007424: f7ff fe8b bl 800713e <LL_C1_IPCC_IsActiveFlag_CHx> + 8007428: 4603 mov r3, r0 + 800742a: 2b00 cmp r3, #0 + 800742c: d013 beq.n 8007456 <HW_IPCC_MM_SendFreeBuf+0x3e> + { + FreeBufCb = cb; + 800742e: 4a10 ldr r2, [pc, #64] @ (8007470 <HW_IPCC_MM_SendFreeBuf+0x58>) + 8007430: 687b ldr r3, [r7, #4] + 8007432: 6013 str r3, [r2, #0] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8007434: f3ef 8310 mrs r3, PRIMASK + 8007438: 60fb str r3, [r7, #12] + return(result); + 800743a: 68fb ldr r3, [r7, #12] + UTILS_ENTER_CRITICAL_SECTION(); + 800743c: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800743e: b672 cpsid i +} + 8007440: bf00 nop + LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ); + 8007442: 2108 movs r1, #8 + 8007444: 4809 ldr r0, [pc, #36] @ (800746c <HW_IPCC_MM_SendFreeBuf+0x54>) + 8007446: f7ff fe26 bl 8007096 <LL_C1_IPCC_EnableTransmitChannel> + 800744a: 697b ldr r3, [r7, #20] + 800744c: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800744e: 693b ldr r3, [r7, #16] + 8007450: f383 8810 msr PRIMASK, r3 +} + 8007454: e005 b.n 8007462 <HW_IPCC_MM_SendFreeBuf+0x4a> + UTILS_EXIT_CRITICAL_SECTION(); + } + else + { + cb(); + 8007456: 687b ldr r3, [r7, #4] + 8007458: 4798 blx r3 + + LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ); + 800745a: 2108 movs r1, #8 + 800745c: 4803 ldr r0, [pc, #12] @ (800746c <HW_IPCC_MM_SendFreeBuf+0x54>) + 800745e: f7ff fe5f bl 8007120 <LL_C1_IPCC_SetFlag_CHx> + } + + return; + 8007462: bf00 nop +} + 8007464: 3718 adds r7, #24 + 8007466: 46bd mov sp, r7 + 8007468: bd80 pop {r7, pc} + 800746a: bf00 nop + 800746c: 58000c00 .word 0x58000c00 + 8007470: 200002fc .word 0x200002fc + +08007474 <HW_IPCC_MM_FreeBufHandler>: + +static void HW_IPCC_MM_FreeBufHandler( void ) +{ + 8007474: b580 push {r7, lr} + 8007476: b084 sub sp, #16 + 8007478: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800747a: f3ef 8310 mrs r3, PRIMASK + 800747e: 607b str r3, [r7, #4] + return(result); + 8007480: 687b ldr r3, [r7, #4] + UTILS_ENTER_CRITICAL_SECTION(); + 8007482: 60fb str r3, [r7, #12] + __ASM volatile ("cpsid i" : : : "memory"); + 8007484: b672 cpsid i +} + 8007486: bf00 nop + LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ); + 8007488: 2108 movs r1, #8 + 800748a: 480a ldr r0, [pc, #40] @ (80074b4 <HW_IPCC_MM_FreeBufHandler+0x40>) + 800748c: f7ff fe16 bl 80070bc <LL_C1_IPCC_DisableTransmitChannel> + 8007490: 68fb ldr r3, [r7, #12] + 8007492: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8007494: 68bb ldr r3, [r7, #8] + 8007496: f383 8810 msr PRIMASK, r3 +} + 800749a: bf00 nop + UTILS_EXIT_CRITICAL_SECTION(); + + FreeBufCb(); + 800749c: 4b06 ldr r3, [pc, #24] @ (80074b8 <HW_IPCC_MM_FreeBufHandler+0x44>) + 800749e: 681b ldr r3, [r3, #0] + 80074a0: 4798 blx r3 + + LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ); + 80074a2: 2108 movs r1, #8 + 80074a4: 4803 ldr r0, [pc, #12] @ (80074b4 <HW_IPCC_MM_FreeBufHandler+0x40>) + 80074a6: f7ff fe3b bl 8007120 <LL_C1_IPCC_SetFlag_CHx> + + return; + 80074aa: bf00 nop +} + 80074ac: 3710 adds r7, #16 + 80074ae: 46bd mov sp, r7 + 80074b0: bd80 pop {r7, pc} + 80074b2: bf00 nop + 80074b4: 58000c00 .word 0x58000c00 + 80074b8: 200002fc .word 0x200002fc + +080074bc <HW_IPCC_TRACES_Init>: + +/****************************************************************************** + * TRACES + ******************************************************************************/ +void HW_IPCC_TRACES_Init( void ) +{ + 80074bc: b580 push {r7, lr} + 80074be: b084 sub sp, #16 + 80074c0: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 80074c2: f3ef 8310 mrs r3, PRIMASK + 80074c6: 607b str r3, [r7, #4] + return(result); + 80074c8: 687b ldr r3, [r7, #4] + UTILS_ENTER_CRITICAL_SECTION(); + 80074ca: 60fb str r3, [r7, #12] + __ASM volatile ("cpsid i" : : : "memory"); + 80074cc: b672 cpsid i +} + 80074ce: bf00 nop + LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_TRACES_CHANNEL ); + 80074d0: 2108 movs r1, #8 + 80074d2: 4806 ldr r0, [pc, #24] @ (80074ec <HW_IPCC_TRACES_Init+0x30>) + 80074d4: f7ff fe04 bl 80070e0 <LL_C1_IPCC_EnableReceiveChannel> + 80074d8: 68fb ldr r3, [r7, #12] + 80074da: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80074dc: 68bb ldr r3, [r7, #8] + 80074de: f383 8810 msr PRIMASK, r3 +} + 80074e2: bf00 nop + UTILS_EXIT_CRITICAL_SECTION(); + + return; + 80074e4: bf00 nop +} + 80074e6: 3710 adds r7, #16 + 80074e8: 46bd mov sp, r7 + 80074ea: bd80 pop {r7, pc} + 80074ec: 58000c00 .word 0x58000c00 + +080074f0 <HW_IPCC_TRACES_EvtHandler>: + +static void HW_IPCC_TRACES_EvtHandler( void ) +{ + 80074f0: b580 push {r7, lr} + 80074f2: af00 add r7, sp, #0 + HW_IPCC_TRACES_EvtNot(); + 80074f4: f7ff f832 bl 800655c <HW_IPCC_TRACES_EvtNot> + + LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_TRACES_CHANNEL ); + 80074f8: 2108 movs r1, #8 + 80074fa: 4802 ldr r0, [pc, #8] @ (8007504 <HW_IPCC_TRACES_EvtHandler+0x14>) + 80074fc: f7ff fe02 bl 8007104 <LL_C1_IPCC_ClearFlag_CHx> + + return; + 8007500: bf00 nop +} + 8007502: bd80 pop {r7, pc} + 8007504: 58000c00 .word 0x58000c00 + +08007508 <UTIL_LPM_Init>: + +/** @addtogroup TINY_LPM_Exported_function + * @{ + */ +void UTIL_LPM_Init( void ) +{ + 8007508: b480 push {r7} + 800750a: af00 add r7, sp, #0 + StopModeDisable = UTIL_LPM_NO_BIT_SET; + 800750c: 4b05 ldr r3, [pc, #20] @ (8007524 <UTIL_LPM_Init+0x1c>) + 800750e: 2200 movs r2, #0 + 8007510: 601a str r2, [r3, #0] + OffModeDisable = UTIL_LPM_NO_BIT_SET; + 8007512: 4b05 ldr r3, [pc, #20] @ (8007528 <UTIL_LPM_Init+0x20>) + 8007514: 2200 movs r2, #0 + 8007516: 601a str r2, [r3, #0] + UTIL_LPM_INIT_CRITICAL_SECTION( ); +} + 8007518: bf00 nop + 800751a: 46bd mov sp, r7 + 800751c: f85d 7b04 ldr.w r7, [sp], #4 + 8007520: 4770 bx lr + 8007522: bf00 nop + 8007524: 20000300 .word 0x20000300 + 8007528: 20000304 .word 0x20000304 + +0800752c <UTIL_LPM_SetOffMode>: + + UTIL_LPM_EXIT_CRITICAL_SECTION( ); +} + +void UTIL_LPM_SetOffMode( UTIL_LPM_bm_t lpm_id_bm, UTIL_LPM_State_t state ) +{ + 800752c: b480 push {r7} + 800752e: b087 sub sp, #28 + 8007530: af00 add r7, sp, #0 + 8007532: 6078 str r0, [r7, #4] + 8007534: 460b mov r3, r1 + 8007536: 70fb strb r3, [r7, #3] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8007538: f3ef 8310 mrs r3, PRIMASK + 800753c: 613b str r3, [r7, #16] + return(result); + 800753e: 693b ldr r3, [r7, #16] + UTIL_LPM_ENTER_CRITICAL_SECTION( ); + 8007540: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 8007542: b672 cpsid i +} + 8007544: bf00 nop + + switch(state) + 8007546: 78fb ldrb r3, [r7, #3] + 8007548: 2b00 cmp r3, #0 + 800754a: d008 beq.n 800755e <UTIL_LPM_SetOffMode+0x32> + 800754c: 2b01 cmp r3, #1 + 800754e: d10e bne.n 800756e <UTIL_LPM_SetOffMode+0x42> + { + case UTIL_LPM_DISABLE: + { + OffModeDisable |= lpm_id_bm; + 8007550: 4b0d ldr r3, [pc, #52] @ (8007588 <UTIL_LPM_SetOffMode+0x5c>) + 8007552: 681a ldr r2, [r3, #0] + 8007554: 687b ldr r3, [r7, #4] + 8007556: 4313 orrs r3, r2 + 8007558: 4a0b ldr r2, [pc, #44] @ (8007588 <UTIL_LPM_SetOffMode+0x5c>) + 800755a: 6013 str r3, [r2, #0] + break; + 800755c: e008 b.n 8007570 <UTIL_LPM_SetOffMode+0x44> + } + case UTIL_LPM_ENABLE: + { + OffModeDisable &= ( ~lpm_id_bm ); + 800755e: 687b ldr r3, [r7, #4] + 8007560: 43da mvns r2, r3 + 8007562: 4b09 ldr r3, [pc, #36] @ (8007588 <UTIL_LPM_SetOffMode+0x5c>) + 8007564: 681b ldr r3, [r3, #0] + 8007566: 4013 ands r3, r2 + 8007568: 4a07 ldr r2, [pc, #28] @ (8007588 <UTIL_LPM_SetOffMode+0x5c>) + 800756a: 6013 str r3, [r2, #0] + break; + 800756c: e000 b.n 8007570 <UTIL_LPM_SetOffMode+0x44> + } + default : + { + break; + 800756e: bf00 nop + 8007570: 697b ldr r3, [r7, #20] + 8007572: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8007574: 68fb ldr r3, [r7, #12] + 8007576: f383 8810 msr PRIMASK, r3 +} + 800757a: bf00 nop + } + } + + UTIL_LPM_EXIT_CRITICAL_SECTION( ); +} + 800757c: bf00 nop + 800757e: 371c adds r7, #28 + 8007580: 46bd mov sp, r7 + 8007582: f85d 7b04 ldr.w r7, [sp], #4 + 8007586: 4770 bx lr + 8007588: 20000304 .word 0x20000304 + +0800758c <UTIL_SEQ_Run>: + * That is the reason why many variables that are used only in that function are declared static. + * Note: These variables could have been declared static in the function. + * + */ +void UTIL_SEQ_Run( UTIL_SEQ_bm_t Mask_bm ) +{ + 800758c: b580 push {r7, lr} + 800758e: b094 sub sp, #80 @ 0x50 + 8007590: af00 add r7, sp, #0 + 8007592: 6078 str r0, [r7, #4] + /* + * When this function is nested, the mask to be applied cannot be larger than the first call + * The mask is always getting smaller and smaller + * A copy is made of the mask set by UTIL_SEQ_Run() in case it is called again in the task + */ + super_mask_backup = SuperMask; + 8007594: 4b89 ldr r3, [pc, #548] @ (80077bc <UTIL_SEQ_Run+0x230>) + 8007596: 681b ldr r3, [r3, #0] + 8007598: 62fb str r3, [r7, #44] @ 0x2c + SuperMask &= Mask_bm; + 800759a: 4b88 ldr r3, [pc, #544] @ (80077bc <UTIL_SEQ_Run+0x230>) + 800759c: 681a ldr r2, [r3, #0] + 800759e: 687b ldr r3, [r7, #4] + 80075a0: 4013 ands r3, r2 + 80075a2: 4a86 ldr r2, [pc, #536] @ (80077bc <UTIL_SEQ_Run+0x230>) + 80075a4: 6013 str r3, [r2, #0] + * TaskMask that comes from UTIL_SEQ_PauseTask() / UTIL_SEQ_ResumeTask + * SuperMask that comes from UTIL_SEQ_Run + * If the waited event is there, exit from UTIL_SEQ_Run() to return to the + * waiting task + */ + local_taskset = TaskSet; + 80075a6: 4b86 ldr r3, [pc, #536] @ (80077c0 <UTIL_SEQ_Run+0x234>) + 80075a8: 681b ldr r3, [r3, #0] + 80075aa: 647b str r3, [r7, #68] @ 0x44 + local_evtset = EvtSet; + 80075ac: 4b85 ldr r3, [pc, #532] @ (80077c4 <UTIL_SEQ_Run+0x238>) + 80075ae: 681b ldr r3, [r3, #0] + 80075b0: 643b str r3, [r7, #64] @ 0x40 + local_taskmask = TaskMask; + 80075b2: 4b85 ldr r3, [pc, #532] @ (80077c8 <UTIL_SEQ_Run+0x23c>) + 80075b4: 681b ldr r3, [r3, #0] + 80075b6: 63fb str r3, [r7, #60] @ 0x3c + local_evtwaited = EvtWaited; + 80075b8: 4b84 ldr r3, [pc, #528] @ (80077cc <UTIL_SEQ_Run+0x240>) + 80075ba: 681b ldr r3, [r3, #0] + 80075bc: 63bb str r3, [r7, #56] @ 0x38 + while(((local_taskset & local_taskmask & SuperMask) != 0U) && ((local_evtset & local_evtwaited)==0U)) + 80075be: e112 b.n 80077e6 <UTIL_SEQ_Run+0x25a> + { + counter = 0U; + 80075c0: 2300 movs r3, #0 + 80075c2: 64fb str r3, [r7, #76] @ 0x4c + /* + * When a flag is set, the associated bit is set in TaskPrio[counter].priority mask depending + * on the priority parameter given from UTIL_SEQ_SetTask() + * The while loop is looking for a flag set from the highest priority maskr to the lower + */ + while((TaskPrio[counter].priority & local_taskmask & SuperMask)== 0U) + 80075c4: e002 b.n 80075cc <UTIL_SEQ_Run+0x40> + { + counter++; + 80075c6: 6cfb ldr r3, [r7, #76] @ 0x4c + 80075c8: 3301 adds r3, #1 + 80075ca: 64fb str r3, [r7, #76] @ 0x4c + while((TaskPrio[counter].priority & local_taskmask & SuperMask)== 0U) + 80075cc: 4a80 ldr r2, [pc, #512] @ (80077d0 <UTIL_SEQ_Run+0x244>) + 80075ce: 6cfb ldr r3, [r7, #76] @ 0x4c + 80075d0: f852 2033 ldr.w r2, [r2, r3, lsl #3] + 80075d4: 6bfb ldr r3, [r7, #60] @ 0x3c + 80075d6: 401a ands r2, r3 + 80075d8: 4b78 ldr r3, [pc, #480] @ (80077bc <UTIL_SEQ_Run+0x230>) + 80075da: 681b ldr r3, [r3, #0] + 80075dc: 4013 ands r3, r2 + 80075de: 2b00 cmp r3, #0 + 80075e0: d0f1 beq.n 80075c6 <UTIL_SEQ_Run+0x3a> + } + + current_task_set = TaskPrio[counter].priority & local_taskmask & SuperMask; + 80075e2: 4a7b ldr r2, [pc, #492] @ (80077d0 <UTIL_SEQ_Run+0x244>) + 80075e4: 6cfb ldr r3, [r7, #76] @ 0x4c + 80075e6: f852 2033 ldr.w r2, [r2, r3, lsl #3] + 80075ea: 6bfb ldr r3, [r7, #60] @ 0x3c + 80075ec: 401a ands r2, r3 + 80075ee: 4b73 ldr r3, [pc, #460] @ (80077bc <UTIL_SEQ_Run+0x230>) + 80075f0: 681b ldr r3, [r3, #0] + 80075f2: 4013 ands r3, r2 + 80075f4: 64bb str r3, [r7, #72] @ 0x48 + * the round_robin mask + * + * In the check below, the round_robin mask is reinitialize in case all pending + * tasks haven been executed at least once + */ + if ((TaskPrio[counter].round_robin & current_task_set) == 0U) + 80075f6: 4a76 ldr r2, [pc, #472] @ (80077d0 <UTIL_SEQ_Run+0x244>) + 80075f8: 6cfb ldr r3, [r7, #76] @ 0x4c + 80075fa: 00db lsls r3, r3, #3 + 80075fc: 4413 add r3, r2 + 80075fe: 685a ldr r2, [r3, #4] + 8007600: 6cbb ldr r3, [r7, #72] @ 0x48 + 8007602: 4013 ands r3, r2 + 8007604: 2b00 cmp r3, #0 + 8007606: d106 bne.n 8007616 <UTIL_SEQ_Run+0x8a> + { + TaskPrio[counter].round_robin = UTIL_SEQ_ALL_BIT_SET; + 8007608: 4a71 ldr r2, [pc, #452] @ (80077d0 <UTIL_SEQ_Run+0x244>) + 800760a: 6cfb ldr r3, [r7, #76] @ 0x4c + 800760c: 00db lsls r3, r3, #3 + 800760e: 4413 add r3, r2 + 8007610: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8007614: 605a str r2, [r3, #4] + + /* + * Compute the Stack Startving List + * This is the list of the task that have been set at least once minus the one that have been cleared ar least once + */ + task_starving_list = TaskSet; + 8007616: 4b6a ldr r3, [pc, #424] @ (80077c0 <UTIL_SEQ_Run+0x234>) + 8007618: 681b ldr r3, [r3, #0] + 800761a: 62bb str r3, [r7, #40] @ 0x28 + * Such situation shall not happen when evaluating task_starving_list + * At any time, there should not be any bit reset in TaskPrio[counter].round_robin and reset in TaskClearList + * It is correct with regard to the Sequencer Architecture to set in TaskClearList all tasks that are said to be executed from TaskPrio[counter].round_robin + * This synchronizes both information before calculating the CurrentTaskIdx + */ + TaskClearList |= (~TaskPrio[counter].round_robin); + 800761c: 4a6c ldr r2, [pc, #432] @ (80077d0 <UTIL_SEQ_Run+0x244>) + 800761e: 6cfb ldr r3, [r7, #76] @ 0x4c + 8007620: 00db lsls r3, r3, #3 + 8007622: 4413 add r3, r2 + 8007624: 685b ldr r3, [r3, #4] + 8007626: 43da mvns r2, r3 + 8007628: 4b6a ldr r3, [pc, #424] @ (80077d4 <UTIL_SEQ_Run+0x248>) + 800762a: 681b ldr r3, [r3, #0] + 800762c: 4313 orrs r3, r2 + 800762e: 4a69 ldr r2, [pc, #420] @ (80077d4 <UTIL_SEQ_Run+0x248>) + 8007630: 6013 str r3, [r2, #0] + + task_starving_list &= (~TaskClearList); + 8007632: 4b68 ldr r3, [pc, #416] @ (80077d4 <UTIL_SEQ_Run+0x248>) + 8007634: 681b ldr r3, [r3, #0] + 8007636: 43db mvns r3, r3 + 8007638: 6aba ldr r2, [r7, #40] @ 0x28 + 800763a: 4013 ands r3, r2 + 800763c: 62bb str r3, [r7, #40] @ 0x28 + + /* + * Consider first the starving list and update current_task_set accordingly + */ + if ((task_starving_list & current_task_set) != 0U) + 800763e: 6aba ldr r2, [r7, #40] @ 0x28 + 8007640: 6cbb ldr r3, [r7, #72] @ 0x48 + 8007642: 4013 ands r3, r2 + 8007644: 2b00 cmp r3, #0 + 8007646: d003 beq.n 8007650 <UTIL_SEQ_Run+0xc4> + { + current_task_set = (task_starving_list & current_task_set); + 8007648: 6cba ldr r2, [r7, #72] @ 0x48 + 800764a: 6abb ldr r3, [r7, #40] @ 0x28 + 800764c: 4013 ands r3, r2 + 800764e: 64bb str r3, [r7, #72] @ 0x48 + } + + /* + * Reinitialize the Starving List if required + */ + if(task_starving_list == 0) + 8007650: 6abb ldr r3, [r7, #40] @ 0x28 + 8007652: 2b00 cmp r3, #0 + 8007654: d102 bne.n 800765c <UTIL_SEQ_Run+0xd0> + { + TaskClearList = 0; + 8007656: 4b5f ldr r3, [pc, #380] @ (80077d4 <UTIL_SEQ_Run+0x248>) + 8007658: 2200 movs r2, #0 + 800765a: 601a str r2, [r3, #0] + /* + * Read the flag index of the task to be executed + * Once the index is read, the associated task will be executed even though a higher priority stack is requested + * before task execution. + */ + CurrentTaskIdx = (SEQ_BitPosition(current_task_set & TaskPrio[counter].round_robin)); + 800765c: 4a5c ldr r2, [pc, #368] @ (80077d0 <UTIL_SEQ_Run+0x244>) + 800765e: 6cfb ldr r3, [r7, #76] @ 0x4c + 8007660: 00db lsls r3, r3, #3 + 8007662: 4413 add r3, r2 + 8007664: 685a ldr r2, [r3, #4] + 8007666: 6cbb ldr r3, [r7, #72] @ 0x48 + 8007668: 4013 ands r3, r2 + 800766a: 4618 mov r0, r3 + 800766c: f000 fa43 bl 8007af6 <SEQ_BitPosition> + 8007670: 4603 mov r3, r0 + 8007672: 461a mov r2, r3 + 8007674: 4b58 ldr r3, [pc, #352] @ (80077d8 <UTIL_SEQ_Run+0x24c>) + 8007676: 601a str r2, [r3, #0] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8007678: f3ef 8310 mrs r3, PRIMASK + 800767c: 61fb str r3, [r7, #28] + return(result); + 800767e: 69fb ldr r3, [r7, #28] + + UTIL_SEQ_ENTER_CRITICAL_SECTION( ); + 8007680: 627b str r3, [r7, #36] @ 0x24 + __ASM volatile ("cpsid i" : : : "memory"); + 8007682: b672 cpsid i +} + 8007684: bf00 nop + /* remove from the list or pending task the one that has been selected to be executed */ + TaskSet &= ~(1U << CurrentTaskIdx); + 8007686: 4b54 ldr r3, [pc, #336] @ (80077d8 <UTIL_SEQ_Run+0x24c>) + 8007688: 681b ldr r3, [r3, #0] + 800768a: 2201 movs r2, #1 + 800768c: fa02 f303 lsl.w r3, r2, r3 + 8007690: 43da mvns r2, r3 + 8007692: 4b4b ldr r3, [pc, #300] @ (80077c0 <UTIL_SEQ_Run+0x234>) + 8007694: 681b ldr r3, [r3, #0] + 8007696: 4013 ands r3, r2 + 8007698: 4a49 ldr r2, [pc, #292] @ (80077c0 <UTIL_SEQ_Run+0x234>) + 800769a: 6013 str r3, [r2, #0] + + /* + * remove from all priority mask the task that has been selected to be executed + */ + for (counter = UTIL_SEQ_CONF_PRIO_NBR; counter != 0U; counter--) + 800769c: 2301 movs r3, #1 + 800769e: 64fb str r3, [r7, #76] @ 0x4c + 80076a0: e013 b.n 80076ca <UTIL_SEQ_Run+0x13e> + { + TaskPrio[counter - 1u].priority &= ~(1U << CurrentTaskIdx); + 80076a2: 6cfb ldr r3, [r7, #76] @ 0x4c + 80076a4: 3b01 subs r3, #1 + 80076a6: 4a4a ldr r2, [pc, #296] @ (80077d0 <UTIL_SEQ_Run+0x244>) + 80076a8: f852 1033 ldr.w r1, [r2, r3, lsl #3] + 80076ac: 4b4a ldr r3, [pc, #296] @ (80077d8 <UTIL_SEQ_Run+0x24c>) + 80076ae: 681b ldr r3, [r3, #0] + 80076b0: 2201 movs r2, #1 + 80076b2: fa02 f303 lsl.w r3, r2, r3 + 80076b6: 43da mvns r2, r3 + 80076b8: 6cfb ldr r3, [r7, #76] @ 0x4c + 80076ba: 3b01 subs r3, #1 + 80076bc: 400a ands r2, r1 + 80076be: 4944 ldr r1, [pc, #272] @ (80077d0 <UTIL_SEQ_Run+0x244>) + 80076c0: f841 2033 str.w r2, [r1, r3, lsl #3] + for (counter = UTIL_SEQ_CONF_PRIO_NBR; counter != 0U; counter--) + 80076c4: 6cfb ldr r3, [r7, #76] @ 0x4c + 80076c6: 3b01 subs r3, #1 + 80076c8: 64fb str r3, [r7, #76] @ 0x4c + 80076ca: 6cfb ldr r3, [r7, #76] @ 0x4c + 80076cc: 2b00 cmp r3, #0 + 80076ce: d1e8 bne.n 80076a2 <UTIL_SEQ_Run+0x116> + 80076d0: 6a7b ldr r3, [r7, #36] @ 0x24 + 80076d2: 61bb str r3, [r7, #24] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80076d4: 69bb ldr r3, [r7, #24] + 80076d6: f383 8810 msr PRIMASK, r3 +} + 80076da: bf00 nop + } + UTIL_SEQ_EXIT_CRITICAL_SECTION( ); + + UTIL_SEQ_PreTask(CurrentTaskIdx); + 80076dc: 4b3e ldr r3, [pc, #248] @ (80077d8 <UTIL_SEQ_Run+0x24c>) + 80076de: 681b ldr r3, [r3, #0] + 80076e0: 4618 mov r0, r3 + 80076e2: f000 f9e9 bl 8007ab8 <UTIL_SEQ_PreTask> + + /* + * Check that function exists before calling it + */ + if ((CurrentTaskIdx < UTIL_SEQ_CONF_TASK_NBR) && (TaskCb[CurrentTaskIdx] != NULL)) + 80076e6: 4b3c ldr r3, [pc, #240] @ (80077d8 <UTIL_SEQ_Run+0x24c>) + 80076e8: 681b ldr r3, [r3, #0] + 80076ea: 2b1f cmp r3, #31 + 80076ec: d878 bhi.n 80077e0 <UTIL_SEQ_Run+0x254> + 80076ee: 4b3a ldr r3, [pc, #232] @ (80077d8 <UTIL_SEQ_Run+0x24c>) + 80076f0: 681b ldr r3, [r3, #0] + 80076f2: 4a3a ldr r2, [pc, #232] @ (80077dc <UTIL_SEQ_Run+0x250>) + 80076f4: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80076f8: 2b00 cmp r3, #0 + 80076fa: d071 beq.n 80077e0 <UTIL_SEQ_Run+0x254> + { + /* + * save the round-robin value to take into account the operation done in UTIL_SEQ_WaitEvt + */ + for (uint32_t index = 0; index < UTIL_SEQ_CONF_PRIO_NBR; index++) + 80076fc: 2300 movs r3, #0 + 80076fe: 637b str r3, [r7, #52] @ 0x34 + 8007700: e01e b.n 8007740 <UTIL_SEQ_Run+0x1b4> + { + TaskPrio[index].round_robin &= ~(1U << CurrentTaskIdx); + 8007702: 4a33 ldr r2, [pc, #204] @ (80077d0 <UTIL_SEQ_Run+0x244>) + 8007704: 6b7b ldr r3, [r7, #52] @ 0x34 + 8007706: 00db lsls r3, r3, #3 + 8007708: 4413 add r3, r2 + 800770a: 685a ldr r2, [r3, #4] + 800770c: 4b32 ldr r3, [pc, #200] @ (80077d8 <UTIL_SEQ_Run+0x24c>) + 800770e: 681b ldr r3, [r3, #0] + 8007710: 2101 movs r1, #1 + 8007712: fa01 f303 lsl.w r3, r1, r3 + 8007716: 43db mvns r3, r3 + 8007718: 401a ands r2, r3 + 800771a: 492d ldr r1, [pc, #180] @ (80077d0 <UTIL_SEQ_Run+0x244>) + 800771c: 6b7b ldr r3, [r7, #52] @ 0x34 + 800771e: 00db lsls r3, r3, #3 + 8007720: 440b add r3, r1 + 8007722: 605a str r2, [r3, #4] + round_robin[index] = TaskPrio[index].round_robin; + 8007724: 4a2a ldr r2, [pc, #168] @ (80077d0 <UTIL_SEQ_Run+0x244>) + 8007726: 6b7b ldr r3, [r7, #52] @ 0x34 + 8007728: 00db lsls r3, r3, #3 + 800772a: 4413 add r3, r2 + 800772c: 685a ldr r2, [r3, #4] + 800772e: 6b7b ldr r3, [r7, #52] @ 0x34 + 8007730: 009b lsls r3, r3, #2 + 8007732: 3350 adds r3, #80 @ 0x50 + 8007734: 443b add r3, r7 + 8007736: f843 2c44 str.w r2, [r3, #-68] + for (uint32_t index = 0; index < UTIL_SEQ_CONF_PRIO_NBR; index++) + 800773a: 6b7b ldr r3, [r7, #52] @ 0x34 + 800773c: 3301 adds r3, #1 + 800773e: 637b str r3, [r7, #52] @ 0x34 + 8007740: 6b7b ldr r3, [r7, #52] @ 0x34 + 8007742: 2b00 cmp r3, #0 + 8007744: d0dd beq.n 8007702 <UTIL_SEQ_Run+0x176> + } + + /* Execute the task */ + TaskCb[CurrentTaskIdx]( ); + 8007746: 4b24 ldr r3, [pc, #144] @ (80077d8 <UTIL_SEQ_Run+0x24c>) + 8007748: 681b ldr r3, [r3, #0] + 800774a: 4a24 ldr r2, [pc, #144] @ (80077dc <UTIL_SEQ_Run+0x250>) + 800774c: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8007750: 4798 blx r3 + + /* + * restore the round-robin context + */ + for (uint32_t index = 0; index < UTIL_SEQ_CONF_PRIO_NBR; index++) + 8007752: 2300 movs r3, #0 + 8007754: 633b str r3, [r7, #48] @ 0x30 + 8007756: e013 b.n 8007780 <UTIL_SEQ_Run+0x1f4> + { + TaskPrio[index].round_robin &= round_robin[index]; + 8007758: 4a1d ldr r2, [pc, #116] @ (80077d0 <UTIL_SEQ_Run+0x244>) + 800775a: 6b3b ldr r3, [r7, #48] @ 0x30 + 800775c: 00db lsls r3, r3, #3 + 800775e: 4413 add r3, r2 + 8007760: 685a ldr r2, [r3, #4] + 8007762: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007764: 009b lsls r3, r3, #2 + 8007766: 3350 adds r3, #80 @ 0x50 + 8007768: 443b add r3, r7 + 800776a: f853 3c44 ldr.w r3, [r3, #-68] + 800776e: 401a ands r2, r3 + 8007770: 4917 ldr r1, [pc, #92] @ (80077d0 <UTIL_SEQ_Run+0x244>) + 8007772: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007774: 00db lsls r3, r3, #3 + 8007776: 440b add r3, r1 + 8007778: 605a str r2, [r3, #4] + for (uint32_t index = 0; index < UTIL_SEQ_CONF_PRIO_NBR; index++) + 800777a: 6b3b ldr r3, [r7, #48] @ 0x30 + 800777c: 3301 adds r3, #1 + 800777e: 633b str r3, [r7, #48] @ 0x30 + 8007780: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007782: 2b00 cmp r3, #0 + 8007784: d0e8 beq.n 8007758 <UTIL_SEQ_Run+0x1cc> + } + + UTIL_SEQ_PostTask(CurrentTaskIdx); + 8007786: 4b14 ldr r3, [pc, #80] @ (80077d8 <UTIL_SEQ_Run+0x24c>) + 8007788: 681b ldr r3, [r3, #0] + 800778a: 4618 mov r0, r3 + 800778c: f000 f99e bl 8007acc <UTIL_SEQ_PostTask> + + local_taskset = TaskSet; + 8007790: 4b0b ldr r3, [pc, #44] @ (80077c0 <UTIL_SEQ_Run+0x234>) + 8007792: 681b ldr r3, [r3, #0] + 8007794: 647b str r3, [r7, #68] @ 0x44 + local_evtset = EvtSet; + 8007796: 4b0b ldr r3, [pc, #44] @ (80077c4 <UTIL_SEQ_Run+0x238>) + 8007798: 681b ldr r3, [r3, #0] + 800779a: 643b str r3, [r7, #64] @ 0x40 + local_taskmask = TaskMask; + 800779c: 4b0a ldr r3, [pc, #40] @ (80077c8 <UTIL_SEQ_Run+0x23c>) + 800779e: 681b ldr r3, [r3, #0] + 80077a0: 63fb str r3, [r7, #60] @ 0x3c + local_evtwaited = EvtWaited; + 80077a2: 4b0a ldr r3, [pc, #40] @ (80077cc <UTIL_SEQ_Run+0x240>) + 80077a4: 681b ldr r3, [r3, #0] + 80077a6: 63bb str r3, [r7, #56] @ 0x38 + + /* + * Update the two list for next round + */ + TaskClearList |= (1U << CurrentTaskIdx); + 80077a8: 4b0b ldr r3, [pc, #44] @ (80077d8 <UTIL_SEQ_Run+0x24c>) + 80077aa: 681b ldr r3, [r3, #0] + 80077ac: 2201 movs r2, #1 + 80077ae: 409a lsls r2, r3 + 80077b0: 4b08 ldr r3, [pc, #32] @ (80077d4 <UTIL_SEQ_Run+0x248>) + 80077b2: 681b ldr r3, [r3, #0] + 80077b4: 4313 orrs r3, r2 + 80077b6: 4a07 ldr r2, [pc, #28] @ (80077d4 <UTIL_SEQ_Run+0x248>) + 80077b8: 6013 str r3, [r2, #0] + 80077ba: e014 b.n 80077e6 <UTIL_SEQ_Run+0x25a> + 80077bc: 20000028 .word 0x20000028 + 80077c0: 20000308 .word 0x20000308 + 80077c4: 2000030c .word 0x2000030c + 80077c8: 20000024 .word 0x20000024 + 80077cc: 20000310 .word 0x20000310 + 80077d0: 20000398 .word 0x20000398 + 80077d4: 200003a0 .word 0x200003a0 + 80077d8: 20000314 .word 0x20000314 + 80077dc: 20000318 .word 0x20000318 + else + { + /* + * must never occurs, it means there is a warning in the system + */ + UTIL_SEQ_CatchWarning(UTIL_SEQ_WARNING_INVALIDTASKID); + 80077e0: 2000 movs r0, #0 + 80077e2: f000 f97d bl 8007ae0 <UTIL_SEQ_CatchWarning> + while(((local_taskset & local_taskmask & SuperMask) != 0U) && ((local_evtset & local_evtwaited)==0U)) + 80077e6: 6c7a ldr r2, [r7, #68] @ 0x44 + 80077e8: 6bfb ldr r3, [r7, #60] @ 0x3c + 80077ea: 401a ands r2, r3 + 80077ec: 4b22 ldr r3, [pc, #136] @ (8007878 <UTIL_SEQ_Run+0x2ec>) + 80077ee: 681b ldr r3, [r3, #0] + 80077f0: 4013 ands r3, r2 + 80077f2: 2b00 cmp r3, #0 + 80077f4: d005 beq.n 8007802 <UTIL_SEQ_Run+0x276> + 80077f6: 6c3a ldr r2, [r7, #64] @ 0x40 + 80077f8: 6bbb ldr r3, [r7, #56] @ 0x38 + 80077fa: 4013 ands r3, r2 + 80077fc: 2b00 cmp r3, #0 + 80077fe: f43f aedf beq.w 80075c0 <UTIL_SEQ_Run+0x34> + } + } + + /* the set of CurrentTaskIdx to no task running allows to call WaitEvt in the Pre/Post ilde context */ + CurrentTaskIdx = UTIL_SEQ_NOTASKRUNNING; + 8007802: 4b1e ldr r3, [pc, #120] @ (800787c <UTIL_SEQ_Run+0x2f0>) + 8007804: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8007808: 601a str r2, [r3, #0] + /* if a waited event is present, ignore the IDLE sequence */ + if ((local_evtset & EvtWaited)== 0U) + 800780a: 4b1d ldr r3, [pc, #116] @ (8007880 <UTIL_SEQ_Run+0x2f4>) + 800780c: 681a ldr r2, [r3, #0] + 800780e: 6c3b ldr r3, [r7, #64] @ 0x40 + 8007810: 4013 ands r3, r2 + 8007812: 2b00 cmp r3, #0 + 8007814: d129 bne.n 800786a <UTIL_SEQ_Run+0x2de> + { + UTIL_SEQ_PreIdle( ); + 8007816: f000 f941 bl 8007a9c <UTIL_SEQ_PreIdle> + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800781a: f3ef 8310 mrs r3, PRIMASK + 800781e: 617b str r3, [r7, #20] + return(result); + 8007820: 697b ldr r3, [r7, #20] + + UTIL_SEQ_ENTER_CRITICAL_SECTION_IDLE( ); + 8007822: 623b str r3, [r7, #32] + __ASM volatile ("cpsid i" : : : "memory"); + 8007824: b672 cpsid i +} + 8007826: bf00 nop + local_taskset = TaskSet; + 8007828: 4b16 ldr r3, [pc, #88] @ (8007884 <UTIL_SEQ_Run+0x2f8>) + 800782a: 681b ldr r3, [r3, #0] + 800782c: 647b str r3, [r7, #68] @ 0x44 + local_evtset = EvtSet; + 800782e: 4b16 ldr r3, [pc, #88] @ (8007888 <UTIL_SEQ_Run+0x2fc>) + 8007830: 681b ldr r3, [r3, #0] + 8007832: 643b str r3, [r7, #64] @ 0x40 + local_taskmask = TaskMask; + 8007834: 4b15 ldr r3, [pc, #84] @ (800788c <UTIL_SEQ_Run+0x300>) + 8007836: 681b ldr r3, [r3, #0] + 8007838: 63fb str r3, [r7, #60] @ 0x3c + if ((local_taskset & local_taskmask & SuperMask) == 0U) + 800783a: 6c7a ldr r2, [r7, #68] @ 0x44 + 800783c: 6bfb ldr r3, [r7, #60] @ 0x3c + 800783e: 401a ands r2, r3 + 8007840: 4b0d ldr r3, [pc, #52] @ (8007878 <UTIL_SEQ_Run+0x2ec>) + 8007842: 681b ldr r3, [r3, #0] + 8007844: 4013 ands r3, r2 + 8007846: 2b00 cmp r3, #0 + 8007848: d107 bne.n 800785a <UTIL_SEQ_Run+0x2ce> + { + if ((local_evtset & EvtWaited)== 0U) + 800784a: 4b0d ldr r3, [pc, #52] @ (8007880 <UTIL_SEQ_Run+0x2f4>) + 800784c: 681a ldr r2, [r3, #0] + 800784e: 6c3b ldr r3, [r7, #64] @ 0x40 + 8007850: 4013 ands r3, r2 + 8007852: 2b00 cmp r3, #0 + 8007854: d101 bne.n 800785a <UTIL_SEQ_Run+0x2ce> + { + UTIL_SEQ_Idle( ); + 8007856: f7f8 fed5 bl 8000604 <UTIL_SEQ_Idle> + 800785a: 6a3b ldr r3, [r7, #32] + 800785c: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800785e: 693b ldr r3, [r7, #16] + 8007860: f383 8810 msr PRIMASK, r3 +} + 8007864: bf00 nop + } + } + UTIL_SEQ_EXIT_CRITICAL_SECTION_IDLE( ); + + UTIL_SEQ_PostIdle( ); + 8007866: f000 f920 bl 8007aaa <UTIL_SEQ_PostIdle> + } + + /* restore the mask from UTIL_SEQ_Run() */ + SuperMask = super_mask_backup; + 800786a: 4a03 ldr r2, [pc, #12] @ (8007878 <UTIL_SEQ_Run+0x2ec>) + 800786c: 6afb ldr r3, [r7, #44] @ 0x2c + 800786e: 6013 str r3, [r2, #0] + + return; + 8007870: bf00 nop +} + 8007872: 3750 adds r7, #80 @ 0x50 + 8007874: 46bd mov sp, r7 + 8007876: bd80 pop {r7, pc} + 8007878: 20000028 .word 0x20000028 + 800787c: 20000314 .word 0x20000314 + 8007880: 20000310 .word 0x20000310 + 8007884: 20000308 .word 0x20000308 + 8007888: 2000030c .word 0x2000030c + 800788c: 20000024 .word 0x20000024 + +08007890 <UTIL_SEQ_RegTask>: + +void UTIL_SEQ_RegTask(UTIL_SEQ_bm_t TaskId_bm, uint32_t Flags, void (*Task)( void )) +{ + 8007890: b580 push {r7, lr} + 8007892: b088 sub sp, #32 + 8007894: af00 add r7, sp, #0 + 8007896: 60f8 str r0, [r7, #12] + 8007898: 60b9 str r1, [r7, #8] + 800789a: 607a str r2, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800789c: f3ef 8310 mrs r3, PRIMASK + 80078a0: 617b str r3, [r7, #20] + return(result); + 80078a2: 697b ldr r3, [r7, #20] + (void)Flags; + UTIL_SEQ_ENTER_CRITICAL_SECTION(); + 80078a4: 61fb str r3, [r7, #28] + __ASM volatile ("cpsid i" : : : "memory"); + 80078a6: b672 cpsid i +} + 80078a8: bf00 nop + + TaskCb[SEQ_BitPosition(TaskId_bm)] = Task; + 80078aa: 68f8 ldr r0, [r7, #12] + 80078ac: f000 f923 bl 8007af6 <SEQ_BitPosition> + 80078b0: 4603 mov r3, r0 + 80078b2: 4619 mov r1, r3 + 80078b4: 4a06 ldr r2, [pc, #24] @ (80078d0 <UTIL_SEQ_RegTask+0x40>) + 80078b6: 687b ldr r3, [r7, #4] + 80078b8: f842 3021 str.w r3, [r2, r1, lsl #2] + 80078bc: 69fb ldr r3, [r7, #28] + 80078be: 61bb str r3, [r7, #24] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80078c0: 69bb ldr r3, [r7, #24] + 80078c2: f383 8810 msr PRIMASK, r3 +} + 80078c6: bf00 nop + + UTIL_SEQ_EXIT_CRITICAL_SECTION(); + + return; + 80078c8: bf00 nop +} + 80078ca: 3720 adds r7, #32 + 80078cc: 46bd mov sp, r7 + 80078ce: bd80 pop {r7, pc} + 80078d0: 20000318 .word 0x20000318 + +080078d4 <UTIL_SEQ_SetTask>: + UTIL_SEQ_EXIT_CRITICAL_SECTION(); + return _status; +} + +void UTIL_SEQ_SetTask( UTIL_SEQ_bm_t TaskId_bm, uint32_t Task_Prio ) +{ + 80078d4: b480 push {r7} + 80078d6: b087 sub sp, #28 + 80078d8: af00 add r7, sp, #0 + 80078da: 6078 str r0, [r7, #4] + 80078dc: 6039 str r1, [r7, #0] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 80078de: f3ef 8310 mrs r3, PRIMASK + 80078e2: 60fb str r3, [r7, #12] + return(result); + 80078e4: 68fb ldr r3, [r7, #12] + UTIL_SEQ_ENTER_CRITICAL_SECTION( ); + 80078e6: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 80078e8: b672 cpsid i +} + 80078ea: bf00 nop + + TaskSet |= TaskId_bm; + 80078ec: 4b0d ldr r3, [pc, #52] @ (8007924 <UTIL_SEQ_SetTask+0x50>) + 80078ee: 681a ldr r2, [r3, #0] + 80078f0: 687b ldr r3, [r7, #4] + 80078f2: 4313 orrs r3, r2 + 80078f4: 4a0b ldr r2, [pc, #44] @ (8007924 <UTIL_SEQ_SetTask+0x50>) + 80078f6: 6013 str r3, [r2, #0] + TaskPrio[Task_Prio].priority |= TaskId_bm; + 80078f8: 4a0b ldr r2, [pc, #44] @ (8007928 <UTIL_SEQ_SetTask+0x54>) + 80078fa: 683b ldr r3, [r7, #0] + 80078fc: f852 2033 ldr.w r2, [r2, r3, lsl #3] + 8007900: 687b ldr r3, [r7, #4] + 8007902: 431a orrs r2, r3 + 8007904: 4908 ldr r1, [pc, #32] @ (8007928 <UTIL_SEQ_SetTask+0x54>) + 8007906: 683b ldr r3, [r7, #0] + 8007908: f841 2033 str.w r2, [r1, r3, lsl #3] + 800790c: 697b ldr r3, [r7, #20] + 800790e: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8007910: 693b ldr r3, [r7, #16] + 8007912: f383 8810 msr PRIMASK, r3 +} + 8007916: bf00 nop + + UTIL_SEQ_EXIT_CRITICAL_SECTION( ); + + return; + 8007918: bf00 nop +} + 800791a: 371c adds r7, #28 + 800791c: 46bd mov sp, r7 + 800791e: f85d 7b04 ldr.w r7, [sp], #4 + 8007922: 4770 bx lr + 8007924: 20000308 .word 0x20000308 + 8007928: 20000398 .word 0x20000398 + +0800792c <UTIL_SEQ_PauseTask>: + UTIL_SEQ_EXIT_CRITICAL_SECTION(); + return _status; +} + +void UTIL_SEQ_PauseTask( UTIL_SEQ_bm_t TaskId_bm ) +{ + 800792c: b480 push {r7} + 800792e: b087 sub sp, #28 + 8007930: af00 add r7, sp, #0 + 8007932: 6078 str r0, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8007934: f3ef 8310 mrs r3, PRIMASK + 8007938: 60fb str r3, [r7, #12] + return(result); + 800793a: 68fb ldr r3, [r7, #12] + UTIL_SEQ_ENTER_CRITICAL_SECTION( ); + 800793c: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800793e: b672 cpsid i +} + 8007940: bf00 nop + + TaskMask &= (~TaskId_bm); + 8007942: 687b ldr r3, [r7, #4] + 8007944: 43da mvns r2, r3 + 8007946: 4b08 ldr r3, [pc, #32] @ (8007968 <UTIL_SEQ_PauseTask+0x3c>) + 8007948: 681b ldr r3, [r3, #0] + 800794a: 4013 ands r3, r2 + 800794c: 4a06 ldr r2, [pc, #24] @ (8007968 <UTIL_SEQ_PauseTask+0x3c>) + 800794e: 6013 str r3, [r2, #0] + 8007950: 697b ldr r3, [r7, #20] + 8007952: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8007954: 693b ldr r3, [r7, #16] + 8007956: f383 8810 msr PRIMASK, r3 +} + 800795a: bf00 nop + + UTIL_SEQ_EXIT_CRITICAL_SECTION( ); + + return; + 800795c: bf00 nop +} + 800795e: 371c adds r7, #28 + 8007960: 46bd mov sp, r7 + 8007962: f85d 7b04 ldr.w r7, [sp], #4 + 8007966: 4770 bx lr + 8007968: 20000024 .word 0x20000024 + +0800796c <UTIL_SEQ_ResumeTask>: + UTIL_SEQ_EXIT_CRITICAL_SECTION( ); + return _status; +} + +void UTIL_SEQ_ResumeTask( UTIL_SEQ_bm_t TaskId_bm ) +{ + 800796c: b480 push {r7} + 800796e: b087 sub sp, #28 + 8007970: af00 add r7, sp, #0 + 8007972: 6078 str r0, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8007974: f3ef 8310 mrs r3, PRIMASK + 8007978: 60fb str r3, [r7, #12] + return(result); + 800797a: 68fb ldr r3, [r7, #12] + UTIL_SEQ_ENTER_CRITICAL_SECTION( ); + 800797c: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800797e: b672 cpsid i +} + 8007980: bf00 nop + + TaskMask |= TaskId_bm; + 8007982: 4b09 ldr r3, [pc, #36] @ (80079a8 <UTIL_SEQ_ResumeTask+0x3c>) + 8007984: 681a ldr r2, [r3, #0] + 8007986: 687b ldr r3, [r7, #4] + 8007988: 4313 orrs r3, r2 + 800798a: 4a07 ldr r2, [pc, #28] @ (80079a8 <UTIL_SEQ_ResumeTask+0x3c>) + 800798c: 6013 str r3, [r2, #0] + 800798e: 697b ldr r3, [r7, #20] + 8007990: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8007992: 693b ldr r3, [r7, #16] + 8007994: f383 8810 msr PRIMASK, r3 +} + 8007998: bf00 nop + + UTIL_SEQ_EXIT_CRITICAL_SECTION( ); + + return; + 800799a: bf00 nop +} + 800799c: 371c adds r7, #28 + 800799e: 46bd mov sp, r7 + 80079a0: f85d 7b04 ldr.w r7, [sp], #4 + 80079a4: 4770 bx lr + 80079a6: bf00 nop + 80079a8: 20000024 .word 0x20000024 + +080079ac <UTIL_SEQ_SetEvt>: + +void UTIL_SEQ_SetEvt( UTIL_SEQ_bm_t EvtId_bm ) +{ + 80079ac: b480 push {r7} + 80079ae: b087 sub sp, #28 + 80079b0: af00 add r7, sp, #0 + 80079b2: 6078 str r0, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 80079b4: f3ef 8310 mrs r3, PRIMASK + 80079b8: 60fb str r3, [r7, #12] + return(result); + 80079ba: 68fb ldr r3, [r7, #12] + UTIL_SEQ_ENTER_CRITICAL_SECTION( ); + 80079bc: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 80079be: b672 cpsid i +} + 80079c0: bf00 nop + + EvtSet |= EvtId_bm; + 80079c2: 4b09 ldr r3, [pc, #36] @ (80079e8 <UTIL_SEQ_SetEvt+0x3c>) + 80079c4: 681a ldr r2, [r3, #0] + 80079c6: 687b ldr r3, [r7, #4] + 80079c8: 4313 orrs r3, r2 + 80079ca: 4a07 ldr r2, [pc, #28] @ (80079e8 <UTIL_SEQ_SetEvt+0x3c>) + 80079cc: 6013 str r3, [r2, #0] + 80079ce: 697b ldr r3, [r7, #20] + 80079d0: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 80079d2: 693b ldr r3, [r7, #16] + 80079d4: f383 8810 msr PRIMASK, r3 +} + 80079d8: bf00 nop + + UTIL_SEQ_EXIT_CRITICAL_SECTION( ); + + return; + 80079da: bf00 nop +} + 80079dc: 371c adds r7, #28 + 80079de: 46bd mov sp, r7 + 80079e0: f85d 7b04 ldr.w r7, [sp], #4 + 80079e4: 4770 bx lr + 80079e6: bf00 nop + 80079e8: 2000030c .word 0x2000030c + +080079ec <UTIL_SEQ_WaitEvt>: + + return; +} + +void UTIL_SEQ_WaitEvt(UTIL_SEQ_bm_t EvtId_bm) +{ + 80079ec: b580 push {r7, lr} + 80079ee: b088 sub sp, #32 + 80079f0: af00 add r7, sp, #0 + 80079f2: 6078 str r0, [r7, #4] + UTIL_SEQ_bm_t wait_task_idx; + /* + * store in local the current_task_id_bm as the global variable CurrentTaskIdx + * may be overwritten in case there are nested call of UTIL_SEQ_Run() + */ + current_task_idx = CurrentTaskIdx; + 80079f4: 4b1f ldr r3, [pc, #124] @ (8007a74 <UTIL_SEQ_WaitEvt+0x88>) + 80079f6: 681b ldr r3, [r3, #0] + 80079f8: 61bb str r3, [r7, #24] + if(UTIL_SEQ_NOTASKRUNNING == CurrentTaskIdx) + 80079fa: 4b1e ldr r3, [pc, #120] @ (8007a74 <UTIL_SEQ_WaitEvt+0x88>) + 80079fc: 681b ldr r3, [r3, #0] + 80079fe: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8007a02: d102 bne.n 8007a0a <UTIL_SEQ_WaitEvt+0x1e> + { + wait_task_idx = 0u; + 8007a04: 2300 movs r3, #0 + 8007a06: 61fb str r3, [r7, #28] + 8007a08: e005 b.n 8007a16 <UTIL_SEQ_WaitEvt+0x2a> + } + else + { + wait_task_idx = (uint32_t)1u << CurrentTaskIdx; + 8007a0a: 4b1a ldr r3, [pc, #104] @ (8007a74 <UTIL_SEQ_WaitEvt+0x88>) + 8007a0c: 681b ldr r3, [r3, #0] + 8007a0e: 2201 movs r2, #1 + 8007a10: fa02 f303 lsl.w r3, r2, r3 + 8007a14: 61fb str r3, [r7, #28] + } + + /* backup the event id that was currently waited */ + event_waited_id_backup = EvtWaited; + 8007a16: 4b18 ldr r3, [pc, #96] @ (8007a78 <UTIL_SEQ_WaitEvt+0x8c>) + 8007a18: 681b ldr r3, [r3, #0] + 8007a1a: 617b str r3, [r7, #20] + EvtWaited = EvtId_bm; + 8007a1c: 4a16 ldr r2, [pc, #88] @ (8007a78 <UTIL_SEQ_WaitEvt+0x8c>) + 8007a1e: 687b ldr r3, [r7, #4] + 8007a20: 6013 str r3, [r2, #0] + * The system is waiting only for the last waited event. + * When it will go out, it will wait again from the previous one. + * It case it occurs while waiting for the second one, the while loop will exit immediately + */ + + while ((EvtSet & EvtId_bm) == 0U) + 8007a22: e003 b.n 8007a2c <UTIL_SEQ_WaitEvt+0x40> + { + UTIL_SEQ_EvtIdle(wait_task_idx, EvtId_bm); + 8007a24: 6879 ldr r1, [r7, #4] + 8007a26: 69f8 ldr r0, [r7, #28] + 8007a28: f000 f82a bl 8007a80 <UTIL_SEQ_EvtIdle> + while ((EvtSet & EvtId_bm) == 0U) + 8007a2c: 4b13 ldr r3, [pc, #76] @ (8007a7c <UTIL_SEQ_WaitEvt+0x90>) + 8007a2e: 681a ldr r2, [r3, #0] + 8007a30: 687b ldr r3, [r7, #4] + 8007a32: 4013 ands r3, r2 + 8007a34: 2b00 cmp r3, #0 + 8007a36: d0f5 beq.n 8007a24 <UTIL_SEQ_WaitEvt+0x38> + /* + * Restore the CurrentTaskIdx that may have been modified by call of UTIL_SEQ_Run() + * from UTIL_SEQ_EvtIdle(). This is required so that a second call of UTIL_SEQ_WaitEvt() + * in the same process pass the correct current_task_id_bm in the call of UTIL_SEQ_EvtIdle() + */ + CurrentTaskIdx = current_task_idx; + 8007a38: 4a0e ldr r2, [pc, #56] @ (8007a74 <UTIL_SEQ_WaitEvt+0x88>) + 8007a3a: 69bb ldr r3, [r7, #24] + 8007a3c: 6013 str r3, [r2, #0] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 8007a3e: f3ef 8310 mrs r3, PRIMASK + 8007a42: 60bb str r3, [r7, #8] + return(result); + 8007a44: 68bb ldr r3, [r7, #8] + + UTIL_SEQ_ENTER_CRITICAL_SECTION( ); + 8007a46: 613b str r3, [r7, #16] + __ASM volatile ("cpsid i" : : : "memory"); + 8007a48: b672 cpsid i +} + 8007a4a: bf00 nop + + EvtSet &= (~EvtId_bm); + 8007a4c: 687b ldr r3, [r7, #4] + 8007a4e: 43da mvns r2, r3 + 8007a50: 4b0a ldr r3, [pc, #40] @ (8007a7c <UTIL_SEQ_WaitEvt+0x90>) + 8007a52: 681b ldr r3, [r3, #0] + 8007a54: 4013 ands r3, r2 + 8007a56: 4a09 ldr r2, [pc, #36] @ (8007a7c <UTIL_SEQ_WaitEvt+0x90>) + 8007a58: 6013 str r3, [r2, #0] + 8007a5a: 693b ldr r3, [r7, #16] + 8007a5c: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 8007a5e: 68fb ldr r3, [r7, #12] + 8007a60: f383 8810 msr PRIMASK, r3 +} + 8007a64: bf00 nop + + UTIL_SEQ_EXIT_CRITICAL_SECTION( ); + + EvtWaited = event_waited_id_backup; + 8007a66: 4a04 ldr r2, [pc, #16] @ (8007a78 <UTIL_SEQ_WaitEvt+0x8c>) + 8007a68: 697b ldr r3, [r7, #20] + 8007a6a: 6013 str r3, [r2, #0] + return; + 8007a6c: bf00 nop +} + 8007a6e: 3720 adds r7, #32 + 8007a70: 46bd mov sp, r7 + 8007a72: bd80 pop {r7, pc} + 8007a74: 20000314 .word 0x20000314 + 8007a78: 20000310 .word 0x20000310 + 8007a7c: 2000030c .word 0x2000030c + +08007a80 <UTIL_SEQ_EvtIdle>: + UTIL_SEQ_bm_t local_evtwaited = EvtWaited; + return (EvtSet & local_evtwaited); +} + +__WEAK void UTIL_SEQ_EvtIdle( UTIL_SEQ_bm_t TaskId_bm, UTIL_SEQ_bm_t EvtWaited_bm ) +{ + 8007a80: b580 push {r7, lr} + 8007a82: b082 sub sp, #8 + 8007a84: af00 add r7, sp, #0 + 8007a86: 6078 str r0, [r7, #4] + 8007a88: 6039 str r1, [r7, #0] + (void)EvtWaited_bm; + UTIL_SEQ_Run(~TaskId_bm); + 8007a8a: 687b ldr r3, [r7, #4] + 8007a8c: 43db mvns r3, r3 + 8007a8e: 4618 mov r0, r3 + 8007a90: f7ff fd7c bl 800758c <UTIL_SEQ_Run> + return; + 8007a94: bf00 nop +} + 8007a96: 3708 adds r7, #8 + 8007a98: 46bd mov sp, r7 + 8007a9a: bd80 pop {r7, pc} + +08007a9c <UTIL_SEQ_PreIdle>: +{ + return; +} + +__WEAK void UTIL_SEQ_PreIdle( void ) +{ + 8007a9c: b480 push {r7} + 8007a9e: af00 add r7, sp, #0 + /* + * Unless specified by the application, there is nothing to be done + */ + return; + 8007aa0: bf00 nop +} + 8007aa2: 46bd mov sp, r7 + 8007aa4: f85d 7b04 ldr.w r7, [sp], #4 + 8007aa8: 4770 bx lr + +08007aaa <UTIL_SEQ_PostIdle>: + +__WEAK void UTIL_SEQ_PostIdle( void ) +{ + 8007aaa: b480 push {r7} + 8007aac: af00 add r7, sp, #0 + /* + * Unless specified by the application, there is nothing to be done + */ + return; + 8007aae: bf00 nop +} + 8007ab0: 46bd mov sp, r7 + 8007ab2: f85d 7b04 ldr.w r7, [sp], #4 + 8007ab6: 4770 bx lr + +08007ab8 <UTIL_SEQ_PreTask>: + +__WEAK void UTIL_SEQ_PreTask( uint32_t TaskId ) +{ + 8007ab8: b480 push {r7} + 8007aba: b083 sub sp, #12 + 8007abc: af00 add r7, sp, #0 + 8007abe: 6078 str r0, [r7, #4] + (void)TaskId; + return; + 8007ac0: bf00 nop +} + 8007ac2: 370c adds r7, #12 + 8007ac4: 46bd mov sp, r7 + 8007ac6: f85d 7b04 ldr.w r7, [sp], #4 + 8007aca: 4770 bx lr + +08007acc <UTIL_SEQ_PostTask>: + +__WEAK void UTIL_SEQ_PostTask( uint32_t TaskId ) +{ + 8007acc: b480 push {r7} + 8007ace: b083 sub sp, #12 + 8007ad0: af00 add r7, sp, #0 + 8007ad2: 6078 str r0, [r7, #4] + (void)TaskId; + return; + 8007ad4: bf00 nop +} + 8007ad6: 370c adds r7, #12 + 8007ad8: 46bd mov sp, r7 + 8007ada: f85d 7b04 ldr.w r7, [sp], #4 + 8007ade: 4770 bx lr + +08007ae0 <UTIL_SEQ_CatchWarning>: + +__WEAK void UTIL_SEQ_CatchWarning(UTIL_SEQ_WARNING WarningId) +{ + 8007ae0: b480 push {r7} + 8007ae2: b083 sub sp, #12 + 8007ae4: af00 add r7, sp, #0 + 8007ae6: 4603 mov r3, r0 + 8007ae8: 71fb strb r3, [r7, #7] + (void)WarningId; + return; + 8007aea: bf00 nop +} + 8007aec: 370c adds r7, #12 + 8007aee: 46bd mov sp, r7 + 8007af0: f85d 7b04 ldr.w r7, [sp], #4 + 8007af4: 4770 bx lr + +08007af6 <SEQ_BitPosition>: + * @brief return the position of the first bit set to 1 + * @param Value 32 bit value + * @retval bit position + */ +uint8_t SEQ_BitPosition(uint32_t Value) +{ + 8007af6: b480 push {r7} + 8007af8: b085 sub sp, #20 + 8007afa: af00 add r7, sp, #0 + 8007afc: 6078 str r0, [r7, #4] + 8007afe: 687b ldr r3, [r7, #4] + 8007b00: 60fb str r3, [r7, #12] + if (value == 0U) + 8007b02: 68fb ldr r3, [r7, #12] + 8007b04: 2b00 cmp r3, #0 + 8007b06: d101 bne.n 8007b0c <SEQ_BitPosition+0x16> + return 32U; + 8007b08: 2320 movs r3, #32 + 8007b0a: e003 b.n 8007b14 <SEQ_BitPosition+0x1e> + return __builtin_clz(value); + 8007b0c: 68fb ldr r3, [r7, #12] + 8007b0e: fab3 f383 clz r3, r3 + 8007b12: b2db uxtb r3, r3 + return (uint8_t)(31 -__CLZ( Value )); + 8007b14: f1c3 031f rsb r3, r3, #31 + 8007b18: b2db uxtb r3, r3 +} + 8007b1a: 4618 mov r0, r3 + 8007b1c: 3714 adds r7, #20 + 8007b1e: 46bd mov sp, r7 + 8007b20: f85d 7b04 ldr.w r7, [sp], #4 + 8007b24: 4770 bx lr + +08007b26 <memset>: + 8007b26: 4402 add r2, r0 + 8007b28: 4603 mov r3, r0 + 8007b2a: 4293 cmp r3, r2 + 8007b2c: d100 bne.n 8007b30 <memset+0xa> + 8007b2e: 4770 bx lr + 8007b30: f803 1b01 strb.w r1, [r3], #1 + 8007b34: e7f9 b.n 8007b2a <memset+0x4> + ... + +08007b38 <__libc_init_array>: + 8007b38: b570 push {r4, r5, r6, lr} + 8007b3a: 4d0d ldr r5, [pc, #52] @ (8007b70 <__libc_init_array+0x38>) + 8007b3c: 4c0d ldr r4, [pc, #52] @ (8007b74 <__libc_init_array+0x3c>) + 8007b3e: 1b64 subs r4, r4, r5 + 8007b40: 10a4 asrs r4, r4, #2 + 8007b42: 2600 movs r6, #0 + 8007b44: 42a6 cmp r6, r4 + 8007b46: d109 bne.n 8007b5c <__libc_init_array+0x24> + 8007b48: 4d0b ldr r5, [pc, #44] @ (8007b78 <__libc_init_array+0x40>) + 8007b4a: 4c0c ldr r4, [pc, #48] @ (8007b7c <__libc_init_array+0x44>) + 8007b4c: f000 f826 bl 8007b9c <_init> + 8007b50: 1b64 subs r4, r4, r5 + 8007b52: 10a4 asrs r4, r4, #2 + 8007b54: 2600 movs r6, #0 + 8007b56: 42a6 cmp r6, r4 + 8007b58: d105 bne.n 8007b66 <__libc_init_array+0x2e> + 8007b5a: bd70 pop {r4, r5, r6, pc} + 8007b5c: f855 3b04 ldr.w r3, [r5], #4 + 8007b60: 4798 blx r3 + 8007b62: 3601 adds r6, #1 + 8007b64: e7ee b.n 8007b44 <__libc_init_array+0xc> + 8007b66: f855 3b04 ldr.w r3, [r5], #4 + 8007b6a: 4798 blx r3 + 8007b6c: 3601 adds r6, #1 + 8007b6e: e7f2 b.n 8007b56 <__libc_init_array+0x1e> + 8007b70: 08007e28 .word 0x08007e28 + 8007b74: 08007e28 .word 0x08007e28 + 8007b78: 08007e28 .word 0x08007e28 + 8007b7c: 08007e2c .word 0x08007e2c + +08007b80 <memcpy>: + 8007b80: 440a add r2, r1 + 8007b82: 4291 cmp r1, r2 + 8007b84: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff + 8007b88: d100 bne.n 8007b8c <memcpy+0xc> + 8007b8a: 4770 bx lr + 8007b8c: b510 push {r4, lr} + 8007b8e: f811 4b01 ldrb.w r4, [r1], #1 + 8007b92: f803 4f01 strb.w r4, [r3, #1]! + 8007b96: 4291 cmp r1, r2 + 8007b98: d1f9 bne.n 8007b8e <memcpy+0xe> + 8007b9a: bd10 pop {r4, pc} + +08007b9c <_init>: + 8007b9c: b5f8 push {r3, r4, r5, r6, r7, lr} + 8007b9e: bf00 nop + 8007ba0: bcf8 pop {r3, r4, r5, r6, r7} + 8007ba2: bc08 pop {r3} + 8007ba4: 469e mov lr, r3 + 8007ba6: 4770 bx lr + +08007ba8 <_fini>: + 8007ba8: b5f8 push {r3, r4, r5, r6, r7, lr} + 8007baa: bf00 nop + 8007bac: bcf8 pop {r3, r4, r5, r6, r7} + 8007bae: bc08 pop {r3} + 8007bb0: 469e mov lr, r3 + 8007bb2: 4770 bx lr |