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-rw-r--r--firmware/rf test/Core/Inc/fonts.h22
-rw-r--r--firmware/rf test/Core/Inc/libs.h27
-rw-r--r--firmware/rf test/Core/Inc/lis2dw12.h43
-rw-r--r--firmware/rf test/Core/Inc/main.h69
-rw-r--r--firmware/rf test/Core/Inc/sharpmem.h41
-rw-r--r--firmware/rf test/Core/Inc/stm32wbxx_hal_conf.h352
-rw-r--r--firmware/rf test/Core/Inc/stm32wbxx_it.h70
-rw-r--r--firmware/rf test/Core/Inc/w25q_mem.hrr218
8 files changed, 842 insertions, 0 deletions
diff --git a/firmware/rf test/Core/Inc/fonts.h b/firmware/rf test/Core/Inc/fonts.h
new file mode 100644
index 0000000..3a4cbc6
--- /dev/null
+++ b/firmware/rf test/Core/Inc/fonts.h
@@ -0,0 +1,22 @@
+#include <stdint.h>
+#include <stdlib.h>
+
+#ifndef _FONTS_H
+#define _FONTS_H
+
+#define NUMBER_OF_FONTS 1
+
+typedef struct {
+ uint8_t char_w;
+ uint8_t char_h;
+ uint8_t bytes_per_row;
+ uint8_t bytes_per_char;
+ uint8_t *font_bytes;
+ uint8_t *lookup;
+} bitmap_font_t;
+
+extern bitmap_font_t** fonts;
+
+void set_up_fonts();
+
+#endif
diff --git a/firmware/rf test/Core/Inc/libs.h b/firmware/rf test/Core/Inc/libs.h
new file mode 100644
index 0000000..d11de62
--- /dev/null
+++ b/firmware/rf test/Core/Inc/libs.h
@@ -0,0 +1,27 @@
+/**
+ *******************************************
+ * @file libs.h
+ * @author Dmitriy Semenov / Crazy_Geeks
+ * @brief Internal header for adding sys libs and defines
+ *******************************************
+*/
+
+#ifndef LIBS_H_
+#define LIBS_H_
+
+#include "main.h" ///< Main project file
+#include <stdint.h> ///< Std types
+#include <stdbool.h> ///< _Bool to bool
+#include <string.h> ///< Lib for sprintf, strlen, etc
+
+typedef uint8_t u8_t; ///< 8-bit unsigned
+typedef int8_t i8_t; ///< 8-bit signed
+typedef uint16_t u16_t; ///< 16-bit unsigned
+typedef int16_t i16_t; ///< 16-bit signed
+typedef uint32_t u32_t; ///< 32-bit unsigned
+typedef int32_t i32_t; ///< 32-bit signed
+typedef float fl_t; ///< float type
+
+#define delay(x) HAL_Delay(x) ///< arduino-supportable delay or RTOS support ability
+
+#endif /* LIBS_H_ */
diff --git a/firmware/rf test/Core/Inc/lis2dw12.h b/firmware/rf test/Core/Inc/lis2dw12.h
new file mode 100644
index 0000000..6430da6
--- /dev/null
+++ b/firmware/rf test/Core/Inc/lis2dw12.h
@@ -0,0 +1,43 @@
+/*
+ * lis2dw12.h
+ *
+ * Created on: Dec 30, 2025
+ * Author: Anson Bridges
+ */
+
+#ifndef INC_LIS2DW12_H_
+#define INC_LIS2DW12_H_
+
+#include <stdint.h>
+
+const uint8_t LIS2DW_ADDR = 0x32; //0x0011001_
+
+const uint8_t TAP_THS_Z = 0x32;
+const uint8_t TAP_THS_Y = 0x31;
+const uint8_t TAP_THS_X = 0x30;
+const uint8_t TAP_SRC = 0x39;
+const uint8_t OUT_X_L = 0x28;
+const uint8_t CTRL1 = 0x20;
+const uint8_t CTRL3 = 0x22;
+const uint8_t CTRL6 = 0x25;
+const uint8_t CTRL7 = 0x3F;
+const uint8_t INT_DUR = 0x33;
+
+const uint8_t INIT_CTRL1 = 0b01110111; // power mode
+const uint8_t INIT_CTRL3 = 0b00010000;
+const uint8_t INIT_CTRL6 = 0xC8;
+const uint8_t INIT_CTRL7 = 0b00100000; // enable interrupts
+const uint8_t INIT_INT_DUR = 0b00001100;
+const uint8_t INIT_TAP_Z = 0b11101100; //first 3 bits enable tap x/y/z, last 5 z threshold
+const uint8_t INIT_TAP_Y = 0b11101100; //first 3 bits tap priority, last 5 y threshold
+const uint8_t INIT_TAP_X = 0b00001100; // first 3 4D/6D, last 5 x threshold
+
+const uint8_t TAP_IA = 0b01000000;
+const uint8_t TAP_SINGLE = 0b00100000;
+const uint8_t TAP_DOUBLE = 0b00010000;
+const uint8_t TAP_SIGN = 0b00001000;
+const uint8_t TAP_X = 0b00000100;
+const uint8_t TAP_Y = 0b00000010;
+const uint8_t TAP_Z = 0b00000001;
+
+#endif /* INC_LIS2DW12_H_ */
diff --git a/firmware/rf test/Core/Inc/main.h b/firmware/rf test/Core/Inc/main.h
new file mode 100644
index 0000000..c4ad39b
--- /dev/null
+++ b/firmware/rf test/Core/Inc/main.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.h
+ * @brief : Header for main.c file.
+ * This file contains the common defines of the application.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2025 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+
+/* USER CODE BEGIN Private defines */
+void SharpMem_Init();
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
diff --git a/firmware/rf test/Core/Inc/sharpmem.h b/firmware/rf test/Core/Inc/sharpmem.h
new file mode 100644
index 0000000..79f91aa
--- /dev/null
+++ b/firmware/rf test/Core/Inc/sharpmem.h
@@ -0,0 +1,41 @@
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include "stm32wbxx_hal.h"
+
+#ifndef _STM32_SHARPMEM
+#define _STM32_SHARPMEM
+
+#define SHARPMEM_BIT_WRITECMD (0x01) // 0x80 in LSB format
+#define SHARPMEM_BIT_VCOM (0x02) // 0x40 in LSB format
+#define SHARPMEM_BIT_CLEAR (0x04) // 0x20 in LSB format
+
+typedef struct
+{
+ uint16_t width;
+ uint16_t height;
+ uint16_t cs_pin;
+ GPIO_TypeDef *cs_pin_bank;
+ uint16_t lcdmode_pin;
+ GPIO_TypeDef *lcdmode_pin_bank;
+ SPI_HandleTypeDef *spidev;
+
+ uint8_t *_buffer;
+ uint8_t _sharpmem_vcom;
+} SharpMemDisplay_t;
+
+void SHARPMEM_draw_pixel(SharpMemDisplay_t *display, uint16_t x, uint16_t y, bool black);
+void SHARPMEM_draw_line(SharpMemDisplay_t *display, uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, bool black, uint8_t thickness);
+void SHARPMEM_draw_circle(SharpMemDisplay_t *display, uint16_t x, uint16_t y, uint8_t r, bool filled);
+void SHARPMEM_write(SharpMemDisplay_t *display, char *text, uint8_t font_index, uint16_t x, uint16_t y, bool inverse, bool force_bg);
+void SHARPMEM_draw_rect(SharpMemDisplay_t *display, uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, bool filled);
+uint8_t SHARPMEM_get_pixel(SharpMemDisplay_t *display, uint16_t x, uint16_t y);
+void SHARPMEM_clear_display(SharpMemDisplay_t *display);
+void SHARPMEM_refresh_display(SharpMemDisplay_t *display);
+void SHARPMEM_clear_display_buffer(SharpMemDisplay_t *display);
+uint8_t *SHARPMEM_get_buffer(SharpMemDisplay_t *display);
+
+void SHARPMEM_TOGGLEVCOM(SharpMemDisplay_t *display);
+
+
+#endif
diff --git a/firmware/rf test/Core/Inc/stm32wbxx_hal_conf.h b/firmware/rf test/Core/Inc/stm32wbxx_hal_conf.h
new file mode 100644
index 0000000..a3dcf46
--- /dev/null
+++ b/firmware/rf test/Core/Inc/stm32wbxx_hal_conf.h
@@ -0,0 +1,352 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32wbxx_hal_conf.h
+ * @author MCD Application Team
+ * @brief HAL configuration file.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+/*#define HAL_ADC_MODULE_ENABLED */
+/*#define HAL_CRYP_MODULE_ENABLED */
+/*#define HAL_COMP_MODULE_ENABLED */
+/*#define HAL_CRC_MODULE_ENABLED */
+#define HAL_HSEM_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_IPCC_MODULE_ENABLED
+/*#define HAL_IRDA_MODULE_ENABLED */
+/*#define HAL_IWDG_MODULE_ENABLED */
+/*#define HAL_LCD_MODULE_ENABLED */
+/*#define HAL_LPTIM_MODULE_ENABLED */
+/*#define HAL_PCD_MODULE_ENABLED */
+/*#define HAL_PKA_MODULE_ENABLED */
+/*#define HAL_QSPI_MODULE_ENABLED */
+/*#define HAL_RNG_MODULE_ENABLED */
+#define HAL_RTC_MODULE_ENABLED
+/*#define HAL_SAI_MODULE_ENABLED */
+/*#define HAL_SMBUS_MODULE_ENABLED */
+/*#define HAL_SMARTCARD_MODULE_ENABLED */
+#define HAL_SPI_MODULE_ENABLED
+/*#define HAL_TIM_MODULE_ENABLED */
+/*#define HAL_TSC_MODULE_ENABLED */
+/*#define HAL_UART_MODULE_ENABLED */
+/*#define HAL_USART_MODULE_ENABLED */
+/*#define HAL_WWDG_MODULE_ENABLED */
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS 0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS 0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS 0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS 0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS 0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS 0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS 0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS 0u
+#define USE_HAL_UART_REGISTER_CALLBACKS 0u
+#define USE_HAL_USART_REGISTER_CALLBACKS 0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE 32000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal Multiple Speed oscillator (MSI) default value.
+ * This value is the default MSI range value after Reset.
+ */
+#if !defined (MSI_VALUE)
+ #define MSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI1) value.
+ */
+#if !defined (LSI1_VALUE)
+ #define LSI1_VALUE ((uint32_t)32000) /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature.*/
+/**
+ * @brief Internal Low Speed oscillator (LSI2) value.
+ */
+#if !defined (LSI2_VALUE)
+ #define LSI2_VALUE ((uint32_t)32000) /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature.*/
+
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ * This value is used by the UART, RTC HAL module to compute the system frequency
+ */
+#if !defined (LSE_VALUE)
+#define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+ * @brief Internal Multiple Speed oscillator (HSI48) default value.
+ * This value is the default HSI48 range value after Reset.
+ */
+#if !defined (HSI48_VALUE)
+ #define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief External clock source for SAI1 peripheral
+ * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
+ * frequency.
+ */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+ #define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)2097000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+
+#define VDD_VALUE 3300U /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority */
+#define USE_RTOS 0U
+#define PREFETCH_ENABLE 1U
+#define INSTRUCTION_CACHE_ENABLE 1U
+#define DATA_CACHE_ENABLE 1U
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC 0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+ #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+ #include "stm32wbxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+ #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+ #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+ #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
diff --git a/firmware/rf test/Core/Inc/stm32wbxx_it.h b/firmware/rf test/Core/Inc/stm32wbxx_it.h
new file mode 100644
index 0000000..8a8788f
--- /dev/null
+++ b/firmware/rf test/Core/Inc/stm32wbxx_it.h
@@ -0,0 +1,70 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32wbxx_it.h
+ * @brief This file contains the headers of the interrupt handlers.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2025 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_IT_H
+#define __STM32WBxx_IT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void RTC_WKUP_IRQHandler(void);
+void IPCC_C1_RX_IRQHandler(void);
+void IPCC_C1_TX_IRQHandler(void);
+void HSEM_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_IT_H */
diff --git a/firmware/rf test/Core/Inc/w25q_mem.hrr b/firmware/rf test/Core/Inc/w25q_mem.hrr
new file mode 100644
index 0000000..fd80751
--- /dev/null
+++ b/firmware/rf test/Core/Inc/w25q_mem.hrr
@@ -0,0 +1,218 @@
+/**
+ *******************************************
+ * @file w25q_mem.h
+ * @author Dmitriy Semenov / Crazy_Geeks
+ * @version 0.1b
+ * @date 12-August-2021
+ * @brief Header for W25Qxxx lib
+ * @note https://github.com/Crazy-Geeks/STM32-W25Q-QSPI
+ *******************************************
+ *
+ * @note https://ru.mouser.com/datasheet/2/949/w25q256jv_spi_revg_08032017-1489574.pdf
+ * @note https://www.st.com/resource/en/application_note/DM00227538-.pdf
+*/
+
+#ifndef W25Q_QSPI_W25Q_MEM_H_
+#define W25Q_QSPI_W25Q_MEM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "libs.h"
+
+/**
+ * @addtogroup W25Q_Driver
+ * @brief W25Q QSPI Driver
+ * @{
+ */
+
+/**
+ * @defgroup W25Q_Param W25Q Chip's Parameters
+ * @brief User's chip parameters
+ * @{
+ */
+// YOUR CHIP'S SETTINGS
+/// Mem size in MB-bit
+#define MEM_FLASH_SIZE 128U // 128 MB-bit
+/// Mem big block size in KB
+#define MEM_BLOCK_SIZE 64U // 64 KB: 256 pages
+/// Mem small block size in KB
+#define MEM_SBLOCK_SIZE 32U // 32 KB: 128 pages
+/// Mem sector size in KB
+#define MEM_SECTOR_SIZE 4U // 4 KB : 16 pages
+/// Mem page size in bytes
+#define MEM_PAGE_SIZE 256U // 256 byte : 1 page
+/// Blocks count
+#define BLOCK_COUNT (MEM_FLASH_SIZE * 2) // 512 blocks
+/// Sector count
+#define SECTOR_COUNT (BLOCK_COUNT * 16) // 8192 sectors
+/// Pages count
+#define PAGE_COUNT (SECTOR_COUNT * 16) // 131'072 pages
+
+/**@}*/
+
+/**
+ * @enum W25Q_STATE
+ * @brief W25Q Return State
+ * Lib's functions status returns
+ * @{
+ */
+typedef enum{
+ W25Q_OK = 0, ///< Chip OK - Execution fine
+ W25Q_BUSY = 1, ///< Chip busy
+ W25Q_PARAM_ERR = 2, ///< Function parameters error
+ W25Q_CHIP_ERR = 3, ///< Chip error
+ W25Q_SPI_ERR = 4, ///< SPI Bus err
+ W25Q_CHIP_IGNORE = 5, ///< Chip ignore state
+}W25Q_STATE;
+/** @} */
+
+/**
+ * @struct W25Q_STATUS_REG
+ * @brief W25Q Status Registers
+ * @TODO: Mem protected recognition
+ *
+ * Structure to check chip's status registers
+ * @{
+ */
+typedef struct{
+ bool BUSY; ///< Erase/Write in progress
+ bool WEL; ///< Write enable latch (1 - write allowed)
+ bool QE; ///< Quad SPI mode
+ bool SUS; ///< Suspend Status
+ bool ADS; ///< Current addr mode (0-3 byte / 1-4 byte)
+ bool ADP; ///< Power-up addr mode
+ bool SLEEP; ///< Sleep Status
+}W25Q_STATUS_REG;
+/** @} */
+
+
+W25Q_STATE W25Q_Init(void); ///< Initalize function
+
+W25Q_STATE W25Q_EnableVolatileSR(void); ///< Make Status Register Volatile
+W25Q_STATE W25Q_ReadStatusReg(u8_t *reg_data, u8_t reg_num); ///< Read status register to variable
+W25Q_STATE W25Q_WriteStatusReg(u8_t reg_data, u8_t reg_num);///< Write status register from variable
+W25Q_STATE W25Q_ReadStatusStruct(W25Q_STATUS_REG *status); ///< Read all status registers to struct
+W25Q_STATE W25Q_IsBusy(void); ///< Check chip's busy status
+
+W25Q_STATE W25Q_ReadSByte(i8_t *buf, u8_t pageShift, u32_t pageNum); ///< Read signed 8-bit variable
+W25Q_STATE W25Q_ReadByte(u8_t *buf, u8_t pageShift, u32_t pageNum); ///< Read 8-bit variable
+W25Q_STATE W25Q_ReadSWord(i16_t *buf, u8_t pageShift, u32_t pageNum); ///< Read signed 16-bit variable
+W25Q_STATE W25Q_ReadWord(u16_t *buf, u8_t pageShift, u32_t pageNum); ///< Read 16-bit variable
+W25Q_STATE W25Q_ReadSLong(i32_t *buf, u8_t pageShift, u32_t pageNum); ///< Read signed 32-bit variable
+W25Q_STATE W25Q_ReadLong(u32_t *buf, u8_t pageShift, u32_t pageNum); ///< Read 32-bit variable
+W25Q_STATE W25Q_ReadData(u8_t *buf, u16_t len, u8_t pageShift, u32_t pageNum); ///< Read any 8-bit data
+W25Q_STATE W25Q_ReadRaw(u8_t *buf, u16_t data_len, u32_t rawAddr); ///< Read data from raw addr
+W25Q_STATE W25Q_SingleRead(u8_t *buf, u32_t len, u32_t Addr); ///< Read data from raw addr by single line
+
+W25Q_STATE W25Q_EraseSector(u32_t SectAddr); ///< Erase 4KB Sector
+W25Q_STATE W25Q_EraseBlock(u32_t BlockAddr, u8_t size); ///< Erase 32KB/64KB Sector
+W25Q_STATE W25Q_EraseChip(void); ///< Erase all chip
+
+W25Q_STATE W25Q_ProgramSByte(i8_t buf, u8_t pageShift, u32_t pageNum); ///< Program signed 8-bit variable
+W25Q_STATE W25Q_ProgramByte(u8_t buf, u8_t pageShift, u32_t pageNum); ///< Program 8-bit variable
+W25Q_STATE W25Q_ProgramSWord(i16_t buf, u8_t pageShift, u32_t pageNum); ///< Program signed 16-bit variable
+W25Q_STATE W25Q_ProgramWord(u16_t buf, u8_t pageShift, u32_t pageNum); ///< Program 16-bit variable
+W25Q_STATE W25Q_ProgramSLong(i32_t buf, u8_t pageShift, u32_t pageNum); ///< Program signed 32-bit variable
+W25Q_STATE W25Q_ProgramLong(u32_t buf, u8_t pageShift, u32_t pageNum); ///< Program 32-bit variable
+W25Q_STATE W25Q_ProgramData(u8_t *buf, u16_t len, u8_t pageShift, u32_t pageNum); ///< Program any 8-bit data
+W25Q_STATE W25Q_ProgramRaw(u8_t *buf, u16_t data_len, u32_t rawAddr); ///< Program data to raw addr
+
+W25Q_STATE W25Q_SetBurstWrap(u8_t WrapSize); ///< Set Burst with Wrap
+
+W25Q_STATE W25Q_ProgSuspend(void); ///< Pause Programm/Erase operation
+W25Q_STATE W25Q_ProgResume(void); ///< Resume Programm/Erase operation
+
+W25Q_STATE W25Q_Sleep(void); ///< Set low current consumption
+W25Q_STATE W25Q_WakeUP(void); ///< Wake the chip up from sleep mode
+
+W25Q_STATE W25Q_ReadID(u8_t *buf); ///< Read chip ID
+W25Q_STATE W25Q_ReadFullID(u8_t *buf); ///< Read full chip ID (Manufacturer ID + Device ID)
+W25Q_STATE W25Q_ReadUID(u8_t *buf); ///< Read unique chip ID
+W25Q_STATE W25Q_ReadJEDECID(u8_t *buf); ///< Read ID by JEDEC Standards
+W25Q_STATE W25Q_ReadSFDPRegister(u8_t *buf); ///< Read device descriptor (SFDP Standard)
+
+W25Q_STATE W25Q_EraseSecurityRegisters(u8_t numReg); ///< Erase security register
+W25Q_STATE W25Q_ProgSecurityRegisters(u8_t *buf, u8_t numReg, u8_t byteAddr); ///< Program security register
+W25Q_STATE W25Q_ReadSecurityRegisters(u8_t *buf, u8_t numReg, u8_t byteAddr); ///< Read security register
+
+W25Q_STATE W25Q_BlockReadOnly(u32_t Addr, bool enable); ///< Individual block/sector read-only lock
+W25Q_STATE W25Q_BlockReadOnlyCheck(bool *state, u32_t Addr); ///< Check block's/sector's read-only lock status
+W25Q_STATE W25Q_GlobalReadOnly(bool enable); ///< Set read-only param to all chip
+
+W25Q_STATE W25Q_SwReset(bool force); ///< Software reset
+
+
+/**
+ * @defgroup W25Q_Commands W25Q Chip's Commands
+ * @brief W25Q Chip commands from datasheet
+ * @{
+ */
+#define W25Q_WRITE_ENABLE 0x06U ///< sets WEL bit, must be set before any write/program/erase
+#define W25Q_WRITE_DISABLE 0x04U ///< resets WEL bit (state after power-up)
+#define W25Q_ENABLE_VOLATILE_SR 0x50U ///< check 7.1 in datasheet
+#define W25Q_READ_SR1 0x05U ///< read status-register 1
+#define W25Q_READ_SR2 0x35U ///< read status-register 2
+#define W25Q_READ_SR3 0x15U ///< read ststus-register 3
+#define W25Q_WRITE_SR1 0x01U ///< write status-register 1 (8.2.5)
+#define W25Q_WRITE_SR2 0x31U ///< write status-register 2 (8.2.5)
+#define W25Q_WRITE_SR3 0x11U ///< write status-register 3 (8.2.5)
+#define W25Q_READ_EXT_ADDR_REG 0xC8U ///< read extended addr reg (only in 3-byte mode)
+#define W25Q_WRITE_EXT_ADDR_REG 0xC8U ///< write extended addr reg (only in 3-byte mode)
+#define W25Q_ENABLE_4B_MODE 0xB7U ///< enable 4-byte mode (128+ MB address)
+#define W25Q_DISABLE_4B_MODE 0xE9U ///< disable 4-byte mode (<=128MB)
+#define W25Q_READ_DATA 0x03U ///< read data by standard SPI
+#define W25Q_READ_DATA_4B 0x13U ///< read data by standard SPI in 4-byte mode
+#define W25Q_FAST_READ 0x0BU ///< highest FR speed (8.2.12)
+#define W25Q_FAST_READ_4B 0x0CU ///< fast read in 4-byte mode
+#define W25Q_FAST_READ_DUAL_OUT 0x3BU ///< fast read in dual-SPI OUTPUT (8.2.14)
+#define W25Q_FAST_READ_DUAL_OUT_4B 0x3CU ///< fast read in dual-SPI OUTPUT in 4-byte mode
+#define W25Q_FAST_READ_QUAD_OUT 0x6BU ///< fast read in quad-SPI OUTPUT (8.2.16)
+#define W25Q_FAST_READ_QUAD_OUT_4B 0x6CU ///< fast read in quad-SPI OUTPUT in 4-byte mode
+#define W25Q_FAST_READ_DUAL_IO 0xBBU ///< fast read in dual-SPI I/O (address transmits by both lines)
+#define W25Q_FAST_READ_DUAL_IO_4B 0xBCU ///< fast read in dual-SPI I/O in 4-byte mode
+#define W25Q_FAST_READ_QUAD_IO 0xEBU ///< fast read in quad-SPI I/O (address transmits by quad lines)
+#define W25Q_FAST_READ_QUAD_IO_4B 0xECU ///< fast read in quad-SPI I/O in 4-byte mode
+#define W25Q_SET_BURST_WRAP 0x77U ///< use with quad-I/O (8.2.22)
+#define W25Q_PAGE_PROGRAM 0x02U ///< program page (256bytes) by single SPI line
+#define W25Q_PAGE_PROGRAM_4B 0x12U ///< program page by single SPI in 4-byte mode
+#define W25Q_PAGE_PROGRAM_QUAD_INP 0x32U ///< program page (256bytes) by quad SPI lines
+#define W25Q_PAGE_PROGRAM_QUAD_INP_4B 0x34U ///< program page by quad SPI in 4-byte mode
+#define W25Q_SECTOR_ERASE 0x20U ///< sets all 4Kbyte sector with 0xFF (erases it)
+#define W25Q_SECTOR_ERASE_4B 0x21U ///< sets all 4Kbyte sector with 0xFF in 4-byte mode
+#define W25Q_32KB_BLOCK_ERASE 0x52U ///< sets all 32Kbyte block with 0xFF
+#define W25Q_64KB_BLOCK_ERASE 0xD8U ///< sets all 64Kbyte block with 0xFF
+#define W25Q_64KB_BLOCK_ERASE_4B 0xDCU ///< sets all 64Kbyte sector with 0xFF in 4-byte mode
+#define W25Q_CHIP_ERASE 0xC7U ///< fill all the chip with 0xFF
+//#define W25Q_CHIP_ERASE 0x60U ///< another way to erase chip
+#define W25Q_ERASEPROG_SUSPEND 0x75U ///< suspend erase/program operation (can be applied only when SUS=0, BYSY=1)
+#define W25Q_ERASEPROG_RESUME 0x7AU ///< resume erase/program operation (if SUS=1, BUSY=0)
+#define W25Q_POWERDOWN 0xB9U ///< powers down the chip (power-up by reading ID)
+#define W25Q_POWERUP 0xABU ///< release power-down
+#define W25Q_DEVID 0xABU ///< read Device ID (same as powerup)
+#define W25Q_FULLID 0x90U ///< read Manufacturer ID & Device ID
+#define W25Q_FULLID_DUAL_IO 0x92U ///< read Manufacturer ID & Device ID by dual I/O
+#define W25Q_FULLID_QUAD_IO 0x94U ///< read Manufacturer ID & Device ID by quad I/O
+#define W25Q_READ_UID 0x4BU ///< read unique chip 64-bit ID
+#define W25Q_READ_JEDEC_ID 0x9FU ///< read JEDEC-standard ID
+#define W25Q_READ_SFDP 0x5AU ///< read SFDP register parameters
+#define W25Q_ERASE_SECURITY_REG 0x44U ///< erase security registers
+#define W25Q_PROG_SECURITY_REG 0x42U ///< program security registers
+#define W25Q_READ_SECURITY_REG 0x48U ///< read security registers
+#define W25Q_IND_BLOCK_LOCK 0x36U ///< make block/sector read-only
+#define W25Q_IND_BLOCK_UNLOCK 0x39U ///< disable block/sector protection
+#define W25Q_READ_BLOCK_LOCK 0x3DU ///< check block/sector protection
+#define W25Q_GLOBAL_LOCK 0x7EU ///< global read-only protection enable
+#define W25Q_GLOBAL_UNLOCK 0x98U ///< global read-only protection disable
+#define W25Q_ENABLE_RST 0x66U ///< enable software-reset ability
+#define W25Q_RESET 0x99U ///< make software reset
+/// @}
+
+/// @}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* W25Q_QSPI_W25Q_MEM_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-18 04:28:09 +0000