diff options
Diffstat (limited to 'firmware/rf test/Debug/rf test.list')
| -rw-r--r-- | firmware/rf test/Debug/rf test.list | 13792 |
1 files changed, 13792 insertions, 0 deletions
diff --git a/firmware/rf test/Debug/rf test.list b/firmware/rf test/Debug/rf test.list new file mode 100644 index 0000000..87d7e00 --- /dev/null +++ b/firmware/rf test/Debug/rf test.list @@ -0,0 +1,13792 @@ + +rf test.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 0000013c 08000000 08000000 00001000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 000050c0 08000140 08000140 00001140 2**4 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 000000ec 08005200 08005200 00006200 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM 00000008 080052ec 080052ec 000062ec 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .init_array 00000004 080052f4 080052f4 000062f4 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .fini_array 00000004 080052f8 080052f8 000062f8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 6 .data 0000071c 20000008 080052fc 00007008 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 .bss 000002cc 20000724 08005a18 00007724 2**2 + ALLOC + 8 ._user_heap_stack 00000600 200009f0 08005a18 000079f0 2**0 + ALLOC + 9 .ARM.attributes 00000030 00000000 00000000 00007724 2**0 + CONTENTS, READONLY + 10 .debug_info 00013376 00000000 00000000 00007754 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 11 .debug_abbrev 00003070 00000000 00000000 0001aaca 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 12 .debug_aranges 00001808 00000000 00000000 0001db40 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_rnglists 0000123c 00000000 00000000 0001f348 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_macro 00023286 00000000 00000000 00020584 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_line 0001545c 00000000 00000000 0004380a 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_str 000dc95d 00000000 00000000 00058c66 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .comment 00000043 00000000 00000000 001355c3 2**0 + CONTENTS, READONLY + 18 .debug_frame 000069a4 00000000 00000000 00135608 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_line_str 0000005f 00000000 00000000 0013bfac 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +08000140 <__do_global_dtors_aux>: + 8000140: b510 push {r4, lr} + 8000142: 4c05 ldr r4, [pc, #20] @ (8000158 <__do_global_dtors_aux+0x18>) + 8000144: 7823 ldrb r3, [r4, #0] + 8000146: b933 cbnz r3, 8000156 <__do_global_dtors_aux+0x16> + 8000148: 4b04 ldr r3, [pc, #16] @ (800015c <__do_global_dtors_aux+0x1c>) + 800014a: b113 cbz r3, 8000152 <__do_global_dtors_aux+0x12> + 800014c: 4804 ldr r0, [pc, #16] @ (8000160 <__do_global_dtors_aux+0x20>) + 800014e: f3af 8000 nop.w + 8000152: 2301 movs r3, #1 + 8000154: 7023 strb r3, [r4, #0] + 8000156: bd10 pop {r4, pc} + 8000158: 20000724 .word 0x20000724 + 800015c: 00000000 .word 0x00000000 + 8000160: 080051e8 .word 0x080051e8 + +08000164 <frame_dummy>: + 8000164: b508 push {r3, lr} + 8000166: 4b03 ldr r3, [pc, #12] @ (8000174 <frame_dummy+0x10>) + 8000168: b11b cbz r3, 8000172 <frame_dummy+0xe> + 800016a: 4903 ldr r1, [pc, #12] @ (8000178 <frame_dummy+0x14>) + 800016c: 4803 ldr r0, [pc, #12] @ (800017c <frame_dummy+0x18>) + 800016e: f3af 8000 nop.w + 8000172: bd08 pop {r3, pc} + 8000174: 00000000 .word 0x00000000 + 8000178: 20000728 .word 0x20000728 + 800017c: 080051e8 .word 0x080051e8 + +08000180 <strlen>: + 8000180: 4603 mov r3, r0 + 8000182: f813 2b01 ldrb.w r2, [r3], #1 + 8000186: 2a00 cmp r2, #0 + 8000188: d1fb bne.n 8000182 <strlen+0x2> + 800018a: 1a18 subs r0, r3, r0 + 800018c: 3801 subs r0, #1 + 800018e: 4770 bx lr + +08000190 <memchr>: + 8000190: f001 01ff and.w r1, r1, #255 @ 0xff + 8000194: 2a10 cmp r2, #16 + 8000196: db2b blt.n 80001f0 <memchr+0x60> + 8000198: f010 0f07 tst.w r0, #7 + 800019c: d008 beq.n 80001b0 <memchr+0x20> + 800019e: f810 3b01 ldrb.w r3, [r0], #1 + 80001a2: 3a01 subs r2, #1 + 80001a4: 428b cmp r3, r1 + 80001a6: d02d beq.n 8000204 <memchr+0x74> + 80001a8: f010 0f07 tst.w r0, #7 + 80001ac: b342 cbz r2, 8000200 <memchr+0x70> + 80001ae: d1f6 bne.n 800019e <memchr+0xe> + 80001b0: b4f0 push {r4, r5, r6, r7} + 80001b2: ea41 2101 orr.w r1, r1, r1, lsl #8 + 80001b6: ea41 4101 orr.w r1, r1, r1, lsl #16 + 80001ba: f022 0407 bic.w r4, r2, #7 + 80001be: f07f 0700 mvns.w r7, #0 + 80001c2: 2300 movs r3, #0 + 80001c4: e8f0 5602 ldrd r5, r6, [r0], #8 + 80001c8: 3c08 subs r4, #8 + 80001ca: ea85 0501 eor.w r5, r5, r1 + 80001ce: ea86 0601 eor.w r6, r6, r1 + 80001d2: fa85 f547 uadd8 r5, r5, r7 + 80001d6: faa3 f587 sel r5, r3, r7 + 80001da: fa86 f647 uadd8 r6, r6, r7 + 80001de: faa5 f687 sel r6, r5, r7 + 80001e2: b98e cbnz r6, 8000208 <memchr+0x78> + 80001e4: d1ee bne.n 80001c4 <memchr+0x34> + 80001e6: bcf0 pop {r4, r5, r6, r7} + 80001e8: f001 01ff and.w r1, r1, #255 @ 0xff + 80001ec: f002 0207 and.w r2, r2, #7 + 80001f0: b132 cbz r2, 8000200 <memchr+0x70> + 80001f2: f810 3b01 ldrb.w r3, [r0], #1 + 80001f6: 3a01 subs r2, #1 + 80001f8: ea83 0301 eor.w r3, r3, r1 + 80001fc: b113 cbz r3, 8000204 <memchr+0x74> + 80001fe: d1f8 bne.n 80001f2 <memchr+0x62> + 8000200: 2000 movs r0, #0 + 8000202: 4770 bx lr + 8000204: 3801 subs r0, #1 + 8000206: 4770 bx lr + 8000208: 2d00 cmp r5, #0 + 800020a: bf06 itte eq + 800020c: 4635 moveq r5, r6 + 800020e: 3803 subeq r0, #3 + 8000210: 3807 subne r0, #7 + 8000212: f015 0f01 tst.w r5, #1 + 8000216: d107 bne.n 8000228 <memchr+0x98> + 8000218: 3001 adds r0, #1 + 800021a: f415 7f80 tst.w r5, #256 @ 0x100 + 800021e: bf02 ittt eq + 8000220: 3001 addeq r0, #1 + 8000222: f415 3fc0 tsteq.w r5, #98304 @ 0x18000 + 8000226: 3001 addeq r0, #1 + 8000228: bcf0 pop {r4, r5, r6, r7} + 800022a: 3801 subs r0, #1 + 800022c: 4770 bx lr + 800022e: bf00 nop + +08000230 <set_up_fonts>: + + +bitmap_font_t** fonts; +bitmap_font_t jetbrains_mono_quarter; + +void set_up_fonts() { + 8000230: b580 push {r7, lr} + 8000232: af00 add r7, sp, #0 + fonts = malloc(sizeof(bitmap_font_t *)*NUMBER_OF_FONTS); + 8000234: 2004 movs r0, #4 + 8000236: f004 fb2f bl 8004898 <malloc> + 800023a: 4603 mov r3, r0 + 800023c: 461a mov r2, r3 + 800023e: 4b1b ldr r3, [pc, #108] @ (80002ac <set_up_fonts+0x7c>) + 8000240: 601a str r2, [r3, #0] + fonts[0] = &jetbrains_mono_quarter; + 8000242: 4b1a ldr r3, [pc, #104] @ (80002ac <set_up_fonts+0x7c>) + 8000244: 681b ldr r3, [r3, #0] + 8000246: 4a1a ldr r2, [pc, #104] @ (80002b0 <set_up_fonts+0x80>) + 8000248: 601a str r2, [r3, #0] + + jetbrains_mono_quarter.char_w = 8; + 800024a: 4b19 ldr r3, [pc, #100] @ (80002b0 <set_up_fonts+0x80>) + 800024c: 2208 movs r2, #8 + 800024e: 701a strb r2, [r3, #0] + jetbrains_mono_quarter.char_h = 17; + 8000250: 4b17 ldr r3, [pc, #92] @ (80002b0 <set_up_fonts+0x80>) + 8000252: 2211 movs r2, #17 + 8000254: 705a strb r2, [r3, #1] + jetbrains_mono_quarter.bytes_per_row = 1; + 8000256: 4b16 ldr r3, [pc, #88] @ (80002b0 <set_up_fonts+0x80>) + 8000258: 2201 movs r2, #1 + 800025a: 709a strb r2, [r3, #2] + jetbrains_mono_quarter.bytes_per_char = 17; + 800025c: 4b14 ldr r3, [pc, #80] @ (80002b0 <set_up_fonts+0x80>) + 800025e: 2211 movs r2, #17 + 8000260: 70da strb r2, [r3, #3] + jetbrains_mono_quarter.font_bytes = malloc(sizeof(uint8_t)*1598); + 8000262: f240 603e movw r0, #1598 @ 0x63e + 8000266: f004 fb17 bl 8004898 <malloc> + 800026a: 4603 mov r3, r0 + 800026c: 461a mov r2, r3 + 800026e: 4b10 ldr r3, [pc, #64] @ (80002b0 <set_up_fonts+0x80>) + 8000270: 605a str r2, [r3, #4] + jetbrains_mono_quarter.lookup = malloc(sizeof(uint8_t)*128); + 8000272: 2080 movs r0, #128 @ 0x80 + 8000274: f004 fb10 bl 8004898 <malloc> + 8000278: 4603 mov r3, r0 + 800027a: 461a mov r2, r3 + 800027c: 4b0c ldr r3, [pc, #48] @ (80002b0 <set_up_fonts+0x80>) + 800027e: 609a str r2, [r3, #8] + memcpy(jetbrains_mono_quarter.font_bytes, jetbrains_mono_quarter_fb, 1598); + 8000280: 4b0b ldr r3, [pc, #44] @ (80002b0 <set_up_fonts+0x80>) + 8000282: 685b ldr r3, [r3, #4] + 8000284: 4a0b ldr r2, [pc, #44] @ (80002b4 <set_up_fonts+0x84>) + 8000286: 4618 mov r0, r3 + 8000288: 4611 mov r1, r2 + 800028a: f240 633e movw r3, #1598 @ 0x63e + 800028e: 461a mov r2, r3 + 8000290: f004 fc1e bl 8004ad0 <memcpy> + memcpy(jetbrains_mono_quarter.lookup, jetbrains_mono_quarter_lu, 128); + 8000294: 4b06 ldr r3, [pc, #24] @ (80002b0 <set_up_fonts+0x80>) + 8000296: 689b ldr r3, [r3, #8] + 8000298: 4a07 ldr r2, [pc, #28] @ (80002b8 <set_up_fonts+0x88>) + 800029a: 4618 mov r0, r3 + 800029c: 4611 mov r1, r2 + 800029e: 2380 movs r3, #128 @ 0x80 + 80002a0: 461a mov r2, r3 + 80002a2: f004 fc15 bl 8004ad0 <memcpy> +} + 80002a6: bf00 nop + 80002a8: bd80 pop {r7, pc} + 80002aa: bf00 nop + 80002ac: 20000740 .word 0x20000740 + 80002b0: 20000744 .word 0x20000744 + 80002b4: 20000008 .word 0x20000008 + 80002b8: 20000648 .word 0x20000648 + +080002bc <LL_RCC_LSE_SetDriveCapability>: + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + 80002bc: b480 push {r7} + 80002be: b083 sub sp, #12 + 80002c0: af00 add r7, sp, #0 + 80002c2: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); + 80002c4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80002c8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80002cc: f023 0218 bic.w r2, r3, #24 + 80002d0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80002d4: 687b ldr r3, [r7, #4] + 80002d6: 4313 orrs r3, r2 + 80002d8: f8c1 3090 str.w r3, [r1, #144] @ 0x90 +} + 80002dc: bf00 nop + 80002de: 370c adds r7, #12 + 80002e0: 46bd mov sp, r7 + 80002e2: f85d 7b04 ldr.w r7, [sp], #4 + 80002e6: 4770 bx lr + +080002e8 <LL_AHB2_GRP1_EnableClock>: + * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*) + * @note (*) Not supported by all the devices + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + 80002e8: b480 push {r7} + 80002ea: b085 sub sp, #20 + 80002ec: af00 add r7, sp, #0 + 80002ee: 6078 str r0, [r7, #4] + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2ENR, Periphs); + 80002f0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80002f4: 6cda ldr r2, [r3, #76] @ 0x4c + 80002f6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80002fa: 687b ldr r3, [r7, #4] + 80002fc: 4313 orrs r3, r2 + 80002fe: 64cb str r3, [r1, #76] @ 0x4c + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + 8000300: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000304: 6cda ldr r2, [r3, #76] @ 0x4c + 8000306: 687b ldr r3, [r7, #4] + 8000308: 4013 ands r3, r2 + 800030a: 60fb str r3, [r7, #12] + (void)tmpreg; + 800030c: 68fb ldr r3, [r7, #12] +} + 800030e: bf00 nop + 8000310: 3714 adds r7, #20 + 8000312: 46bd mov sp, r7 + 8000314: f85d 7b04 ldr.w r7, [sp], #4 + 8000318: 4770 bx lr + ... + +0800031c <main>: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 800031c: b580 push {r7, lr} + 800031e: b088 sub sp, #32 + 8000320: af04 add r7, sp, #16 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 8000322: f000 ff35 bl 8001190 <HAL_Init> + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 8000326: f000 f867 bl 80003f8 <SystemClock_Config> + + /* Configure the peripherals common clocks */ + PeriphCommonClock_Config(); + 800032a: f000 f8c1 bl 80004b0 <PeriphCommonClock_Config> + + /* IPCC initialisation */ + MX_IPCC_Init(); + 800032e: f000 f91d bl 800056c <MX_IPCC_Init> + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 8000332: f000 f9dd bl 80006f0 <MX_GPIO_Init> + MX_RTC_Init(); + 8000336: f000 f935 bl 80005a4 <MX_RTC_Init> + MX_SPI1_Init(); + 800033a: f000 f99b bl 8000674 <MX_SPI1_Init> + MX_I2C1_Init(); + 800033e: f000 f8d7 bl 80004f0 <MX_I2C1_Init> + MX_RF_Init(); + 8000342: f000 f927 bl 8000594 <MX_RF_Init> + /* USER CODE BEGIN 2 */ + set_up_fonts(); + 8000346: f7ff ff73 bl 8000230 <set_up_fonts> + SharpMem_Init(); + 800034a: f000 fa3d bl 80007c8 <SharpMem_Init> + uint8_t started = 0; + 800034e: 2300 movs r3, #0 + 8000350: 73fb strb r3, [r7, #15] + //SHARPMEM_write(&lcd, "Boot", 0, 0,0, true, false); + //SHARPMEM_refresh_display(&lcd); + + HAL_Delay(5000); + 8000352: f241 3088 movw r0, #5000 @ 0x1388 + 8000356: f000 ffa1 bl 800129c <HAL_Delay> + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + if (!started){ + 800035a: 7bfb ldrb r3, [r7, #15] + 800035c: 2b00 cmp r3, #0 + 800035e: d101 bne.n 8000364 <main+0x48> + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);*/ + + started = 1; + 8000360: 2301 movs r3, #1 + 8000362: 73fb strb r3, [r7, #15] + } + HAL_RTC_GetTime(&hrtc, &sTime, RTC_FORMAT_BIN); + 8000364: 2200 movs r2, #0 + 8000366: 491e ldr r1, [pc, #120] @ (80003e0 <main+0xc4>) + 8000368: 481e ldr r0, [pc, #120] @ (80003e4 <main+0xc8>) + 800036a: f003 fbc4 bl 8003af6 <HAL_RTC_GetTime> + HAL_RTC_GetDate(&hrtc, &sDate, RTC_FORMAT_BIN); + 800036e: 2200 movs r2, #0 + 8000370: 491d ldr r1, [pc, #116] @ (80003e8 <main+0xcc>) + 8000372: 481c ldr r0, [pc, #112] @ (80003e4 <main+0xc8>) + 8000374: f003 fca6 bl 8003cc4 <HAL_RTC_GetDate> + char timestr[15]; + sprintf(timestr, "%i:%i:%i", sTime.Hours, sTime.Minutes, sTime.Seconds); + 8000378: 4b19 ldr r3, [pc, #100] @ (80003e0 <main+0xc4>) + 800037a: 781b ldrb r3, [r3, #0] + 800037c: 461a mov r2, r3 + 800037e: 4b18 ldr r3, [pc, #96] @ (80003e0 <main+0xc4>) + 8000380: 785b ldrb r3, [r3, #1] + 8000382: 4619 mov r1, r3 + 8000384: 4b16 ldr r3, [pc, #88] @ (80003e0 <main+0xc4>) + 8000386: 789b ldrb r3, [r3, #2] + 8000388: 4638 mov r0, r7 + 800038a: 9300 str r3, [sp, #0] + 800038c: 460b mov r3, r1 + 800038e: 4917 ldr r1, [pc, #92] @ (80003ec <main+0xd0>) + 8000390: f004 fb38 bl 8004a04 <siprintf> + started++; + 8000394: 7bfb ldrb r3, [r7, #15] + 8000396: 3301 adds r3, #1 + 8000398: 73fb strb r3, [r7, #15] + + SHARPMEM_clear_display_buffer(&lcd); + 800039a: 4815 ldr r0, [pc, #84] @ (80003f0 <main+0xd4>) + 800039c: f000 fc75 bl 8000c8a <SHARPMEM_clear_display_buffer> + SHARPMEM_write(&lcd, timestr, 0, 30, 20, true, false); + 80003a0: 4639 mov r1, r7 + 80003a2: 2300 movs r3, #0 + 80003a4: 9302 str r3, [sp, #8] + 80003a6: 2301 movs r3, #1 + 80003a8: 9301 str r3, [sp, #4] + 80003aa: 2314 movs r3, #20 + 80003ac: 9300 str r3, [sp, #0] + 80003ae: 231e movs r3, #30 + 80003b0: 2200 movs r2, #0 + 80003b2: 480f ldr r0, [pc, #60] @ (80003f0 <main+0xd4>) + 80003b4: f000 fac0 bl 8000938 <SHARPMEM_write> + SHARPMEM_refresh_display(&lcd); + 80003b8: 480d ldr r0, [pc, #52] @ (80003f0 <main+0xd4>) + 80003ba: f000 fbb9 bl 8000b30 <SHARPMEM_refresh_display> + //HAL_Delay(900); + + HAL_SuspendTick(); + 80003be: f000 ff91 bl 80012e4 <HAL_SuspendTick> + + + HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI); + 80003c2: 2001 movs r0, #1 + 80003c4: f001 fcda bl 8001d7c <HAL_PWREx_EnterSTOP2Mode> + HAL_RTCEx_DeactivateWakeUpTimer(&hrtc); + 80003c8: 4806 ldr r0, [pc, #24] @ (80003e4 <main+0xc8>) + 80003ca: f003 fe57 bl 800407c <HAL_RTCEx_DeactivateWakeUpTimer> + __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU); + 80003ce: 4b09 ldr r3, [pc, #36] @ (80003f4 <main+0xd8>) + 80003d0: 221f movs r2, #31 + 80003d2: 619a str r2, [r3, #24] + SystemClock_Config(); + 80003d4: f000 f810 bl 80003f8 <SystemClock_Config> + HAL_ResumeTick(); + 80003d8: f000 ff94 bl 8001304 <HAL_ResumeTick> + { + 80003dc: e7bd b.n 800035a <main+0x3e> + 80003de: bf00 nop + 80003e0: 20000770 .word 0x20000770 + 80003e4: 20000818 .word 0x20000818 + 80003e8: 20000784 .word 0x20000784 + 80003ec: 08005200 .word 0x08005200 + 80003f0: 20000750 .word 0x20000750 + 80003f4: 58000400 .word 0x58000400 + +080003f8 <SystemClock_Config>: +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 80003f8: b580 push {r7, lr} + 80003fa: b09a sub sp, #104 @ 0x68 + 80003fc: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 80003fe: f107 0320 add.w r3, r7, #32 + 8000402: 2248 movs r2, #72 @ 0x48 + 8000404: 2100 movs r1, #0 + 8000406: 4618 mov r0, r3 + 8000408: f004 fb1e bl 8004a48 <memset> + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 800040c: 1d3b adds r3, r7, #4 + 800040e: 2200 movs r2, #0 + 8000410: 601a str r2, [r3, #0] + 8000412: 605a str r2, [r3, #4] + 8000414: 609a str r2, [r3, #8] + 8000416: 60da str r2, [r3, #12] + 8000418: 611a str r2, [r3, #16] + 800041a: 615a str r2, [r3, #20] + 800041c: 619a str r2, [r3, #24] + + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + 800041e: f001 fc8f bl 8001d40 <HAL_PWR_EnableBkUpAccess> + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH); + 8000422: 2010 movs r0, #16 + 8000424: f7ff ff4a bl 80002bc <LL_RCC_LSE_SetDriveCapability> + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 8000428: 4b20 ldr r3, [pc, #128] @ (80004ac <SystemClock_Config+0xb4>) + 800042a: 681b ldr r3, [r3, #0] + 800042c: f423 63c0 bic.w r3, r3, #1536 @ 0x600 + 8000430: 4a1e ldr r2, [pc, #120] @ (80004ac <SystemClock_Config+0xb4>) + 8000432: f443 7300 orr.w r3, r3, #512 @ 0x200 + 8000436: 6013 str r3, [r2, #0] + 8000438: 4b1c ldr r3, [pc, #112] @ (80004ac <SystemClock_Config+0xb4>) + 800043a: 681b ldr r3, [r3, #0] + 800043c: f403 63c0 and.w r3, r3, #1536 @ 0x600 + 8000440: 603b str r3, [r7, #0] + 8000442: 683b ldr r3, [r7, #0] + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE + 8000444: 2307 movs r3, #7 + 8000446: 623b str r3, [r7, #32] + |RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 8000448: f44f 3380 mov.w r3, #65536 @ 0x10000 + 800044c: 627b str r3, [r7, #36] @ 0x24 + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + 800044e: 2301 movs r3, #1 + 8000450: 62bb str r3, [r7, #40] @ 0x28 + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 8000452: f44f 7380 mov.w r3, #256 @ 0x100 + 8000456: 62fb str r3, [r7, #44] @ 0x2c + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 8000458: 2340 movs r3, #64 @ 0x40 + 800045a: 633b str r3, [r7, #48] @ 0x30 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 800045c: 2300 movs r3, #0 + 800045e: 64fb str r3, [r7, #76] @ 0x4c + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 8000460: f107 0320 add.w r3, r7, #32 + 8000464: 4618 mov r0, r3 + 8000466: f002 f813 bl 8002490 <HAL_RCC_OscConfig> + 800046a: 4603 mov r3, r0 + 800046c: 2b00 cmp r3, #0 + 800046e: d001 beq.n 8000474 <SystemClock_Config+0x7c> + { + Error_Handler(); + 8000470: f000 f9e2 bl 8000838 <Error_Handler> + } + + /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2 + 8000474: 236f movs r3, #111 @ 0x6f + 8000476: 607b str r3, [r7, #4] + |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; + 8000478: 2302 movs r3, #2 + 800047a: 60bb str r3, [r7, #8] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV16; + 800047c: 23b0 movs r3, #176 @ 0xb0 + 800047e: 60fb str r3, [r7, #12] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 8000480: 2300 movs r3, #0 + 8000482: 613b str r3, [r7, #16] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 8000484: 2300 movs r3, #0 + 8000486: 617b str r3, [r7, #20] + RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1; + 8000488: 2300 movs r3, #0 + 800048a: 61bb str r3, [r7, #24] + RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1; + 800048c: 2300 movs r3, #0 + 800048e: 61fb str r3, [r7, #28] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + 8000490: 1d3b adds r3, r7, #4 + 8000492: 2101 movs r1, #1 + 8000494: 4618 mov r0, r3 + 8000496: f002 fb6f bl 8002b78 <HAL_RCC_ClockConfig> + 800049a: 4603 mov r3, r0 + 800049c: 2b00 cmp r3, #0 + 800049e: d001 beq.n 80004a4 <SystemClock_Config+0xac> + { + Error_Handler(); + 80004a0: f000 f9ca bl 8000838 <Error_Handler> + } +} + 80004a4: bf00 nop + 80004a6: 3768 adds r7, #104 @ 0x68 + 80004a8: 46bd mov sp, r7 + 80004aa: bd80 pop {r7, pc} + 80004ac: 58000400 .word 0x58000400 + +080004b0 <PeriphCommonClock_Config>: +/** + * @brief Peripherals Common Clock Configuration + * @retval None + */ +void PeriphCommonClock_Config(void) +{ + 80004b0: b580 push {r7, lr} + 80004b2: b094 sub sp, #80 @ 0x50 + 80004b4: af00 add r7, sp, #0 + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 80004b6: 463b mov r3, r7 + 80004b8: 2250 movs r2, #80 @ 0x50 + 80004ba: 2100 movs r1, #0 + 80004bc: 4618 mov r0, r3 + 80004be: f004 fac3 bl 8004a48 <memset> + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_RFWAKEUP; + 80004c2: f44f 5340 mov.w r3, #12288 @ 0x3000 + 80004c6: 603b str r3, [r7, #0] + PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE; + 80004c8: f44f 4380 mov.w r3, #16384 @ 0x4000 + 80004cc: 647b str r3, [r7, #68] @ 0x44 + PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE; + 80004ce: 2302 movs r3, #2 + 80004d0: 64bb str r3, [r7, #72] @ 0x48 + PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1; + 80004d2: 2310 movs r3, #16 + 80004d4: 64fb str r3, [r7, #76] @ 0x4c + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 80004d6: 463b mov r3, r7 + 80004d8: 4618 mov r0, r3 + 80004da: f002 ff5e bl 800339a <HAL_RCCEx_PeriphCLKConfig> + 80004de: 4603 mov r3, r0 + 80004e0: 2b00 cmp r3, #0 + 80004e2: d001 beq.n 80004e8 <PeriphCommonClock_Config+0x38> + { + Error_Handler(); + 80004e4: f000 f9a8 bl 8000838 <Error_Handler> + } + /* USER CODE BEGIN Smps */ + + /* USER CODE END Smps */ +} + 80004e8: bf00 nop + 80004ea: 3750 adds r7, #80 @ 0x50 + 80004ec: 46bd mov sp, r7 + 80004ee: bd80 pop {r7, pc} + +080004f0 <MX_I2C1_Init>: + * @brief I2C1 Initialization Function + * @param None + * @retval None + */ +static void MX_I2C1_Init(void) +{ + 80004f0: b580 push {r7, lr} + 80004f2: af00 add r7, sp, #0 + /* USER CODE END I2C1_Init 0 */ + + /* USER CODE BEGIN I2C1_Init 1 */ + + /* USER CODE END I2C1_Init 1 */ + hi2c1.Instance = I2C1; + 80004f4: 4b1b ldr r3, [pc, #108] @ (8000564 <MX_I2C1_Init+0x74>) + 80004f6: 4a1c ldr r2, [pc, #112] @ (8000568 <MX_I2C1_Init+0x78>) + 80004f8: 601a str r2, [r3, #0] + hi2c1.Init.Timing = 0x00000508; + 80004fa: 4b1a ldr r3, [pc, #104] @ (8000564 <MX_I2C1_Init+0x74>) + 80004fc: f44f 62a1 mov.w r2, #1288 @ 0x508 + 8000500: 605a str r2, [r3, #4] + hi2c1.Init.OwnAddress1 = 0; + 8000502: 4b18 ldr r3, [pc, #96] @ (8000564 <MX_I2C1_Init+0x74>) + 8000504: 2200 movs r2, #0 + 8000506: 609a str r2, [r3, #8] + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 8000508: 4b16 ldr r3, [pc, #88] @ (8000564 <MX_I2C1_Init+0x74>) + 800050a: 2201 movs r2, #1 + 800050c: 60da str r2, [r3, #12] + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 800050e: 4b15 ldr r3, [pc, #84] @ (8000564 <MX_I2C1_Init+0x74>) + 8000510: 2200 movs r2, #0 + 8000512: 611a str r2, [r3, #16] + hi2c1.Init.OwnAddress2 = 0; + 8000514: 4b13 ldr r3, [pc, #76] @ (8000564 <MX_I2C1_Init+0x74>) + 8000516: 2200 movs r2, #0 + 8000518: 615a str r2, [r3, #20] + hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 800051a: 4b12 ldr r3, [pc, #72] @ (8000564 <MX_I2C1_Init+0x74>) + 800051c: 2200 movs r2, #0 + 800051e: 619a str r2, [r3, #24] + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 8000520: 4b10 ldr r3, [pc, #64] @ (8000564 <MX_I2C1_Init+0x74>) + 8000522: 2200 movs r2, #0 + 8000524: 61da str r2, [r3, #28] + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 8000526: 4b0f ldr r3, [pc, #60] @ (8000564 <MX_I2C1_Init+0x74>) + 8000528: 2200 movs r2, #0 + 800052a: 621a str r2, [r3, #32] + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + 800052c: 480d ldr r0, [pc, #52] @ (8000564 <MX_I2C1_Init+0x74>) + 800052e: f001 f9b5 bl 800189c <HAL_I2C_Init> + 8000532: 4603 mov r3, r0 + 8000534: 2b00 cmp r3, #0 + 8000536: d001 beq.n 800053c <MX_I2C1_Init+0x4c> + { + Error_Handler(); + 8000538: f000 f97e bl 8000838 <Error_Handler> + } + + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + 800053c: 2100 movs r1, #0 + 800053e: 4809 ldr r0, [pc, #36] @ (8000564 <MX_I2C1_Init+0x74>) + 8000540: f001 fa47 bl 80019d2 <HAL_I2CEx_ConfigAnalogFilter> + 8000544: 4603 mov r3, r0 + 8000546: 2b00 cmp r3, #0 + 8000548: d001 beq.n 800054e <MX_I2C1_Init+0x5e> + { + Error_Handler(); + 800054a: f000 f975 bl 8000838 <Error_Handler> + } + + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) + 800054e: 2100 movs r1, #0 + 8000550: 4804 ldr r0, [pc, #16] @ (8000564 <MX_I2C1_Init+0x74>) + 8000552: f001 fa89 bl 8001a68 <HAL_I2CEx_ConfigDigitalFilter> + 8000556: 4603 mov r3, r0 + 8000558: 2b00 cmp r3, #0 + 800055a: d001 beq.n 8000560 <MX_I2C1_Init+0x70> + { + Error_Handler(); + 800055c: f000 f96c bl 8000838 <Error_Handler> + } + /* USER CODE BEGIN I2C1_Init 2 */ + + /* USER CODE END I2C1_Init 2 */ + +} + 8000560: bf00 nop + 8000562: bd80 pop {r7, pc} + 8000564: 20000788 .word 0x20000788 + 8000568: 40005400 .word 0x40005400 + +0800056c <MX_IPCC_Init>: + * @brief IPCC Initialization Function + * @param None + * @retval None + */ +static void MX_IPCC_Init(void) +{ + 800056c: b580 push {r7, lr} + 800056e: af00 add r7, sp, #0 + /* USER CODE END IPCC_Init 0 */ + + /* USER CODE BEGIN IPCC_Init 1 */ + + /* USER CODE END IPCC_Init 1 */ + hipcc.Instance = IPCC; + 8000570: 4b06 ldr r3, [pc, #24] @ (800058c <MX_IPCC_Init+0x20>) + 8000572: 4a07 ldr r2, [pc, #28] @ (8000590 <MX_IPCC_Init+0x24>) + 8000574: 601a str r2, [r3, #0] + if (HAL_IPCC_Init(&hipcc) != HAL_OK) + 8000576: 4805 ldr r0, [pc, #20] @ (800058c <MX_IPCC_Init+0x20>) + 8000578: f001 fac2 bl 8001b00 <HAL_IPCC_Init> + 800057c: 4603 mov r3, r0 + 800057e: 2b00 cmp r3, #0 + 8000580: d001 beq.n 8000586 <MX_IPCC_Init+0x1a> + { + Error_Handler(); + 8000582: f000 f959 bl 8000838 <Error_Handler> + } + /* USER CODE BEGIN IPCC_Init 2 */ + + /* USER CODE END IPCC_Init 2 */ + +} + 8000586: bf00 nop + 8000588: bd80 pop {r7, pc} + 800058a: bf00 nop + 800058c: 200007dc .word 0x200007dc + 8000590: 58000c00 .word 0x58000c00 + +08000594 <MX_RF_Init>: + * @brief RF Initialization Function + * @param None + * @retval None + */ +static void MX_RF_Init(void) +{ + 8000594: b480 push {r7} + 8000596: af00 add r7, sp, #0 + /* USER CODE END RF_Init 1 */ + /* USER CODE BEGIN RF_Init 2 */ + + /* USER CODE END RF_Init 2 */ + +} + 8000598: bf00 nop + 800059a: 46bd mov sp, r7 + 800059c: f85d 7b04 ldr.w r7, [sp], #4 + 80005a0: 4770 bx lr + ... + +080005a4 <MX_RTC_Init>: + * @brief RTC Initialization Function + * @param None + * @retval None + */ +static void MX_RTC_Init(void) +{ + 80005a4: b580 push {r7, lr} + 80005a6: b086 sub sp, #24 + 80005a8: af00 add r7, sp, #0 + + /* USER CODE BEGIN RTC_Init 0 */ + + /* USER CODE END RTC_Init 0 */ + + RTC_TimeTypeDef sTime = {0}; + 80005aa: 1d3b adds r3, r7, #4 + 80005ac: 2200 movs r2, #0 + 80005ae: 601a str r2, [r3, #0] + 80005b0: 605a str r2, [r3, #4] + 80005b2: 609a str r2, [r3, #8] + 80005b4: 60da str r2, [r3, #12] + 80005b6: 611a str r2, [r3, #16] + RTC_DateTypeDef sDate = {0}; + 80005b8: 2300 movs r3, #0 + 80005ba: 603b str r3, [r7, #0] + + /* USER CODE END RTC_Init 1 */ + + /** Initialize RTC Only + */ + hrtc.Instance = RTC; + 80005bc: 4b2b ldr r3, [pc, #172] @ (800066c <MX_RTC_Init+0xc8>) + 80005be: 4a2c ldr r2, [pc, #176] @ (8000670 <MX_RTC_Init+0xcc>) + 80005c0: 601a str r2, [r3, #0] + hrtc.Init.HourFormat = RTC_HOURFORMAT_24; + 80005c2: 4b2a ldr r3, [pc, #168] @ (800066c <MX_RTC_Init+0xc8>) + 80005c4: 2200 movs r2, #0 + 80005c6: 605a str r2, [r3, #4] + hrtc.Init.AsynchPrediv = 127; + 80005c8: 4b28 ldr r3, [pc, #160] @ (800066c <MX_RTC_Init+0xc8>) + 80005ca: 227f movs r2, #127 @ 0x7f + 80005cc: 609a str r2, [r3, #8] + hrtc.Init.SynchPrediv = 255; + 80005ce: 4b27 ldr r3, [pc, #156] @ (800066c <MX_RTC_Init+0xc8>) + 80005d0: 22ff movs r2, #255 @ 0xff + 80005d2: 60da str r2, [r3, #12] + hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; + 80005d4: 4b25 ldr r3, [pc, #148] @ (800066c <MX_RTC_Init+0xc8>) + 80005d6: 2200 movs r2, #0 + 80005d8: 611a str r2, [r3, #16] + hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + 80005da: 4b24 ldr r3, [pc, #144] @ (800066c <MX_RTC_Init+0xc8>) + 80005dc: 2200 movs r2, #0 + 80005de: 619a str r2, [r3, #24] + hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + 80005e0: 4b22 ldr r3, [pc, #136] @ (800066c <MX_RTC_Init+0xc8>) + 80005e2: 2200 movs r2, #0 + 80005e4: 61da str r2, [r3, #28] + hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE; + 80005e6: 4b21 ldr r3, [pc, #132] @ (800066c <MX_RTC_Init+0xc8>) + 80005e8: 2200 movs r2, #0 + 80005ea: 615a str r2, [r3, #20] + if (HAL_RTC_Init(&hrtc) != HAL_OK) + 80005ec: 481f ldr r0, [pc, #124] @ (800066c <MX_RTC_Init+0xc8>) + 80005ee: f003 f95b bl 80038a8 <HAL_RTC_Init> + 80005f2: 4603 mov r3, r0 + 80005f4: 2b00 cmp r3, #0 + 80005f6: d001 beq.n 80005fc <MX_RTC_Init+0x58> + { + Error_Handler(); + 80005f8: f000 f91e bl 8000838 <Error_Handler> + + /* USER CODE END Check_RTC_BKUP */ + + /** Initialize RTC and set the Time and Date + */ + sTime.Hours = 12; + 80005fc: 230c movs r3, #12 + 80005fe: 713b strb r3, [r7, #4] + sTime.Minutes = 50; + 8000600: 2332 movs r3, #50 @ 0x32 + 8000602: 717b strb r3, [r7, #5] + sTime.Seconds = 30; + 8000604: 231e movs r3, #30 + 8000606: 71bb strb r3, [r7, #6] + sTime.SubSeconds = 0x0; + 8000608: 2300 movs r3, #0 + 800060a: 60bb str r3, [r7, #8] + sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; + 800060c: 2300 movs r3, #0 + 800060e: 613b str r3, [r7, #16] + sTime.StoreOperation = RTC_STOREOPERATION_RESET; + 8000610: 2300 movs r3, #0 + 8000612: 617b str r3, [r7, #20] + if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BIN) != HAL_OK) + 8000614: 1d3b adds r3, r7, #4 + 8000616: 2200 movs r2, #0 + 8000618: 4619 mov r1, r3 + 800061a: 4814 ldr r0, [pc, #80] @ (800066c <MX_RTC_Init+0xc8>) + 800061c: f003 f9cc bl 80039b8 <HAL_RTC_SetTime> + 8000620: 4603 mov r3, r0 + 8000622: 2b00 cmp r3, #0 + 8000624: d001 beq.n 800062a <MX_RTC_Init+0x86> + { + Error_Handler(); + 8000626: f000 f907 bl 8000838 <Error_Handler> + } + sDate.WeekDay = RTC_WEEKDAY_MONDAY; + 800062a: 2301 movs r3, #1 + 800062c: 703b strb r3, [r7, #0] + sDate.Month = RTC_MONTH_JANUARY; + 800062e: 2301 movs r3, #1 + 8000630: 707b strb r3, [r7, #1] + sDate.Date = 1; + 8000632: 2301 movs r3, #1 + 8000634: 70bb strb r3, [r7, #2] + sDate.Year = 0; + 8000636: 2300 movs r3, #0 + 8000638: 70fb strb r3, [r7, #3] + + if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BIN) != HAL_OK) + 800063a: 463b mov r3, r7 + 800063c: 2200 movs r2, #0 + 800063e: 4619 mov r1, r3 + 8000640: 480a ldr r0, [pc, #40] @ (800066c <MX_RTC_Init+0xc8>) + 8000642: f003 fab6 bl 8003bb2 <HAL_RTC_SetDate> + 8000646: 4603 mov r3, r0 + 8000648: 2b00 cmp r3, #0 + 800064a: d001 beq.n 8000650 <MX_RTC_Init+0xac> + { + Error_Handler(); + 800064c: f000 f8f4 bl 8000838 <Error_Handler> + } + + /** Enable the WakeUp + */ + if (HAL_RTCEx_SetWakeUpTimer_IT(&hrtc, 0, RTC_WAKEUPCLOCK_RTCCLK_DIV16) != HAL_OK) + 8000650: 2200 movs r2, #0 + 8000652: 2100 movs r1, #0 + 8000654: 4805 ldr r0, [pc, #20] @ (800066c <MX_RTC_Init+0xc8>) + 8000656: f003 fc45 bl 8003ee4 <HAL_RTCEx_SetWakeUpTimer_IT> + 800065a: 4603 mov r3, r0 + 800065c: 2b00 cmp r3, #0 + 800065e: d001 beq.n 8000664 <MX_RTC_Init+0xc0> + { + Error_Handler(); + 8000660: f000 f8ea bl 8000838 <Error_Handler> + } + /* USER CODE BEGIN RTC_Init 2 */ + + /* USER CODE END RTC_Init 2 */ + +} + 8000664: bf00 nop + 8000666: 3718 adds r7, #24 + 8000668: 46bd mov sp, r7 + 800066a: bd80 pop {r7, pc} + 800066c: 20000818 .word 0x20000818 + 8000670: 40002800 .word 0x40002800 + +08000674 <MX_SPI1_Init>: + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + 8000674: b580 push {r7, lr} + 8000676: af00 add r7, sp, #0 + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + 8000678: 4b1b ldr r3, [pc, #108] @ (80006e8 <MX_SPI1_Init+0x74>) + 800067a: 4a1c ldr r2, [pc, #112] @ (80006ec <MX_SPI1_Init+0x78>) + 800067c: 601a str r2, [r3, #0] + hspi1.Init.Mode = SPI_MODE_MASTER; + 800067e: 4b1a ldr r3, [pc, #104] @ (80006e8 <MX_SPI1_Init+0x74>) + 8000680: f44f 7282 mov.w r2, #260 @ 0x104 + 8000684: 605a str r2, [r3, #4] + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + 8000686: 4b18 ldr r3, [pc, #96] @ (80006e8 <MX_SPI1_Init+0x74>) + 8000688: 2200 movs r2, #0 + 800068a: 609a str r2, [r3, #8] + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + 800068c: 4b16 ldr r3, [pc, #88] @ (80006e8 <MX_SPI1_Init+0x74>) + 800068e: f44f 62e0 mov.w r2, #1792 @ 0x700 + 8000692: 60da str r2, [r3, #12] + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + 8000694: 4b14 ldr r3, [pc, #80] @ (80006e8 <MX_SPI1_Init+0x74>) + 8000696: 2200 movs r2, #0 + 8000698: 611a str r2, [r3, #16] + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + 800069a: 4b13 ldr r3, [pc, #76] @ (80006e8 <MX_SPI1_Init+0x74>) + 800069c: 2200 movs r2, #0 + 800069e: 615a str r2, [r3, #20] + hspi1.Init.NSS = SPI_NSS_SOFT; + 80006a0: 4b11 ldr r3, [pc, #68] @ (80006e8 <MX_SPI1_Init+0x74>) + 80006a2: f44f 7200 mov.w r2, #512 @ 0x200 + 80006a6: 619a str r2, [r3, #24] + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 80006a8: 4b0f ldr r3, [pc, #60] @ (80006e8 <MX_SPI1_Init+0x74>) + 80006aa: 2200 movs r2, #0 + 80006ac: 61da str r2, [r3, #28] + hspi1.Init.FirstBit = SPI_FIRSTBIT_LSB; + 80006ae: 4b0e ldr r3, [pc, #56] @ (80006e8 <MX_SPI1_Init+0x74>) + 80006b0: 2280 movs r2, #128 @ 0x80 + 80006b2: 621a str r2, [r3, #32] + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + 80006b4: 4b0c ldr r3, [pc, #48] @ (80006e8 <MX_SPI1_Init+0x74>) + 80006b6: 2200 movs r2, #0 + 80006b8: 625a str r2, [r3, #36] @ 0x24 + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 80006ba: 4b0b ldr r3, [pc, #44] @ (80006e8 <MX_SPI1_Init+0x74>) + 80006bc: 2200 movs r2, #0 + 80006be: 629a str r2, [r3, #40] @ 0x28 + hspi1.Init.CRCPolynomial = 7; + 80006c0: 4b09 ldr r3, [pc, #36] @ (80006e8 <MX_SPI1_Init+0x74>) + 80006c2: 2207 movs r2, #7 + 80006c4: 62da str r2, [r3, #44] @ 0x2c + hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + 80006c6: 4b08 ldr r3, [pc, #32] @ (80006e8 <MX_SPI1_Init+0x74>) + 80006c8: 2200 movs r2, #0 + 80006ca: 631a str r2, [r3, #48] @ 0x30 + hspi1.Init.NSSPMode = SPI_NSS_PULSE_DISABLE; + 80006cc: 4b06 ldr r3, [pc, #24] @ (80006e8 <MX_SPI1_Init+0x74>) + 80006ce: 2200 movs r2, #0 + 80006d0: 635a str r2, [r3, #52] @ 0x34 + if (HAL_SPI_Init(&hspi1) != HAL_OK) + 80006d2: 4805 ldr r0, [pc, #20] @ (80006e8 <MX_SPI1_Init+0x74>) + 80006d4: f003 fd62 bl 800419c <HAL_SPI_Init> + 80006d8: 4603 mov r3, r0 + 80006da: 2b00 cmp r3, #0 + 80006dc: d001 beq.n 80006e2 <MX_SPI1_Init+0x6e> + { + Error_Handler(); + 80006de: f000 f8ab bl 8000838 <Error_Handler> + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + 80006e2: bf00 nop + 80006e4: bd80 pop {r7, pc} + 80006e6: bf00 nop + 80006e8: 2000083c .word 0x2000083c + 80006ec: 40013000 .word 0x40013000 + +080006f0 <MX_GPIO_Init>: + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 80006f0: b580 push {r7, lr} + 80006f2: b086 sub sp, #24 + 80006f4: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80006f6: 1d3b adds r3, r7, #4 + 80006f8: 2200 movs r2, #0 + 80006fa: 601a str r2, [r3, #0] + 80006fc: 605a str r2, [r3, #4] + 80006fe: 609a str r2, [r3, #8] + 8000700: 60da str r2, [r3, #12] + 8000702: 611a str r2, [r3, #16] + /* USER CODE BEGIN MX_GPIO_Init_1 */ + + /* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8000704: 2004 movs r0, #4 + 8000706: f7ff fdef bl 80002e8 <LL_AHB2_GRP1_EnableClock> + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800070a: 2001 movs r0, #1 + 800070c: f7ff fdec bl 80002e8 <LL_AHB2_GRP1_EnableClock> + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8000710: 2002 movs r0, #2 + 8000712: f7ff fde9 bl 80002e8 <LL_AHB2_GRP1_EnableClock> + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_4|GPIO_PIN_6, GPIO_PIN_RESET); + 8000716: 2200 movs r2, #0 + 8000718: 2150 movs r1, #80 @ 0x50 + 800071a: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 800071e: f001 f881 bl 8001824 <HAL_GPIO_WritePin> + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_10, GPIO_PIN_SET); + 8000722: 2201 movs r2, #1 + 8000724: f44f 6180 mov.w r1, #1024 @ 0x400 + 8000728: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 800072c: f001 f87a bl 8001824 <HAL_GPIO_WritePin> + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4|GPIO_PIN_5, GPIO_PIN_SET); + 8000730: 2201 movs r2, #1 + 8000732: 2130 movs r1, #48 @ 0x30 + 8000734: 4823 ldr r0, [pc, #140] @ (80007c4 <MX_GPIO_Init+0xd4>) + 8000736: f001 f875 bl 8001824 <HAL_GPIO_WritePin> + + /*Configure GPIO pin : PA0 */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + 800073a: 2301 movs r3, #1 + 800073c: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + 800073e: f44f 1388 mov.w r3, #1114112 @ 0x110000 + 8000742: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + 8000744: 2302 movs r3, #2 + 8000746: 60fb str r3, [r7, #12] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8000748: 1d3b adds r3, r7, #4 + 800074a: 4619 mov r1, r3 + 800074c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 8000750: f000 fef8 bl 8001544 <HAL_GPIO_Init> + + /*Configure GPIO pins : PA4 PA6 PA10 */ + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_6|GPIO_PIN_10; + 8000754: f44f 638a mov.w r3, #1104 @ 0x450 + 8000758: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 800075a: 2301 movs r3, #1 + 800075c: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800075e: 2300 movs r3, #0 + 8000760: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8000762: 2300 movs r3, #0 + 8000764: 613b str r3, [r7, #16] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8000766: 1d3b adds r3, r7, #4 + 8000768: 4619 mov r1, r3 + 800076a: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 800076e: f000 fee9 bl 8001544 <HAL_GPIO_Init> + + /*Configure GPIO pins : PA8 PA11 PA15 */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_11|GPIO_PIN_15; + 8000772: f44f 4309 mov.w r3, #35072 @ 0x8900 + 8000776: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8000778: 2300 movs r3, #0 + 800077a: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 800077c: 2301 movs r3, #1 + 800077e: 60fb str r3, [r7, #12] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8000780: 1d3b adds r3, r7, #4 + 8000782: 4619 mov r1, r3 + 8000784: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 8000788: f000 fedc bl 8001544 <HAL_GPIO_Init> + + /*Configure GPIO pin : PB0 */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + 800078c: 2301 movs r3, #1 + 800078e: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8000790: 2300 movs r3, #0 + 8000792: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 8000794: 2301 movs r3, #1 + 8000796: 60fb str r3, [r7, #12] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8000798: 1d3b adds r3, r7, #4 + 800079a: 4619 mov r1, r3 + 800079c: 4809 ldr r0, [pc, #36] @ (80007c4 <MX_GPIO_Init+0xd4>) + 800079e: f000 fed1 bl 8001544 <HAL_GPIO_Init> + + /*Configure GPIO pins : PB4 PB5 */ + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; + 80007a2: 2330 movs r3, #48 @ 0x30 + 80007a4: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; + 80007a6: 2311 movs r3, #17 + 80007a8: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 80007aa: 2301 movs r3, #1 + 80007ac: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80007ae: 2300 movs r3, #0 + 80007b0: 613b str r3, [r7, #16] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 80007b2: 1d3b adds r3, r7, #4 + 80007b4: 4619 mov r1, r3 + 80007b6: 4803 ldr r0, [pc, #12] @ (80007c4 <MX_GPIO_Init+0xd4>) + 80007b8: f000 fec4 bl 8001544 <HAL_GPIO_Init> + + /* USER CODE BEGIN MX_GPIO_Init_2 */ + + /* USER CODE END MX_GPIO_Init_2 */ +} + 80007bc: bf00 nop + 80007be: 3718 adds r7, #24 + 80007c0: 46bd mov sp, r7 + 80007c2: bd80 pop {r7, pc} + 80007c4: 48000400 .word 0x48000400 + +080007c8 <SharpMem_Init>: + +/* USER CODE BEGIN 4 */ + +void SharpMem_Init() { + 80007c8: b580 push {r7, lr} + 80007ca: af00 add r7, sp, #0 + lcd.width = 160; + 80007cc: 4b18 ldr r3, [pc, #96] @ (8000830 <SharpMem_Init+0x68>) + 80007ce: 22a0 movs r2, #160 @ 0xa0 + 80007d0: 801a strh r2, [r3, #0] + lcd.height = 68; + 80007d2: 4b17 ldr r3, [pc, #92] @ (8000830 <SharpMem_Init+0x68>) + 80007d4: 2244 movs r2, #68 @ 0x44 + 80007d6: 805a strh r2, [r3, #2] + lcd.spidev = &hspi1; + 80007d8: 4b15 ldr r3, [pc, #84] @ (8000830 <SharpMem_Init+0x68>) + 80007da: 4a16 ldr r2, [pc, #88] @ (8000834 <SharpMem_Init+0x6c>) + 80007dc: 615a str r2, [r3, #20] + lcd.cs_pin_bank = GPIOA; + 80007de: 4b14 ldr r3, [pc, #80] @ (8000830 <SharpMem_Init+0x68>) + 80007e0: f04f 4290 mov.w r2, #1207959552 @ 0x48000000 + 80007e4: 609a str r2, [r3, #8] + lcd.cs_pin = GPIO_PIN_4; + 80007e6: 4b12 ldr r3, [pc, #72] @ (8000830 <SharpMem_Init+0x68>) + 80007e8: 2210 movs r2, #16 + 80007ea: 809a strh r2, [r3, #4] + lcd.lcdmode_pin_bank = GPIOA; + 80007ec: 4b10 ldr r3, [pc, #64] @ (8000830 <SharpMem_Init+0x68>) + 80007ee: f04f 4290 mov.w r2, #1207959552 @ 0x48000000 + 80007f2: 611a str r2, [r3, #16] + lcd.lcdmode_pin = GPIO_PIN_6; + 80007f4: 4b0e ldr r3, [pc, #56] @ (8000830 <SharpMem_Init+0x68>) + 80007f6: 2240 movs r2, #64 @ 0x40 + 80007f8: 819a strh r2, [r3, #12] + + lcd._sharpmem_vcom = SHARPMEM_BIT_VCOM; + 80007fa: 4b0d ldr r3, [pc, #52] @ (8000830 <SharpMem_Init+0x68>) + 80007fc: 2202 movs r2, #2 + 80007fe: 771a strb r2, [r3, #28] + lcd._buffer = malloc(sizeof(uint8_t)*(lcd.width * lcd.height / 8)); + 8000800: 4b0b ldr r3, [pc, #44] @ (8000830 <SharpMem_Init+0x68>) + 8000802: 881b ldrh r3, [r3, #0] + 8000804: 461a mov r2, r3 + 8000806: 4b0a ldr r3, [pc, #40] @ (8000830 <SharpMem_Init+0x68>) + 8000808: 885b ldrh r3, [r3, #2] + 800080a: fb02 f303 mul.w r3, r2, r3 + 800080e: 2b00 cmp r3, #0 + 8000810: da00 bge.n 8000814 <SharpMem_Init+0x4c> + 8000812: 3307 adds r3, #7 + 8000814: 10db asrs r3, r3, #3 + 8000816: 4618 mov r0, r3 + 8000818: f004 f83e bl 8004898 <malloc> + 800081c: 4603 mov r3, r0 + 800081e: 461a mov r2, r3 + 8000820: 4b03 ldr r3, [pc, #12] @ (8000830 <SharpMem_Init+0x68>) + 8000822: 619a str r2, [r3, #24] + SHARPMEM_clear_display(&lcd); + 8000824: 4802 ldr r0, [pc, #8] @ (8000830 <SharpMem_Init+0x68>) + 8000826: f000 f937 bl 8000a98 <SHARPMEM_clear_display> +} + 800082a: bf00 nop + 800082c: bd80 pop {r7, pc} + 800082e: bf00 nop + 8000830: 20000750 .word 0x20000750 + 8000834: 2000083c .word 0x2000083c + +08000838 <Error_Handler>: +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 8000838: b480 push {r7} + 800083a: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 800083c: b672 cpsid i +} + 800083e: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 8000840: bf00 nop + 8000842: e7fd b.n 8000840 <Error_Handler+0x8> + +08000844 <SHARPMEM_TOGGLEVCOM>: +#include "sharpmem.h" +#include "fonts.h" + +void SHARPMEM_TOGGLEVCOM(SharpMemDisplay_t *display) { + 8000844: b480 push {r7} + 8000846: b083 sub sp, #12 + 8000848: af00 add r7, sp, #0 + 800084a: 6078 str r0, [r7, #4] + display->_sharpmem_vcom = display->_sharpmem_vcom ? 0x00 : SHARPMEM_BIT_VCOM; + 800084c: 687b ldr r3, [r7, #4] + 800084e: 7f1b ldrb r3, [r3, #28] + 8000850: 2b00 cmp r3, #0 + 8000852: d001 beq.n 8000858 <SHARPMEM_TOGGLEVCOM+0x14> + 8000854: 2200 movs r2, #0 + 8000856: e000 b.n 800085a <SHARPMEM_TOGGLEVCOM+0x16> + 8000858: 2202 movs r2, #2 + 800085a: 687b ldr r3, [r7, #4] + 800085c: 771a strb r2, [r3, #28] +} + 800085e: bf00 nop + 8000860: 370c adds r7, #12 + 8000862: 46bd mov sp, r7 + 8000864: f85d 7b04 ldr.w r7, [sp], #4 + 8000868: 4770 bx lr + +0800086a <SHARPMEM_draw_pixel>: + +void SHARPMEM_draw_pixel(SharpMemDisplay_t *display, uint16_t x, uint16_t y, bool black) { + 800086a: b480 push {r7} + 800086c: b085 sub sp, #20 + 800086e: af00 add r7, sp, #0 + 8000870: 60f8 str r0, [r7, #12] + 8000872: 4608 mov r0, r1 + 8000874: 4611 mov r1, r2 + 8000876: 461a mov r2, r3 + 8000878: 4603 mov r3, r0 + 800087a: 817b strh r3, [r7, #10] + 800087c: 460b mov r3, r1 + 800087e: 813b strh r3, [r7, #8] + 8000880: 4613 mov r3, r2 + 8000882: 71fb strb r3, [r7, #7] + if ((x >= display->width) || (y >= display->height)) + 8000884: 68fb ldr r3, [r7, #12] + 8000886: 881b ldrh r3, [r3, #0] + 8000888: 897a ldrh r2, [r7, #10] + 800088a: 429a cmp r2, r3 + 800088c: d24d bcs.n 800092a <SHARPMEM_draw_pixel+0xc0> + 800088e: 68fb ldr r3, [r7, #12] + 8000890: 885b ldrh r3, [r3, #2] + 8000892: 893a ldrh r2, [r7, #8] + 8000894: 429a cmp r2, r3 + 8000896: d248 bcs.n 800092a <SHARPMEM_draw_pixel+0xc0> + return; + + if (black) { + 8000898: 79fb ldrb r3, [r7, #7] + 800089a: 2b00 cmp r3, #0 + 800089c: d021 beq.n 80008e2 <SHARPMEM_draw_pixel+0x78> + display->_buffer[(y * display->width + x) / 8] |= (0x1 << (x & 7)); //potentially expensive when run many times, use lookup from adafruit lib + 800089e: 68fb ldr r3, [r7, #12] + 80008a0: 699a ldr r2, [r3, #24] + 80008a2: 893b ldrh r3, [r7, #8] + 80008a4: 68f9 ldr r1, [r7, #12] + 80008a6: 8809 ldrh r1, [r1, #0] + 80008a8: fb03 f101 mul.w r1, r3, r1 + 80008ac: 897b ldrh r3, [r7, #10] + 80008ae: 440b add r3, r1 + 80008b0: 2b00 cmp r3, #0 + 80008b2: da00 bge.n 80008b6 <SHARPMEM_draw_pixel+0x4c> + 80008b4: 3307 adds r3, #7 + 80008b6: 10db asrs r3, r3, #3 + 80008b8: 4618 mov r0, r3 + 80008ba: 4603 mov r3, r0 + 80008bc: 4413 add r3, r2 + 80008be: 781b ldrb r3, [r3, #0] + 80008c0: b25a sxtb r2, r3 + 80008c2: 897b ldrh r3, [r7, #10] + 80008c4: f003 0307 and.w r3, r3, #7 + 80008c8: 2101 movs r1, #1 + 80008ca: fa01 f303 lsl.w r3, r1, r3 + 80008ce: b25b sxtb r3, r3 + 80008d0: 4313 orrs r3, r2 + 80008d2: b25a sxtb r2, r3 + 80008d4: 68fb ldr r3, [r7, #12] + 80008d6: 699b ldr r3, [r3, #24] + 80008d8: 4601 mov r1, r0 + 80008da: 440b add r3, r1 + 80008dc: b2d2 uxtb r2, r2 + 80008de: 701a strb r2, [r3, #0] + 80008e0: e024 b.n 800092c <SHARPMEM_draw_pixel+0xc2> + } else { + display->_buffer[(y * display->width + x) / 8] &= ~(0x1 << (x & 7)); + 80008e2: 68fb ldr r3, [r7, #12] + 80008e4: 699a ldr r2, [r3, #24] + 80008e6: 893b ldrh r3, [r7, #8] + 80008e8: 68f9 ldr r1, [r7, #12] + 80008ea: 8809 ldrh r1, [r1, #0] + 80008ec: fb03 f101 mul.w r1, r3, r1 + 80008f0: 897b ldrh r3, [r7, #10] + 80008f2: 440b add r3, r1 + 80008f4: 2b00 cmp r3, #0 + 80008f6: da00 bge.n 80008fa <SHARPMEM_draw_pixel+0x90> + 80008f8: 3307 adds r3, #7 + 80008fa: 10db asrs r3, r3, #3 + 80008fc: 4618 mov r0, r3 + 80008fe: 4603 mov r3, r0 + 8000900: 4413 add r3, r2 + 8000902: 781b ldrb r3, [r3, #0] + 8000904: b25a sxtb r2, r3 + 8000906: 897b ldrh r3, [r7, #10] + 8000908: f003 0307 and.w r3, r3, #7 + 800090c: 2101 movs r1, #1 + 800090e: fa01 f303 lsl.w r3, r1, r3 + 8000912: b25b sxtb r3, r3 + 8000914: 43db mvns r3, r3 + 8000916: b25b sxtb r3, r3 + 8000918: 4013 ands r3, r2 + 800091a: b25a sxtb r2, r3 + 800091c: 68fb ldr r3, [r7, #12] + 800091e: 699b ldr r3, [r3, #24] + 8000920: 4601 mov r1, r0 + 8000922: 440b add r3, r1 + 8000924: b2d2 uxtb r2, r2 + 8000926: 701a strb r2, [r3, #0] + 8000928: e000 b.n 800092c <SHARPMEM_draw_pixel+0xc2> + return; + 800092a: bf00 nop + } +} + 800092c: 3714 adds r7, #20 + 800092e: 46bd mov sp, r7 + 8000930: f85d 7b04 ldr.w r7, [sp], #4 + 8000934: 4770 bx lr + ... + +08000938 <SHARPMEM_write>: + +void SHARPMEM_draw_rect(SharpMemDisplay_t *display, uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, bool filled) { + +} + +void SHARPMEM_write(SharpMemDisplay_t *display, char *text, uint8_t font_index, uint16_t x0, uint16_t y0, bool inverse, bool force_bg) { + 8000938: b590 push {r4, r7, lr} + 800093a: b089 sub sp, #36 @ 0x24 + 800093c: af00 add r7, sp, #0 + 800093e: 60f8 str r0, [r7, #12] + 8000940: 60b9 str r1, [r7, #8] + 8000942: 4611 mov r1, r2 + 8000944: 461a mov r2, r3 + 8000946: 460b mov r3, r1 + 8000948: 71fb strb r3, [r7, #7] + 800094a: 4613 mov r3, r2 + 800094c: 80bb strh r3, [r7, #4] + } + } + }*/ + + // potentially inefficient but simplest algorithm involving reading and writing every single pixel + if(font_index > NUMBER_OF_FONTS) return; + 800094e: 79fb ldrb r3, [r7, #7] + 8000950: 2b01 cmp r3, #1 + 8000952: f200 809b bhi.w 8000a8c <SHARPMEM_write+0x154> + bitmap_font_t *font = fonts[font_index]; + 8000956: 4b4f ldr r3, [pc, #316] @ (8000a94 <SHARPMEM_write+0x15c>) + 8000958: 681a ldr r2, [r3, #0] + 800095a: 79fb ldrb r3, [r7, #7] + 800095c: 009b lsls r3, r3, #2 + 800095e: 4413 add r3, r2 + 8000960: 681b ldr r3, [r3, #0] + 8000962: 617b str r3, [r7, #20] + + for (uint8_t ci = 0; ci < strlen(text); ci++){ + 8000964: 2300 movs r3, #0 + 8000966: 77fb strb r3, [r7, #31] + 8000968: e087 b.n 8000a7a <SHARPMEM_write+0x142> + uint16_t base_index = font->lookup[(uint8_t)text[ci]]; + 800096a: 697b ldr r3, [r7, #20] + 800096c: 689b ldr r3, [r3, #8] + 800096e: 7ffa ldrb r2, [r7, #31] + 8000970: 68b9 ldr r1, [r7, #8] + 8000972: 440a add r2, r1 + 8000974: 7812 ldrb r2, [r2, #0] + 8000976: 4413 add r3, r2 + 8000978: 781b ldrb r3, [r3, #0] + 800097a: 827b strh r3, [r7, #18] + + for (uint16_t y = 0; y < font->char_h; y++) { + 800097c: 2300 movs r3, #0 + 800097e: 83bb strh r3, [r7, #28] + 8000980: e072 b.n 8000a68 <SHARPMEM_write+0x130> + uint16_t charbase = base_index*font->bytes_per_char + y*font->bytes_per_row; + 8000982: 697b ldr r3, [r7, #20] + 8000984: 78db ldrb r3, [r3, #3] + 8000986: 461a mov r2, r3 + 8000988: 8a7b ldrh r3, [r7, #18] + 800098a: fb13 f302 smulbb r3, r3, r2 + 800098e: b29a uxth r2, r3 + 8000990: 697b ldr r3, [r7, #20] + 8000992: 789b ldrb r3, [r3, #2] + 8000994: 4619 mov r1, r3 + 8000996: 8bbb ldrh r3, [r7, #28] + 8000998: fb13 f301 smulbb r3, r3, r1 + 800099c: b29b uxth r3, r3 + 800099e: 4413 add r3, r2 + 80009a0: 823b strh r3, [r7, #16] + for (uint16_t x = 0; x < font->char_w; x++) { + 80009a2: 2300 movs r3, #0 + 80009a4: 837b strh r3, [r7, #26] + 80009a6: e056 b.n 8000a56 <SHARPMEM_write+0x11e> + bool white = ( (font->font_bytes[charbase + x/8] & (0x1 << (x%8)) ) == 0 ); + 80009a8: 697b ldr r3, [r7, #20] + 80009aa: 685b ldr r3, [r3, #4] + 80009ac: 8a3a ldrh r2, [r7, #16] + 80009ae: 8b79 ldrh r1, [r7, #26] + 80009b0: 08c9 lsrs r1, r1, #3 + 80009b2: b289 uxth r1, r1 + 80009b4: 440a add r2, r1 + 80009b6: 4413 add r3, r2 + 80009b8: 781b ldrb r3, [r3, #0] + 80009ba: 461a mov r2, r3 + 80009bc: 8b7b ldrh r3, [r7, #26] + 80009be: f003 0307 and.w r3, r3, #7 + 80009c2: fa42 f303 asr.w r3, r2, r3 + 80009c6: f003 0301 and.w r3, r3, #1 + 80009ca: 2b00 cmp r3, #0 + 80009cc: bf0c ite eq + 80009ce: 2301 moveq r3, #1 + 80009d0: 2300 movne r3, #0 + 80009d2: 767b strb r3, [r7, #25] + if (!force_bg && white) continue; + 80009d4: f897 3038 ldrb.w r3, [r7, #56] @ 0x38 + 80009d8: f083 0301 eor.w r3, r3, #1 + 80009dc: b2db uxtb r3, r3 + 80009de: 2b00 cmp r3, #0 + 80009e0: d002 beq.n 80009e8 <SHARPMEM_write+0xb0> + 80009e2: 7e7b ldrb r3, [r7, #25] + 80009e4: 2b00 cmp r3, #0 + 80009e6: d132 bne.n 8000a4e <SHARPMEM_write+0x116> + if (inverse) white = !white; + 80009e8: f897 3034 ldrb.w r3, [r7, #52] @ 0x34 + 80009ec: 2b00 cmp r3, #0 + 80009ee: d00d beq.n 8000a0c <SHARPMEM_write+0xd4> + 80009f0: 7e7b ldrb r3, [r7, #25] + 80009f2: 2b00 cmp r3, #0 + 80009f4: bf14 ite ne + 80009f6: 2301 movne r3, #1 + 80009f8: 2300 moveq r3, #0 + 80009fa: b2db uxtb r3, r3 + 80009fc: f083 0301 eor.w r3, r3, #1 + 8000a00: b2db uxtb r3, r3 + 8000a02: 767b strb r3, [r7, #25] + 8000a04: 7e7b ldrb r3, [r7, #25] + 8000a06: f003 0301 and.w r3, r3, #1 + 8000a0a: 767b strb r3, [r7, #25] + SHARPMEM_draw_pixel(display, x0+ci*font->char_w+x, y0+y, !white); + 8000a0c: 7ffb ldrb r3, [r7, #31] + 8000a0e: b29b uxth r3, r3 + 8000a10: 697a ldr r2, [r7, #20] + 8000a12: 7812 ldrb r2, [r2, #0] + 8000a14: fb13 f302 smulbb r3, r3, r2 + 8000a18: b29a uxth r2, r3 + 8000a1a: 88bb ldrh r3, [r7, #4] + 8000a1c: 4413 add r3, r2 + 8000a1e: b29a uxth r2, r3 + 8000a20: 8b7b ldrh r3, [r7, #26] + 8000a22: 4413 add r3, r2 + 8000a24: b299 uxth r1, r3 + 8000a26: 8e3a ldrh r2, [r7, #48] @ 0x30 + 8000a28: 8bbb ldrh r3, [r7, #28] + 8000a2a: 4413 add r3, r2 + 8000a2c: b29a uxth r2, r3 + 8000a2e: 7e7b ldrb r3, [r7, #25] + 8000a30: 2b00 cmp r3, #0 + 8000a32: bf14 ite ne + 8000a34: 2301 movne r3, #1 + 8000a36: 2300 moveq r3, #0 + 8000a38: b2db uxtb r3, r3 + 8000a3a: f083 0301 eor.w r3, r3, #1 + 8000a3e: b2db uxtb r3, r3 + 8000a40: f003 0301 and.w r3, r3, #1 + 8000a44: b2db uxtb r3, r3 + 8000a46: 68f8 ldr r0, [r7, #12] + 8000a48: f7ff ff0f bl 800086a <SHARPMEM_draw_pixel> + 8000a4c: e000 b.n 8000a50 <SHARPMEM_write+0x118> + if (!force_bg && white) continue; + 8000a4e: bf00 nop + for (uint16_t x = 0; x < font->char_w; x++) { + 8000a50: 8b7b ldrh r3, [r7, #26] + 8000a52: 3301 adds r3, #1 + 8000a54: 837b strh r3, [r7, #26] + 8000a56: 697b ldr r3, [r7, #20] + 8000a58: 781b ldrb r3, [r3, #0] + 8000a5a: 461a mov r2, r3 + 8000a5c: 8b7b ldrh r3, [r7, #26] + 8000a5e: 4293 cmp r3, r2 + 8000a60: d3a2 bcc.n 80009a8 <SHARPMEM_write+0x70> + for (uint16_t y = 0; y < font->char_h; y++) { + 8000a62: 8bbb ldrh r3, [r7, #28] + 8000a64: 3301 adds r3, #1 + 8000a66: 83bb strh r3, [r7, #28] + 8000a68: 697b ldr r3, [r7, #20] + 8000a6a: 785b ldrb r3, [r3, #1] + 8000a6c: 461a mov r2, r3 + 8000a6e: 8bbb ldrh r3, [r7, #28] + 8000a70: 4293 cmp r3, r2 + 8000a72: d386 bcc.n 8000982 <SHARPMEM_write+0x4a> + for (uint8_t ci = 0; ci < strlen(text); ci++){ + 8000a74: 7ffb ldrb r3, [r7, #31] + 8000a76: 3301 adds r3, #1 + 8000a78: 77fb strb r3, [r7, #31] + 8000a7a: 7ffc ldrb r4, [r7, #31] + 8000a7c: 68b8 ldr r0, [r7, #8] + 8000a7e: f7ff fb7f bl 8000180 <strlen> + 8000a82: 4603 mov r3, r0 + 8000a84: 429c cmp r4, r3 + 8000a86: f4ff af70 bcc.w 800096a <SHARPMEM_write+0x32> + 8000a8a: e000 b.n 8000a8e <SHARPMEM_write+0x156> + if(font_index > NUMBER_OF_FONTS) return; + 8000a8c: bf00 nop + } + } + } +} + 8000a8e: 3724 adds r7, #36 @ 0x24 + 8000a90: 46bd mov sp, r7 + 8000a92: bd90 pop {r4, r7, pc} + 8000a94: 20000740 .word 0x20000740 + +08000a98 <SHARPMEM_clear_display>: + if ((x >= display->width) || (y >= display->height)) + return 1; //1 = empty + +} + +void SHARPMEM_clear_display(SharpMemDisplay_t *display) { + 8000a98: b580 push {r7, lr} + 8000a9a: b084 sub sp, #16 + 8000a9c: af00 add r7, sp, #0 + 8000a9e: 6078 str r0, [r7, #4] + HAL_GPIO_WritePin(display->lcdmode_pin_bank, display->lcdmode_pin, GPIO_PIN_RESET); // set lcdmode pin to low for manual vcom control + 8000aa0: 687b ldr r3, [r7, #4] + 8000aa2: 6918 ldr r0, [r3, #16] + 8000aa4: 687b ldr r3, [r7, #4] + 8000aa6: 899b ldrh r3, [r3, #12] + 8000aa8: 2200 movs r2, #0 + 8000aaa: 4619 mov r1, r3 + 8000aac: f000 feba bl 8001824 <HAL_GPIO_WritePin> + + memset(display->_buffer, 0xff, (display->width * display->height) / 8); + 8000ab0: 687b ldr r3, [r7, #4] + 8000ab2: 6998 ldr r0, [r3, #24] + 8000ab4: 687b ldr r3, [r7, #4] + 8000ab6: 881b ldrh r3, [r3, #0] + 8000ab8: 461a mov r2, r3 + 8000aba: 687b ldr r3, [r7, #4] + 8000abc: 885b ldrh r3, [r3, #2] + 8000abe: fb02 f303 mul.w r3, r2, r3 + 8000ac2: 2b00 cmp r3, #0 + 8000ac4: da00 bge.n 8000ac8 <SHARPMEM_clear_display+0x30> + 8000ac6: 3307 adds r3, #7 + 8000ac8: 10db asrs r3, r3, #3 + 8000aca: 461a mov r2, r3 + 8000acc: 21ff movs r1, #255 @ 0xff + 8000ace: f003 ffbb bl 8004a48 <memset> + + // Send the clear screen command rather than doing a HW refresh (quicker) + + uint8_t clear_data[2] = {(uint8_t)(display->_sharpmem_vcom | SHARPMEM_BIT_CLEAR), + 8000ad2: 687b ldr r3, [r7, #4] + 8000ad4: 7f1b ldrb r3, [r3, #28] + 8000ad6: f043 0304 orr.w r3, r3, #4 + 8000ada: b2db uxtb r3, r3 + 8000adc: 733b strb r3, [r7, #12] + 8000ade: 2300 movs r3, #0 + 8000ae0: 737b strb r3, [r7, #13] + 0x00}; + + HAL_GPIO_WritePin(display->cs_pin_bank, display->cs_pin, GPIO_PIN_SET); + 8000ae2: 687b ldr r3, [r7, #4] + 8000ae4: 6898 ldr r0, [r3, #8] + 8000ae6: 687b ldr r3, [r7, #4] + 8000ae8: 889b ldrh r3, [r3, #4] + 8000aea: 2201 movs r2, #1 + 8000aec: 4619 mov r1, r3 + 8000aee: f000 fe99 bl 8001824 <HAL_GPIO_WritePin> + HAL_SPI_Transmit(display->spidev, clear_data, 2, 16); + 8000af2: 687b ldr r3, [r7, #4] + 8000af4: 6958 ldr r0, [r3, #20] + 8000af6: f107 010c add.w r1, r7, #12 + 8000afa: 2310 movs r3, #16 + 8000afc: 2202 movs r2, #2 + 8000afe: f003 fbf0 bl 80042e2 <HAL_SPI_Transmit> + HAL_GPIO_WritePin(display->cs_pin_bank, display->cs_pin, GPIO_PIN_RESET); + 8000b02: 687b ldr r3, [r7, #4] + 8000b04: 6898 ldr r0, [r3, #8] + 8000b06: 687b ldr r3, [r7, #4] + 8000b08: 889b ldrh r3, [r3, #4] + 8000b0a: 2200 movs r2, #0 + 8000b0c: 4619 mov r1, r3 + 8000b0e: f000 fe89 bl 8001824 <HAL_GPIO_WritePin> + + SHARPMEM_TOGGLEVCOM(display); + 8000b12: 6878 ldr r0, [r7, #4] + 8000b14: f7ff fe96 bl 8000844 <SHARPMEM_TOGGLEVCOM> + HAL_GPIO_WritePin(display->lcdmode_pin_bank, display->lcdmode_pin, GPIO_PIN_SET); // set lcdmode pin to high for 1Hz external vcom signal + 8000b18: 687b ldr r3, [r7, #4] + 8000b1a: 6918 ldr r0, [r3, #16] + 8000b1c: 687b ldr r3, [r7, #4] + 8000b1e: 899b ldrh r3, [r3, #12] + 8000b20: 2201 movs r2, #1 + 8000b22: 4619 mov r1, r3 + 8000b24: f000 fe7e bl 8001824 <HAL_GPIO_WritePin> +} + 8000b28: bf00 nop + 8000b2a: 3710 adds r7, #16 + 8000b2c: 46bd mov sp, r7 + 8000b2e: bd80 pop {r7, pc} + +08000b30 <SHARPMEM_refresh_display>: + +void SHARPMEM_refresh_display(SharpMemDisplay_t *display) { + 8000b30: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 8000b34: b089 sub sp, #36 @ 0x24 + 8000b36: af00 add r7, sp, #0 + 8000b38: 6078 str r0, [r7, #4] + HAL_GPIO_WritePin(display->lcdmode_pin_bank, display->lcdmode_pin, GPIO_PIN_RESET); // set lcdmode pin to low for manual vcom control + 8000b3a: 687b ldr r3, [r7, #4] + 8000b3c: 6918 ldr r0, [r3, #16] + 8000b3e: 687b ldr r3, [r7, #4] + 8000b40: 899b ldrh r3, [r3, #12] + 8000b42: 2200 movs r2, #0 + 8000b44: 4619 mov r1, r3 + 8000b46: f000 fe6d bl 8001824 <HAL_GPIO_WritePin> + uint16_t i, currentline; + + //spidev->beginTransaction(); + // Send the write command + HAL_GPIO_WritePin(display->cs_pin_bank, display->cs_pin, GPIO_PIN_SET); + 8000b4a: 687b ldr r3, [r7, #4] + 8000b4c: 6898 ldr r0, [r3, #8] + 8000b4e: 687b ldr r3, [r7, #4] + 8000b50: 889b ldrh r3, [r3, #4] + 8000b52: 2201 movs r2, #1 + 8000b54: 4619 mov r1, r3 + 8000b56: f000 fe65 bl 8001824 <HAL_GPIO_WritePin> + uint8_t write_data[1] = {0x00 | SHARPMEM_BIT_WRITECMD}; + 8000b5a: 2301 movs r3, #1 + 8000b5c: 733b strb r3, [r7, #12] + HAL_SPI_Transmit(display->spidev, write_data, 1, 100); + 8000b5e: 687b ldr r3, [r7, #4] + 8000b60: 6958 ldr r0, [r3, #20] + 8000b62: f107 010c add.w r1, r7, #12 + 8000b66: 2364 movs r3, #100 @ 0x64 + 8000b68: 2201 movs r2, #1 + 8000b6a: f003 fbba bl 80042e2 <HAL_SPI_Transmit> + SHARPMEM_TOGGLEVCOM(display); + 8000b6e: 6878 ldr r0, [r7, #4] + 8000b70: f7ff fe68 bl 8000844 <SHARPMEM_TOGGLEVCOM> + + uint8_t bytes_per_line = display->width / 8; + 8000b74: 687b ldr r3, [r7, #4] + 8000b76: 881b ldrh r3, [r3, #0] + 8000b78: 08db lsrs r3, r3, #3 + 8000b7a: b29b uxth r3, r3 + 8000b7c: 777b strb r3, [r7, #29] + uint16_t totalbytes = (display->width * display->height) / 8; + 8000b7e: 687b ldr r3, [r7, #4] + 8000b80: 881b ldrh r3, [r3, #0] + 8000b82: 461a mov r2, r3 + 8000b84: 687b ldr r3, [r7, #4] + 8000b86: 885b ldrh r3, [r3, #2] + 8000b88: fb02 f303 mul.w r3, r2, r3 + 8000b8c: 2b00 cmp r3, #0 + 8000b8e: da00 bge.n 8000b92 <SHARPMEM_refresh_display+0x62> + 8000b90: 3307 adds r3, #7 + 8000b92: 10db asrs r3, r3, #3 + 8000b94: 837b strh r3, [r7, #26] + + for (i = 0; i < totalbytes; i += bytes_per_line) { + 8000b96: 2300 movs r3, #0 + 8000b98: 83fb strh r3, [r7, #30] + 8000b9a: e056 b.n 8000c4a <SHARPMEM_refresh_display+0x11a> + 8000b9c: 466b mov r3, sp + 8000b9e: 461e mov r6, r3 + uint8_t line[bytes_per_line + 2]; + 8000ba0: 7f7b ldrb r3, [r7, #29] + 8000ba2: 1c99 adds r1, r3, #2 + 8000ba4: 1e4b subs r3, r1, #1 + 8000ba6: 617b str r3, [r7, #20] + 8000ba8: 460a mov r2, r1 + 8000baa: 2300 movs r3, #0 + 8000bac: 4614 mov r4, r2 + 8000bae: 461d mov r5, r3 + 8000bb0: f04f 0200 mov.w r2, #0 + 8000bb4: f04f 0300 mov.w r3, #0 + 8000bb8: 00eb lsls r3, r5, #3 + 8000bba: ea43 7354 orr.w r3, r3, r4, lsr #29 + 8000bbe: 00e2 lsls r2, r4, #3 + 8000bc0: 460a mov r2, r1 + 8000bc2: 2300 movs r3, #0 + 8000bc4: 4690 mov r8, r2 + 8000bc6: 4699 mov r9, r3 + 8000bc8: f04f 0200 mov.w r2, #0 + 8000bcc: f04f 0300 mov.w r3, #0 + 8000bd0: ea4f 03c9 mov.w r3, r9, lsl #3 + 8000bd4: ea43 7358 orr.w r3, r3, r8, lsr #29 + 8000bd8: ea4f 02c8 mov.w r2, r8, lsl #3 + 8000bdc: 460b mov r3, r1 + 8000bde: 3307 adds r3, #7 + 8000be0: 08db lsrs r3, r3, #3 + 8000be2: 00db lsls r3, r3, #3 + 8000be4: ebad 0d03 sub.w sp, sp, r3 + 8000be8: 466b mov r3, sp + 8000bea: 3300 adds r3, #0 + 8000bec: 613b str r3, [r7, #16] + + // Send address byte + currentline = ((i + 1) / (display->width / 8)) + 1; + 8000bee: 8bfb ldrh r3, [r7, #30] + 8000bf0: 3301 adds r3, #1 + 8000bf2: 687a ldr r2, [r7, #4] + 8000bf4: 8812 ldrh r2, [r2, #0] + 8000bf6: 08d2 lsrs r2, r2, #3 + 8000bf8: b292 uxth r2, r2 + 8000bfa: fb93 f3f2 sdiv r3, r3, r2 + 8000bfe: b29b uxth r3, r3 + 8000c00: 3301 adds r3, #1 + 8000c02: 81fb strh r3, [r7, #14] + line[0] = currentline; + 8000c04: 89fb ldrh r3, [r7, #14] + 8000c06: b2da uxtb r2, r3 + 8000c08: 693b ldr r3, [r7, #16] + 8000c0a: 701a strb r2, [r3, #0] + // copy over this line + memcpy(line + 1, display->_buffer + i, bytes_per_line); + 8000c0c: 693b ldr r3, [r7, #16] + 8000c0e: 1c58 adds r0, r3, #1 + 8000c10: 687b ldr r3, [r7, #4] + 8000c12: 699a ldr r2, [r3, #24] + 8000c14: 8bfb ldrh r3, [r7, #30] + 8000c16: 4413 add r3, r2 + 8000c18: 7f7a ldrb r2, [r7, #29] + 8000c1a: 4619 mov r1, r3 + 8000c1c: f003 ff58 bl 8004ad0 <memcpy> + // Send end of line + line[bytes_per_line + 1] = 0x00; + 8000c20: 7f7b ldrb r3, [r7, #29] + 8000c22: 3301 adds r3, #1 + 8000c24: 693a ldr r2, [r7, #16] + 8000c26: 2100 movs r1, #0 + 8000c28: 54d1 strb r1, [r2, r3] + // send it! + HAL_SPI_Transmit(display->spidev, line, bytes_per_line + 2, 16); + 8000c2a: 687b ldr r3, [r7, #4] + 8000c2c: 6958 ldr r0, [r3, #20] + 8000c2e: 7f7b ldrb r3, [r7, #29] + 8000c30: b29b uxth r3, r3 + 8000c32: 3302 adds r3, #2 + 8000c34: b29a uxth r2, r3 + 8000c36: 2310 movs r3, #16 + 8000c38: 6939 ldr r1, [r7, #16] + 8000c3a: f003 fb52 bl 80042e2 <HAL_SPI_Transmit> + 8000c3e: 46b5 mov sp, r6 + for (i = 0; i < totalbytes; i += bytes_per_line) { + 8000c40: 7f7b ldrb r3, [r7, #29] + 8000c42: b29a uxth r2, r3 + 8000c44: 8bfb ldrh r3, [r7, #30] + 8000c46: 4413 add r3, r2 + 8000c48: 83fb strh r3, [r7, #30] + 8000c4a: 8bfa ldrh r2, [r7, #30] + 8000c4c: 8b7b ldrh r3, [r7, #26] + 8000c4e: 429a cmp r2, r3 + 8000c50: d3a4 bcc.n 8000b9c <SHARPMEM_refresh_display+0x6c> + } + + // Send another trailing 8 bits for the last line + HAL_SPI_Transmit(display->spidev, (0x00), 1, 100); + 8000c52: 687b ldr r3, [r7, #4] + 8000c54: 6958 ldr r0, [r3, #20] + 8000c56: 2364 movs r3, #100 @ 0x64 + 8000c58: 2201 movs r2, #1 + 8000c5a: 2100 movs r1, #0 + 8000c5c: f003 fb41 bl 80042e2 <HAL_SPI_Transmit> + HAL_GPIO_WritePin(display->cs_pin_bank, display->cs_pin, GPIO_PIN_RESET); + 8000c60: 687b ldr r3, [r7, #4] + 8000c62: 6898 ldr r0, [r3, #8] + 8000c64: 687b ldr r3, [r7, #4] + 8000c66: 889b ldrh r3, [r3, #4] + 8000c68: 2200 movs r2, #0 + 8000c6a: 4619 mov r1, r3 + 8000c6c: f000 fdda bl 8001824 <HAL_GPIO_WritePin> + HAL_GPIO_WritePin(display->lcdmode_pin_bank, display->lcdmode_pin, GPIO_PIN_SET); // set lcdmode pin to high for 1Hz external vcom signal + 8000c70: 687b ldr r3, [r7, #4] + 8000c72: 6918 ldr r0, [r3, #16] + 8000c74: 687b ldr r3, [r7, #4] + 8000c76: 899b ldrh r3, [r3, #12] + 8000c78: 2201 movs r2, #1 + 8000c7a: 4619 mov r1, r3 + 8000c7c: f000 fdd2 bl 8001824 <HAL_GPIO_WritePin> +} + 8000c80: bf00 nop + 8000c82: 3724 adds r7, #36 @ 0x24 + 8000c84: 46bd mov sp, r7 + 8000c86: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + +08000c8a <SHARPMEM_clear_display_buffer>: + +void SHARPMEM_clear_display_buffer(SharpMemDisplay_t *display) { + 8000c8a: b580 push {r7, lr} + 8000c8c: b082 sub sp, #8 + 8000c8e: af00 add r7, sp, #0 + 8000c90: 6078 str r0, [r7, #4] + memset(display->_buffer, 0xff, (display->width * display->height) / 8); + 8000c92: 687b ldr r3, [r7, #4] + 8000c94: 6998 ldr r0, [r3, #24] + 8000c96: 687b ldr r3, [r7, #4] + 8000c98: 881b ldrh r3, [r3, #0] + 8000c9a: 461a mov r2, r3 + 8000c9c: 687b ldr r3, [r7, #4] + 8000c9e: 885b ldrh r3, [r3, #2] + 8000ca0: fb02 f303 mul.w r3, r2, r3 + 8000ca4: 2b00 cmp r3, #0 + 8000ca6: da00 bge.n 8000caa <SHARPMEM_clear_display_buffer+0x20> + 8000ca8: 3307 adds r3, #7 + 8000caa: 10db asrs r3, r3, #3 + 8000cac: 461a mov r2, r3 + 8000cae: 21ff movs r1, #255 @ 0xff + 8000cb0: f003 feca bl 8004a48 <memset> +} + 8000cb4: bf00 nop + 8000cb6: 3708 adds r7, #8 + 8000cb8: 46bd mov sp, r7 + 8000cba: bd80 pop {r7, pc} + +08000cbc <LL_RCC_EnableRTC>: + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + 8000cbc: b480 push {r7} + 8000cbe: af00 add r7, sp, #0 + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); + 8000cc0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000cc4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8000cc8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8000ccc: f443 4300 orr.w r3, r3, #32768 @ 0x8000 + 8000cd0: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 8000cd4: bf00 nop + 8000cd6: 46bd mov sp, r7 + 8000cd8: f85d 7b04 ldr.w r7, [sp], #4 + 8000cdc: 4770 bx lr + +08000cde <LL_AHB2_GRP1_EnableClock>: +{ + 8000cde: b480 push {r7} + 8000ce0: b085 sub sp, #20 + 8000ce2: af00 add r7, sp, #0 + 8000ce4: 6078 str r0, [r7, #4] + SET_BIT(RCC->AHB2ENR, Periphs); + 8000ce6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000cea: 6cda ldr r2, [r3, #76] @ 0x4c + 8000cec: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8000cf0: 687b ldr r3, [r7, #4] + 8000cf2: 4313 orrs r3, r2 + 8000cf4: 64cb str r3, [r1, #76] @ 0x4c + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + 8000cf6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000cfa: 6cda ldr r2, [r3, #76] @ 0x4c + 8000cfc: 687b ldr r3, [r7, #4] + 8000cfe: 4013 ands r3, r2 + 8000d00: 60fb str r3, [r7, #12] + (void)tmpreg; + 8000d02: 68fb ldr r3, [r7, #12] +} + 8000d04: bf00 nop + 8000d06: 3714 adds r7, #20 + 8000d08: 46bd mov sp, r7 + 8000d0a: f85d 7b04 ldr.w r7, [sp], #4 + 8000d0e: 4770 bx lr + +08000d10 <LL_AHB3_GRP1_EnableClock>: + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @note (*) Not supported by all the devices + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + 8000d10: b480 push {r7} + 8000d12: b085 sub sp, #20 + 8000d14: af00 add r7, sp, #0 + 8000d16: 6078 str r0, [r7, #4] + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3ENR, Periphs); + 8000d18: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000d1c: 6d1a ldr r2, [r3, #80] @ 0x50 + 8000d1e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8000d22: 687b ldr r3, [r7, #4] + 8000d24: 4313 orrs r3, r2 + 8000d26: 650b str r3, [r1, #80] @ 0x50 + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); + 8000d28: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000d2c: 6d1a ldr r2, [r3, #80] @ 0x50 + 8000d2e: 687b ldr r3, [r7, #4] + 8000d30: 4013 ands r3, r2 + 8000d32: 60fb str r3, [r7, #12] + (void)tmpreg; + 8000d34: 68fb ldr r3, [r7, #12] +} + 8000d36: bf00 nop + 8000d38: 3714 adds r7, #20 + 8000d3a: 46bd mov sp, r7 + 8000d3c: f85d 7b04 ldr.w r7, [sp], #4 + 8000d40: 4770 bx lr + +08000d42 <LL_APB1_GRP1_EnableClock>: + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @note (*) Not supported by all the devices + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + 8000d42: b480 push {r7} + 8000d44: b085 sub sp, #20 + 8000d46: af00 add r7, sp, #0 + 8000d48: 6078 str r0, [r7, #4] + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR1, Periphs); + 8000d4a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000d4e: 6d9a ldr r2, [r3, #88] @ 0x58 + 8000d50: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8000d54: 687b ldr r3, [r7, #4] + 8000d56: 4313 orrs r3, r2 + 8000d58: 658b str r3, [r1, #88] @ 0x58 + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); + 8000d5a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000d5e: 6d9a ldr r2, [r3, #88] @ 0x58 + 8000d60: 687b ldr r3, [r7, #4] + 8000d62: 4013 ands r3, r2 + 8000d64: 60fb str r3, [r7, #12] + (void)tmpreg; + 8000d66: 68fb ldr r3, [r7, #12] +} + 8000d68: bf00 nop + 8000d6a: 3714 adds r7, #20 + 8000d6c: 46bd mov sp, r7 + 8000d6e: f85d 7b04 ldr.w r7, [sp], #4 + 8000d72: 4770 bx lr + +08000d74 <LL_APB2_GRP1_EnableClock>: + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @note (*) Not supported by all the devices + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + 8000d74: b480 push {r7} + 8000d76: b085 sub sp, #20 + 8000d78: af00 add r7, sp, #0 + 8000d7a: 6078 str r0, [r7, #4] + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + 8000d7c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000d80: 6e1a ldr r2, [r3, #96] @ 0x60 + 8000d82: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8000d86: 687b ldr r3, [r7, #4] + 8000d88: 4313 orrs r3, r2 + 8000d8a: 660b str r3, [r1, #96] @ 0x60 + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + 8000d8c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8000d90: 6e1a ldr r2, [r3, #96] @ 0x60 + 8000d92: 687b ldr r3, [r7, #4] + 8000d94: 4013 ands r3, r2 + 8000d96: 60fb str r3, [r7, #12] + (void)tmpreg; + 8000d98: 68fb ldr r3, [r7, #12] +} + 8000d9a: bf00 nop + 8000d9c: 3714 adds r7, #20 + 8000d9e: 46bd mov sp, r7 + 8000da0: f85d 7b04 ldr.w r7, [sp], #4 + 8000da4: 4770 bx lr + +08000da6 <HAL_MspInit>: +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 8000da6: b580 push {r7, lr} + 8000da8: af00 add r7, sp, #0 + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_HSEM_CLK_ENABLE(); + 8000daa: f44f 2000 mov.w r0, #524288 @ 0x80000 + 8000dae: f7ff ffaf bl 8000d10 <LL_AHB3_GRP1_EnableClock> + + /* System interrupt init*/ + + /* Peripheral interrupt init */ + /* HSEM_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(HSEM_IRQn, 0, 0); + 8000db2: 2200 movs r2, #0 + 8000db4: 2100 movs r1, #0 + 8000db6: 202e movs r0, #46 @ 0x2e + 8000db8: f000 fb8f bl 80014da <HAL_NVIC_SetPriority> + HAL_NVIC_EnableIRQ(HSEM_IRQn); + 8000dbc: 202e movs r0, #46 @ 0x2e + 8000dbe: f000 fba6 bl 800150e <HAL_NVIC_EnableIRQ> + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8000dc2: bf00 nop + 8000dc4: bd80 pop {r7, pc} + ... + +08000dc8 <HAL_I2C_MspInit>: + * This function configures the hardware resources used in this example + * @param hi2c: I2C handle pointer + * @retval None + */ +void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) +{ + 8000dc8: b580 push {r7, lr} + 8000dca: b09c sub sp, #112 @ 0x70 + 8000dcc: af00 add r7, sp, #0 + 8000dce: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000dd0: f107 035c add.w r3, r7, #92 @ 0x5c + 8000dd4: 2200 movs r2, #0 + 8000dd6: 601a str r2, [r3, #0] + 8000dd8: 605a str r2, [r3, #4] + 8000dda: 609a str r2, [r3, #8] + 8000ddc: 60da str r2, [r3, #12] + 8000dde: 611a str r2, [r3, #16] + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 8000de0: f107 030c add.w r3, r7, #12 + 8000de4: 2250 movs r2, #80 @ 0x50 + 8000de6: 2100 movs r1, #0 + 8000de8: 4618 mov r0, r3 + 8000dea: f003 fe2d bl 8004a48 <memset> + if(hi2c->Instance==I2C1) + 8000dee: 687b ldr r3, [r7, #4] + 8000df0: 681b ldr r3, [r3, #0] + 8000df2: 4a16 ldr r2, [pc, #88] @ (8000e4c <HAL_I2C_MspInit+0x84>) + 8000df4: 4293 cmp r3, r2 + 8000df6: d125 bne.n 8000e44 <HAL_I2C_MspInit+0x7c> + + /* USER CODE END I2C1_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C1; + 8000df8: 2304 movs r3, #4 + 8000dfa: 60fb str r3, [r7, #12] + PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1; + 8000dfc: f44f 3340 mov.w r3, #196608 @ 0x30000 + 8000e00: 62fb str r3, [r7, #44] @ 0x2c + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 8000e02: f107 030c add.w r3, r7, #12 + 8000e06: 4618 mov r0, r3 + 8000e08: f002 fac7 bl 800339a <HAL_RCCEx_PeriphCLKConfig> + 8000e0c: 4603 mov r3, r0 + 8000e0e: 2b00 cmp r3, #0 + 8000e10: d001 beq.n 8000e16 <HAL_I2C_MspInit+0x4e> + { + Error_Handler(); + 8000e12: f7ff fd11 bl 8000838 <Error_Handler> + } + + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8000e16: 2002 movs r0, #2 + 8000e18: f7ff ff61 bl 8000cde <LL_AHB2_GRP1_EnableClock> + /**I2C1 GPIO Configuration + PB6 ------> I2C1_SCL + PB7 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + 8000e1c: 23c0 movs r3, #192 @ 0xc0 + 8000e1e: 65fb str r3, [r7, #92] @ 0x5c + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 8000e20: 2312 movs r3, #18 + 8000e22: 663b str r3, [r7, #96] @ 0x60 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000e24: 2300 movs r3, #0 + 8000e26: 667b str r3, [r7, #100] @ 0x64 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8000e28: 2300 movs r3, #0 + 8000e2a: 66bb str r3, [r7, #104] @ 0x68 + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + 8000e2c: 2304 movs r3, #4 + 8000e2e: 66fb str r3, [r7, #108] @ 0x6c + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8000e30: f107 035c add.w r3, r7, #92 @ 0x5c + 8000e34: 4619 mov r1, r3 + 8000e36: 4806 ldr r0, [pc, #24] @ (8000e50 <HAL_I2C_MspInit+0x88>) + 8000e38: f000 fb84 bl 8001544 <HAL_GPIO_Init> + + /* Peripheral clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + 8000e3c: f44f 1000 mov.w r0, #2097152 @ 0x200000 + 8000e40: f7ff ff7f bl 8000d42 <LL_APB1_GRP1_EnableClock> + + /* USER CODE END I2C1_MspInit 1 */ + + } + +} + 8000e44: bf00 nop + 8000e46: 3770 adds r7, #112 @ 0x70 + 8000e48: 46bd mov sp, r7 + 8000e4a: bd80 pop {r7, pc} + 8000e4c: 40005400 .word 0x40005400 + 8000e50: 48000400 .word 0x48000400 + +08000e54 <HAL_IPCC_MspInit>: + * This function configures the hardware resources used in this example + * @param hipcc: IPCC handle pointer + * @retval None + */ +void HAL_IPCC_MspInit(IPCC_HandleTypeDef* hipcc) +{ + 8000e54: b580 push {r7, lr} + 8000e56: b082 sub sp, #8 + 8000e58: af00 add r7, sp, #0 + 8000e5a: 6078 str r0, [r7, #4] + if(hipcc->Instance==IPCC) + 8000e5c: 687b ldr r3, [r7, #4] + 8000e5e: 681b ldr r3, [r3, #0] + 8000e60: 4a0d ldr r2, [pc, #52] @ (8000e98 <HAL_IPCC_MspInit+0x44>) + 8000e62: 4293 cmp r3, r2 + 8000e64: d113 bne.n 8000e8e <HAL_IPCC_MspInit+0x3a> + { + /* USER CODE BEGIN IPCC_MspInit 0 */ + + /* USER CODE END IPCC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_IPCC_CLK_ENABLE(); + 8000e66: f44f 1080 mov.w r0, #1048576 @ 0x100000 + 8000e6a: f7ff ff51 bl 8000d10 <LL_AHB3_GRP1_EnableClock> + /* IPCC interrupt Init */ + HAL_NVIC_SetPriority(IPCC_C1_RX_IRQn, 0, 0); + 8000e6e: 2200 movs r2, #0 + 8000e70: 2100 movs r1, #0 + 8000e72: 202c movs r0, #44 @ 0x2c + 8000e74: f000 fb31 bl 80014da <HAL_NVIC_SetPriority> + HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn); + 8000e78: 202c movs r0, #44 @ 0x2c + 8000e7a: f000 fb48 bl 800150e <HAL_NVIC_EnableIRQ> + HAL_NVIC_SetPriority(IPCC_C1_TX_IRQn, 0, 0); + 8000e7e: 2200 movs r2, #0 + 8000e80: 2100 movs r1, #0 + 8000e82: 202d movs r0, #45 @ 0x2d + 8000e84: f000 fb29 bl 80014da <HAL_NVIC_SetPriority> + HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn); + 8000e88: 202d movs r0, #45 @ 0x2d + 8000e8a: f000 fb40 bl 800150e <HAL_NVIC_EnableIRQ> + + /* USER CODE END IPCC_MspInit 1 */ + + } + +} + 8000e8e: bf00 nop + 8000e90: 3708 adds r7, #8 + 8000e92: 46bd mov sp, r7 + 8000e94: bd80 pop {r7, pc} + 8000e96: bf00 nop + 8000e98: 58000c00 .word 0x58000c00 + +08000e9c <HAL_RTC_MspInit>: + * This function configures the hardware resources used in this example + * @param hrtc: RTC handle pointer + * @retval None + */ +void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) +{ + 8000e9c: b580 push {r7, lr} + 8000e9e: b096 sub sp, #88 @ 0x58 + 8000ea0: af00 add r7, sp, #0 + 8000ea2: 6078 str r0, [r7, #4] + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 8000ea4: f107 0308 add.w r3, r7, #8 + 8000ea8: 2250 movs r2, #80 @ 0x50 + 8000eaa: 2100 movs r1, #0 + 8000eac: 4618 mov r0, r3 + 8000eae: f003 fdcb bl 8004a48 <memset> + if(hrtc->Instance==RTC) + 8000eb2: 687b ldr r3, [r7, #4] + 8000eb4: 681b ldr r3, [r3, #0] + 8000eb6: 4a12 ldr r2, [pc, #72] @ (8000f00 <HAL_RTC_MspInit+0x64>) + 8000eb8: 4293 cmp r3, r2 + 8000eba: d11d bne.n 8000ef8 <HAL_RTC_MspInit+0x5c> + + /* USER CODE END RTC_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + 8000ebc: f44f 6300 mov.w r3, #2048 @ 0x800 + 8000ec0: 60bb str r3, [r7, #8] + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + 8000ec2: f44f 7380 mov.w r3, #256 @ 0x100 + 8000ec6: 64bb str r3, [r7, #72] @ 0x48 + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 8000ec8: f107 0308 add.w r3, r7, #8 + 8000ecc: 4618 mov r0, r3 + 8000ece: f002 fa64 bl 800339a <HAL_RCCEx_PeriphCLKConfig> + 8000ed2: 4603 mov r3, r0 + 8000ed4: 2b00 cmp r3, #0 + 8000ed6: d001 beq.n 8000edc <HAL_RTC_MspInit+0x40> + { + Error_Handler(); + 8000ed8: f7ff fcae bl 8000838 <Error_Handler> + } + + /* Peripheral clock enable */ + __HAL_RCC_RTC_ENABLE(); + 8000edc: f7ff feee bl 8000cbc <LL_RCC_EnableRTC> + __HAL_RCC_RTCAPB_CLK_ENABLE(); + 8000ee0: f44f 6080 mov.w r0, #1024 @ 0x400 + 8000ee4: f7ff ff2d bl 8000d42 <LL_APB1_GRP1_EnableClock> + /* RTC interrupt Init */ + HAL_NVIC_SetPriority(RTC_WKUP_IRQn, 0, 0); + 8000ee8: 2200 movs r2, #0 + 8000eea: 2100 movs r1, #0 + 8000eec: 2003 movs r0, #3 + 8000eee: f000 faf4 bl 80014da <HAL_NVIC_SetPriority> + HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn); + 8000ef2: 2003 movs r0, #3 + 8000ef4: f000 fb0b bl 800150e <HAL_NVIC_EnableIRQ> + + /* USER CODE END RTC_MspInit 1 */ + + } + +} + 8000ef8: bf00 nop + 8000efa: 3758 adds r7, #88 @ 0x58 + 8000efc: 46bd mov sp, r7 + 8000efe: bd80 pop {r7, pc} + 8000f00: 40002800 .word 0x40002800 + +08000f04 <HAL_SPI_MspInit>: + * This function configures the hardware resources used in this example + * @param hspi: SPI handle pointer + * @retval None + */ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + 8000f04: b580 push {r7, lr} + 8000f06: b088 sub sp, #32 + 8000f08: af00 add r7, sp, #0 + 8000f0a: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000f0c: f107 030c add.w r3, r7, #12 + 8000f10: 2200 movs r2, #0 + 8000f12: 601a str r2, [r3, #0] + 8000f14: 605a str r2, [r3, #4] + 8000f16: 609a str r2, [r3, #8] + 8000f18: 60da str r2, [r3, #12] + 8000f1a: 611a str r2, [r3, #16] + if(hspi->Instance==SPI1) + 8000f1c: 687b ldr r3, [r7, #4] + 8000f1e: 681b ldr r3, [r3, #0] + 8000f20: 4a0f ldr r2, [pc, #60] @ (8000f60 <HAL_SPI_MspInit+0x5c>) + 8000f22: 4293 cmp r3, r2 + 8000f24: d117 bne.n 8000f56 <HAL_SPI_MspInit+0x52> + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + 8000f26: f44f 5080 mov.w r0, #4096 @ 0x1000 + 8000f2a: f7ff ff23 bl 8000d74 <LL_APB2_GRP1_EnableClock> + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8000f2e: 2001 movs r0, #1 + 8000f30: f7ff fed5 bl 8000cde <LL_AHB2_GRP1_EnableClock> + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7; + 8000f34: 23a0 movs r3, #160 @ 0xa0 + 8000f36: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8000f38: 2302 movs r3, #2 + 8000f3a: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000f3c: 2300 movs r3, #0 + 8000f3e: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8000f40: 2300 movs r3, #0 + 8000f42: 61bb str r3, [r7, #24] + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + 8000f44: 2305 movs r3, #5 + 8000f46: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8000f48: f107 030c add.w r3, r7, #12 + 8000f4c: 4619 mov r1, r3 + 8000f4e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 8000f52: f000 faf7 bl 8001544 <HAL_GPIO_Init> + + /* USER CODE END SPI1_MspInit 1 */ + + } + +} + 8000f56: bf00 nop + 8000f58: 3720 adds r7, #32 + 8000f5a: 46bd mov sp, r7 + 8000f5c: bd80 pop {r7, pc} + 8000f5e: bf00 nop + 8000f60: 40013000 .word 0x40013000 + +08000f64 <NMI_Handler>: +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 8000f64: b480 push {r7} + 8000f66: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 8000f68: bf00 nop + 8000f6a: e7fd b.n 8000f68 <NMI_Handler+0x4> + +08000f6c <HardFault_Handler>: + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 8000f6c: b480 push {r7} + 8000f6e: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 8000f70: bf00 nop + 8000f72: e7fd b.n 8000f70 <HardFault_Handler+0x4> + +08000f74 <MemManage_Handler>: + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 8000f74: b480 push {r7} + 8000f76: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 8000f78: bf00 nop + 8000f7a: e7fd b.n 8000f78 <MemManage_Handler+0x4> + +08000f7c <BusFault_Handler>: + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 8000f7c: b480 push {r7} + 8000f7e: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 8000f80: bf00 nop + 8000f82: e7fd b.n 8000f80 <BusFault_Handler+0x4> + +08000f84 <UsageFault_Handler>: + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 8000f84: b480 push {r7} + 8000f86: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 8000f88: bf00 nop + 8000f8a: e7fd b.n 8000f88 <UsageFault_Handler+0x4> + +08000f8c <SVC_Handler>: + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 8000f8c: b480 push {r7} + 8000f8e: af00 add r7, sp, #0 + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + 8000f90: bf00 nop + 8000f92: 46bd mov sp, r7 + 8000f94: f85d 7b04 ldr.w r7, [sp], #4 + 8000f98: 4770 bx lr + +08000f9a <DebugMon_Handler>: + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 8000f9a: b480 push {r7} + 8000f9c: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 8000f9e: bf00 nop + 8000fa0: 46bd mov sp, r7 + 8000fa2: f85d 7b04 ldr.w r7, [sp], #4 + 8000fa6: 4770 bx lr + +08000fa8 <PendSV_Handler>: + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 8000fa8: b480 push {r7} + 8000faa: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8000fac: bf00 nop + 8000fae: 46bd mov sp, r7 + 8000fb0: f85d 7b04 ldr.w r7, [sp], #4 + 8000fb4: 4770 bx lr + +08000fb6 <SysTick_Handler>: + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 8000fb6: b580 push {r7, lr} + 8000fb8: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 8000fba: f000 f943 bl 8001244 <HAL_IncTick> + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8000fbe: bf00 nop + 8000fc0: bd80 pop {r7, pc} + ... + +08000fc4 <RTC_WKUP_IRQHandler>: + +/** + * @brief This function handles RTC wake-up interrupt through EXTI line 19. + */ +void RTC_WKUP_IRQHandler(void) +{ + 8000fc4: b580 push {r7, lr} + 8000fc6: af00 add r7, sp, #0 + /* USER CODE BEGIN RTC_WKUP_IRQn 0 */ + + /* USER CODE END RTC_WKUP_IRQn 0 */ + HAL_RTCEx_WakeUpTimerIRQHandler(&hrtc); + 8000fc8: 4802 ldr r0, [pc, #8] @ (8000fd4 <RTC_WKUP_IRQHandler+0x10>) + 8000fca: f003 f8b7 bl 800413c <HAL_RTCEx_WakeUpTimerIRQHandler> + /* USER CODE BEGIN RTC_WKUP_IRQn 1 */ + + /* USER CODE END RTC_WKUP_IRQn 1 */ +} + 8000fce: bf00 nop + 8000fd0: bd80 pop {r7, pc} + 8000fd2: bf00 nop + 8000fd4: 20000818 .word 0x20000818 + +08000fd8 <IPCC_C1_RX_IRQHandler>: + +/** + * @brief This function handles IPCC RX occupied interrupt. + */ +void IPCC_C1_RX_IRQHandler(void) +{ + 8000fd8: b580 push {r7, lr} + 8000fda: af00 add r7, sp, #0 + /* USER CODE BEGIN IPCC_C1_RX_IRQn 0 */ + + /* USER CODE END IPCC_C1_RX_IRQn 0 */ + HAL_IPCC_RX_IRQHandler(&hipcc); + 8000fdc: 4802 ldr r0, [pc, #8] @ (8000fe8 <IPCC_C1_RX_IRQHandler+0x10>) + 8000fde: f000 fe0f bl 8001c00 <HAL_IPCC_RX_IRQHandler> + /* USER CODE BEGIN IPCC_C1_RX_IRQn 1 */ + + /* USER CODE END IPCC_C1_RX_IRQn 1 */ +} + 8000fe2: bf00 nop + 8000fe4: bd80 pop {r7, pc} + 8000fe6: bf00 nop + 8000fe8: 200007dc .word 0x200007dc + +08000fec <IPCC_C1_TX_IRQHandler>: + +/** + * @brief This function handles IPCC TX free interrupt. + */ +void IPCC_C1_TX_IRQHandler(void) +{ + 8000fec: b580 push {r7, lr} + 8000fee: af00 add r7, sp, #0 + /* USER CODE BEGIN IPCC_C1_TX_IRQn 0 */ + + /* USER CODE END IPCC_C1_TX_IRQn 0 */ + HAL_IPCC_TX_IRQHandler(&hipcc); + 8000ff0: 4802 ldr r0, [pc, #8] @ (8000ffc <IPCC_C1_TX_IRQHandler+0x10>) + 8000ff2: f000 fdb7 bl 8001b64 <HAL_IPCC_TX_IRQHandler> + /* USER CODE BEGIN IPCC_C1_TX_IRQn 1 */ + + /* USER CODE END IPCC_C1_TX_IRQn 1 */ +} + 8000ff6: bf00 nop + 8000ff8: bd80 pop {r7, pc} + 8000ffa: bf00 nop + 8000ffc: 200007dc .word 0x200007dc + +08001000 <HSEM_IRQHandler>: + +/** + * @brief This function handles HSEM global interrupt. + */ +void HSEM_IRQHandler(void) +{ + 8001000: b580 push {r7, lr} + 8001002: af00 add r7, sp, #0 + /* USER CODE BEGIN HSEM_IRQn 0 */ + + /* USER CODE END HSEM_IRQn 0 */ + HAL_HSEM_IRQHandler(); + 8001004: f000 fc26 bl 8001854 <HAL_HSEM_IRQHandler> + /* USER CODE BEGIN HSEM_IRQn 1 */ + + /* USER CODE END HSEM_IRQn 1 */ +} + 8001008: bf00 nop + 800100a: bd80 pop {r7, pc} + +0800100c <_sbrk>: + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + 800100c: b580 push {r7, lr} + 800100e: b086 sub sp, #24 + 8001010: af00 add r7, sp, #0 + 8001012: 6078 str r0, [r7, #4] + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + 8001014: 4a14 ldr r2, [pc, #80] @ (8001068 <_sbrk+0x5c>) + 8001016: 4b15 ldr r3, [pc, #84] @ (800106c <_sbrk+0x60>) + 8001018: 1ad3 subs r3, r2, r3 + 800101a: 617b str r3, [r7, #20] + const uint8_t *max_heap = (uint8_t *)stack_limit; + 800101c: 697b ldr r3, [r7, #20] + 800101e: 613b str r3, [r7, #16] + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + 8001020: 4b13 ldr r3, [pc, #76] @ (8001070 <_sbrk+0x64>) + 8001022: 681b ldr r3, [r3, #0] + 8001024: 2b00 cmp r3, #0 + 8001026: d102 bne.n 800102e <_sbrk+0x22> + { + __sbrk_heap_end = &_end; + 8001028: 4b11 ldr r3, [pc, #68] @ (8001070 <_sbrk+0x64>) + 800102a: 4a12 ldr r2, [pc, #72] @ (8001074 <_sbrk+0x68>) + 800102c: 601a str r2, [r3, #0] + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + 800102e: 4b10 ldr r3, [pc, #64] @ (8001070 <_sbrk+0x64>) + 8001030: 681a ldr r2, [r3, #0] + 8001032: 687b ldr r3, [r7, #4] + 8001034: 4413 add r3, r2 + 8001036: 693a ldr r2, [r7, #16] + 8001038: 429a cmp r2, r3 + 800103a: d207 bcs.n 800104c <_sbrk+0x40> + { + errno = ENOMEM; + 800103c: f003 fd1c bl 8004a78 <__errno> + 8001040: 4603 mov r3, r0 + 8001042: 220c movs r2, #12 + 8001044: 601a str r2, [r3, #0] + return (void *)-1; + 8001046: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800104a: e009 b.n 8001060 <_sbrk+0x54> + } + + prev_heap_end = __sbrk_heap_end; + 800104c: 4b08 ldr r3, [pc, #32] @ (8001070 <_sbrk+0x64>) + 800104e: 681b ldr r3, [r3, #0] + 8001050: 60fb str r3, [r7, #12] + __sbrk_heap_end += incr; + 8001052: 4b07 ldr r3, [pc, #28] @ (8001070 <_sbrk+0x64>) + 8001054: 681a ldr r2, [r3, #0] + 8001056: 687b ldr r3, [r7, #4] + 8001058: 4413 add r3, r2 + 800105a: 4a05 ldr r2, [pc, #20] @ (8001070 <_sbrk+0x64>) + 800105c: 6013 str r3, [r2, #0] + + return (void *)prev_heap_end; + 800105e: 68fb ldr r3, [r7, #12] +} + 8001060: 4618 mov r0, r3 + 8001062: 3718 adds r7, #24 + 8001064: 46bd mov sp, r7 + 8001066: bd80 pop {r7, pc} + 8001068: 20030000 .word 0x20030000 + 800106c: 00000400 .word 0x00000400 + 8001070: 200008a0 .word 0x200008a0 + 8001074: 200009f0 .word 0x200009f0 + +08001078 <SystemInit>: + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit(void) +{ + 8001078: b480 push {r7} + 800107a: af00 add r7, sp, #0 + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; +#endif /* USER_VECT_TAB_ADDRESS */ + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10UL * 2UL)) | (3UL << (11UL * 2UL))); /* set CP10 and CP11 Full Access */ + 800107c: 4b24 ldr r3, [pc, #144] @ (8001110 <SystemInit+0x98>) + 800107e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8001082: 4a23 ldr r2, [pc, #140] @ (8001110 <SystemInit+0x98>) + 8001084: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 + 8001088: f8c2 3088 str.w r3, [r2, #136] @ 0x88 +#endif /* FPU */ + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC->CR |= RCC_CR_MSION; + 800108c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001090: 681b ldr r3, [r3, #0] + 8001092: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8001096: f043 0301 orr.w r3, r3, #1 + 800109a: 6013 str r3, [r2, #0] + + /* Reset CFGR register */ + RCC->CFGR = 0x00070000U; + 800109c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80010a0: f44f 22e0 mov.w r2, #458752 @ 0x70000 + 80010a4: 609a str r2, [r3, #8] + + /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */ + RCC->CR &= (uint32_t)0xFAF6FEFBU; + 80010a6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80010aa: 681a ldr r2, [r3, #0] + 80010ac: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80010b0: 4b18 ldr r3, [pc, #96] @ (8001114 <SystemInit+0x9c>) + 80010b2: 4013 ands r3, r2 + 80010b4: 600b str r3, [r1, #0] + + /*!< Reset LSI1 and LSI2 bits */ + RCC->CSR &= (uint32_t)0xFFFFFFFAU; + 80010b6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80010ba: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 80010be: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80010c2: f023 0305 bic.w r3, r3, #5 + 80010c6: f8c2 3094 str.w r3, [r2, #148] @ 0x94 + + /*!< Reset HSI48ON bit */ + RCC->CRRCR &= (uint32_t)0xFFFFFFFEU; + 80010ca: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80010ce: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 + 80010d2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80010d6: f023 0301 bic.w r3, r3, #1 + 80010da: f8c2 3098 str.w r3, [r2, #152] @ 0x98 + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x22041000U; + 80010de: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80010e2: 4a0d ldr r2, [pc, #52] @ (8001118 <SystemInit+0xa0>) + 80010e4: 60da str r2, [r3, #12] + +#if defined(STM32WB55xx) || defined(STM32WB5Mxx) + /* Reset PLLSAI1CFGR register */ + RCC->PLLSAI1CFGR = 0x22041000U; + 80010e6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80010ea: 4a0b ldr r2, [pc, #44] @ (8001118 <SystemInit+0xa0>) + 80010ec: 611a str r2, [r3, #16] +#endif /* STM32WB55xx || STM32WB5Mxx */ + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + 80010ee: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80010f2: 681b ldr r3, [r3, #0] + 80010f4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80010f8: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 80010fc: 6013 str r3, [r2, #0] + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + 80010fe: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001102: 2200 movs r2, #0 + 8001104: 619a str r2, [r3, #24] +} + 8001106: bf00 nop + 8001108: 46bd mov sp, r7 + 800110a: f85d 7b04 ldr.w r7, [sp], #4 + 800110e: 4770 bx lr + 8001110: e000ed00 .word 0xe000ed00 + 8001114: faf6fefb .word 0xfaf6fefb + 8001118: 22041000 .word 0x22041000 + +0800111c <CopyDataInit>: + bl LoopCopyDataInit +.endm + +.section .text.data_initializers +CopyDataInit: + ldr r4, [r2, r3] + 800111c: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 800111e: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 8001120: 3304 adds r3, #4 + +08001122 <LoopCopyDataInit>: + +LoopCopyDataInit: + adds r4, r0, r3 + 8001122: 18c4 adds r4, r0, r3 + cmp r4, r1 + 8001124: 428c cmp r4, r1 + bcc CopyDataInit + 8001126: d3f9 bcc.n 800111c <CopyDataInit> + bx lr + 8001128: 4770 bx lr + +0800112a <FillZerobss>: + +FillZerobss: + str r3, [r0] + 800112a: 6003 str r3, [r0, #0] + adds r0, r0, #4 + 800112c: 3004 adds r0, #4 + +0800112e <LoopFillZerobss>: + +LoopFillZerobss: + cmp r0, r1 + 800112e: 4288 cmp r0, r1 + bcc FillZerobss + 8001130: d3fb bcc.n 800112a <FillZerobss> + bx lr + 8001132: 4770 bx lr + +08001134 <Reset_Handler>: + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + 8001134: 480c ldr r0, [pc, #48] @ (8001168 <LoopForever+0x2>) + mov sp, r0 /* set stack pointer */ + 8001136: 4685 mov sp, r0 +/* Call the clock system initialization function.*/ + bl SystemInit + 8001138: f7ff ff9e bl 8001078 <SystemInit> + +/* Copy the data segment initializers from flash to SRAM */ + INIT_DATA _sdata, _edata, _sidata + 800113c: 480b ldr r0, [pc, #44] @ (800116c <LoopForever+0x6>) + 800113e: 490c ldr r1, [pc, #48] @ (8001170 <LoopForever+0xa>) + 8001140: 4a0c ldr r2, [pc, #48] @ (8001174 <LoopForever+0xe>) + 8001142: 2300 movs r3, #0 + 8001144: f7ff ffed bl 8001122 <LoopCopyDataInit> + INIT_DATA _sMB_MEM2, _eMB_MEM2, _siMB_MEM2 + 8001148: 480b ldr r0, [pc, #44] @ (8001178 <LoopForever+0x12>) + 800114a: 490c ldr r1, [pc, #48] @ (800117c <LoopForever+0x16>) + 800114c: 4a0c ldr r2, [pc, #48] @ (8001180 <LoopForever+0x1a>) + 800114e: 2300 movs r3, #0 + 8001150: f7ff ffe7 bl 8001122 <LoopCopyDataInit> + +/* Zero fill the bss segments. */ + INIT_BSS _sbss, _ebss + 8001154: 480b ldr r0, [pc, #44] @ (8001184 <LoopForever+0x1e>) + 8001156: 490c ldr r1, [pc, #48] @ (8001188 <LoopForever+0x22>) + 8001158: 2300 movs r3, #0 + 800115a: f7ff ffe8 bl 800112e <LoopFillZerobss> + +/* Call static constructors */ + bl __libc_init_array + 800115e: f003 fc91 bl 8004a84 <__libc_init_array> +/* Call the application s entry point.*/ + bl main + 8001162: f7ff f8db bl 800031c <main> + +08001166 <LoopForever>: + +LoopForever: + b LoopForever + 8001166: e7fe b.n 8001166 <LoopForever> + ldr r0, =_estack + 8001168: 20030000 .word 0x20030000 + INIT_DATA _sdata, _edata, _sidata + 800116c: 20000008 .word 0x20000008 + 8001170: 20000724 .word 0x20000724 + 8001174: 080052fc .word 0x080052fc + INIT_DATA _sMB_MEM2, _eMB_MEM2, _siMB_MEM2 + 8001178: 20030000 .word 0x20030000 + 800117c: 20030000 .word 0x20030000 + 8001180: 08005a18 .word 0x08005a18 + INIT_BSS _sbss, _ebss + 8001184: 20000724 .word 0x20000724 + 8001188: 200009f0 .word 0x200009f0 + +0800118c <ADC1_IRQHandler>: + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 800118c: e7fe b.n 800118c <ADC1_IRQHandler> + ... + +08001190 <HAL_Init>: + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8001190: b580 push {r7, lr} + 8001192: b082 sub sp, #8 + 8001194: af00 add r7, sp, #0 + HAL_StatusTypeDef status = HAL_OK; + 8001196: 2300 movs r3, #0 + 8001198: 71fb strb r3, [r7, #7] +#if (DATA_CACHE_ENABLE == 0U) + __HAL_FLASH_DATA_CACHE_DISABLE(); +#endif /* DATA_CACHE_ENABLE */ + +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); + 800119a: 4b0c ldr r3, [pc, #48] @ (80011cc <HAL_Init+0x3c>) + 800119c: 681b ldr r3, [r3, #0] + 800119e: 4a0b ldr r2, [pc, #44] @ (80011cc <HAL_Init+0x3c>) + 80011a0: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80011a4: 6013 str r3, [r2, #0] +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 80011a6: 2003 movs r0, #3 + 80011a8: f000 f98c bl 80014c4 <HAL_NVIC_SetPriorityGrouping> + + /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 80011ac: 200f movs r0, #15 + 80011ae: f000 f80f bl 80011d0 <HAL_InitTick> + 80011b2: 4603 mov r3, r0 + 80011b4: 2b00 cmp r3, #0 + 80011b6: d002 beq.n 80011be <HAL_Init+0x2e> + { + status = HAL_ERROR; + 80011b8: 2301 movs r3, #1 + 80011ba: 71fb strb r3, [r7, #7] + 80011bc: e001 b.n 80011c2 <HAL_Init+0x32> + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + 80011be: f7ff fdf2 bl 8000da6 <HAL_MspInit> + } + + /* Return function status */ + return status; + 80011c2: 79fb ldrb r3, [r7, #7] +} + 80011c4: 4618 mov r0, r3 + 80011c6: 3708 adds r7, #8 + 80011c8: 46bd mov sp, r7 + 80011ca: bd80 pop {r7, pc} + 80011cc: 58004000 .word 0x58004000 + +080011d0 <HAL_InitTick>: + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 80011d0: b580 push {r7, lr} + 80011d2: b084 sub sp, #16 + 80011d4: af00 add r7, sp, #0 + 80011d6: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 80011d8: 2300 movs r3, #0 + 80011da: 73fb strb r3, [r7, #15] + + if ((uint32_t)uwTickFreq != 0U) + 80011dc: 4b17 ldr r3, [pc, #92] @ (800123c <HAL_InitTick+0x6c>) + 80011de: 781b ldrb r3, [r3, #0] + 80011e0: 2b00 cmp r3, #0 + 80011e2: d024 beq.n 800122e <HAL_InitTick+0x5e> + { + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / (1000U / (uint32_t)uwTickFreq)) == 0U) + 80011e4: f001 fe74 bl 8002ed0 <HAL_RCC_GetHCLKFreq> + 80011e8: 4602 mov r2, r0 + 80011ea: 4b14 ldr r3, [pc, #80] @ (800123c <HAL_InitTick+0x6c>) + 80011ec: 781b ldrb r3, [r3, #0] + 80011ee: 4619 mov r1, r3 + 80011f0: f44f 737a mov.w r3, #1000 @ 0x3e8 + 80011f4: fbb3 f3f1 udiv r3, r3, r1 + 80011f8: fbb2 f3f3 udiv r3, r2, r3 + 80011fc: 4618 mov r0, r3 + 80011fe: f000 f994 bl 800152a <HAL_SYSTICK_Config> + 8001202: 4603 mov r3, r0 + 8001204: 2b00 cmp r3, #0 + 8001206: d10f bne.n 8001228 <HAL_InitTick+0x58> + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 8001208: 687b ldr r3, [r7, #4] + 800120a: 2b0f cmp r3, #15 + 800120c: d809 bhi.n 8001222 <HAL_InitTick+0x52> + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 800120e: 2200 movs r2, #0 + 8001210: 6879 ldr r1, [r7, #4] + 8001212: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8001216: f000 f960 bl 80014da <HAL_NVIC_SetPriority> + uwTickPrio = TickPriority; + 800121a: 4a09 ldr r2, [pc, #36] @ (8001240 <HAL_InitTick+0x70>) + 800121c: 687b ldr r3, [r7, #4] + 800121e: 6013 str r3, [r2, #0] + 8001220: e007 b.n 8001232 <HAL_InitTick+0x62> + } + else + { + status = HAL_ERROR; + 8001222: 2301 movs r3, #1 + 8001224: 73fb strb r3, [r7, #15] + 8001226: e004 b.n 8001232 <HAL_InitTick+0x62> + } + } + else + { + status = HAL_ERROR; + 8001228: 2301 movs r3, #1 + 800122a: 73fb strb r3, [r7, #15] + 800122c: e001 b.n 8001232 <HAL_InitTick+0x62> + } + } + else + { + status = HAL_ERROR; + 800122e: 2301 movs r3, #1 + 8001230: 73fb strb r3, [r7, #15] + } + + /* Return function status */ + return status; + 8001232: 7bfb ldrb r3, [r7, #15] +} + 8001234: 4618 mov r0, r3 + 8001236: 3710 adds r7, #16 + 8001238: 46bd mov sp, r7 + 800123a: bd80 pop {r7, pc} + 800123c: 200006d0 .word 0x200006d0 + 8001240: 200006cc .word 0x200006cc + +08001244 <HAL_IncTick>: + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 8001244: b480 push {r7} + 8001246: af00 add r7, sp, #0 + uwTick += (uint32_t)uwTickFreq; + 8001248: 4b06 ldr r3, [pc, #24] @ (8001264 <HAL_IncTick+0x20>) + 800124a: 781b ldrb r3, [r3, #0] + 800124c: 461a mov r2, r3 + 800124e: 4b06 ldr r3, [pc, #24] @ (8001268 <HAL_IncTick+0x24>) + 8001250: 681b ldr r3, [r3, #0] + 8001252: 4413 add r3, r2 + 8001254: 4a04 ldr r2, [pc, #16] @ (8001268 <HAL_IncTick+0x24>) + 8001256: 6013 str r3, [r2, #0] +} + 8001258: bf00 nop + 800125a: 46bd mov sp, r7 + 800125c: f85d 7b04 ldr.w r7, [sp], #4 + 8001260: 4770 bx lr + 8001262: bf00 nop + 8001264: 200006d0 .word 0x200006d0 + 8001268: 200008a4 .word 0x200008a4 + +0800126c <HAL_GetTick>: + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 800126c: b480 push {r7} + 800126e: af00 add r7, sp, #0 + return uwTick; + 8001270: 4b03 ldr r3, [pc, #12] @ (8001280 <HAL_GetTick+0x14>) + 8001272: 681b ldr r3, [r3, #0] +} + 8001274: 4618 mov r0, r3 + 8001276: 46bd mov sp, r7 + 8001278: f85d 7b04 ldr.w r7, [sp], #4 + 800127c: 4770 bx lr + 800127e: bf00 nop + 8001280: 200008a4 .word 0x200008a4 + +08001284 <HAL_GetTickPrio>: +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + 8001284: b480 push {r7} + 8001286: af00 add r7, sp, #0 + return uwTickPrio; + 8001288: 4b03 ldr r3, [pc, #12] @ (8001298 <HAL_GetTickPrio+0x14>) + 800128a: 681b ldr r3, [r3, #0] +} + 800128c: 4618 mov r0, r3 + 800128e: 46bd mov sp, r7 + 8001290: f85d 7b04 ldr.w r7, [sp], #4 + 8001294: 4770 bx lr + 8001296: bf00 nop + 8001298: 200006cc .word 0x200006cc + +0800129c <HAL_Delay>: + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + 800129c: b580 push {r7, lr} + 800129e: b084 sub sp, #16 + 80012a0: af00 add r7, sp, #0 + 80012a2: 6078 str r0, [r7, #4] + uint32_t tickstart = HAL_GetTick(); + 80012a4: f7ff ffe2 bl 800126c <HAL_GetTick> + 80012a8: 60b8 str r0, [r7, #8] + uint32_t wait = Delay; + 80012aa: 687b ldr r3, [r7, #4] + 80012ac: 60fb str r3, [r7, #12] + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + 80012ae: 68fb ldr r3, [r7, #12] + 80012b0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80012b4: d005 beq.n 80012c2 <HAL_Delay+0x26> + { + wait += (uint32_t)(uwTickFreq); + 80012b6: 4b0a ldr r3, [pc, #40] @ (80012e0 <HAL_Delay+0x44>) + 80012b8: 781b ldrb r3, [r3, #0] + 80012ba: 461a mov r2, r3 + 80012bc: 68fb ldr r3, [r7, #12] + 80012be: 4413 add r3, r2 + 80012c0: 60fb str r3, [r7, #12] + } + + while ((HAL_GetTick() - tickstart) < wait) + 80012c2: bf00 nop + 80012c4: f7ff ffd2 bl 800126c <HAL_GetTick> + 80012c8: 4602 mov r2, r0 + 80012ca: 68bb ldr r3, [r7, #8] + 80012cc: 1ad3 subs r3, r2, r3 + 80012ce: 68fa ldr r2, [r7, #12] + 80012d0: 429a cmp r2, r3 + 80012d2: d8f7 bhi.n 80012c4 <HAL_Delay+0x28> + { + } +} + 80012d4: bf00 nop + 80012d6: bf00 nop + 80012d8: 3710 adds r7, #16 + 80012da: 46bd mov sp, r7 + 80012dc: bd80 pop {r7, pc} + 80012de: bf00 nop + 80012e0: 200006d0 .word 0x200006d0 + +080012e4 <HAL_SuspendTick>: + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + 80012e4: b480 push {r7} + 80012e6: af00 add r7, sp, #0 + /* Disable SysTick Interrupt */ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); + 80012e8: 4b05 ldr r3, [pc, #20] @ (8001300 <HAL_SuspendTick+0x1c>) + 80012ea: 681b ldr r3, [r3, #0] + 80012ec: 4a04 ldr r2, [pc, #16] @ (8001300 <HAL_SuspendTick+0x1c>) + 80012ee: f023 0302 bic.w r3, r3, #2 + 80012f2: 6013 str r3, [r2, #0] +} + 80012f4: bf00 nop + 80012f6: 46bd mov sp, r7 + 80012f8: f85d 7b04 ldr.w r7, [sp], #4 + 80012fc: 4770 bx lr + 80012fe: bf00 nop + 8001300: e000e010 .word 0xe000e010 + +08001304 <HAL_ResumeTick>: + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + 8001304: b480 push {r7} + 8001306: af00 add r7, sp, #0 + /* Enable SysTick Interrupt */ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); + 8001308: 4b05 ldr r3, [pc, #20] @ (8001320 <HAL_ResumeTick+0x1c>) + 800130a: 681b ldr r3, [r3, #0] + 800130c: 4a04 ldr r2, [pc, #16] @ (8001320 <HAL_ResumeTick+0x1c>) + 800130e: f043 0302 orr.w r3, r3, #2 + 8001312: 6013 str r3, [r2, #0] +} + 8001314: bf00 nop + 8001316: 46bd mov sp, r7 + 8001318: f85d 7b04 ldr.w r7, [sp], #4 + 800131c: 4770 bx lr + 800131e: bf00 nop + 8001320: e000e010 .word 0xe000e010 + +08001324 <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8001324: b480 push {r7} + 8001326: b085 sub sp, #20 + 8001328: af00 add r7, sp, #0 + 800132a: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 800132c: 687b ldr r3, [r7, #4] + 800132e: f003 0307 and.w r3, r3, #7 + 8001332: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 8001334: 4b0c ldr r3, [pc, #48] @ (8001368 <__NVIC_SetPriorityGrouping+0x44>) + 8001336: 68db ldr r3, [r3, #12] + 8001338: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 800133a: 68ba ldr r2, [r7, #8] + 800133c: f64f 03ff movw r3, #63743 @ 0xf8ff + 8001340: 4013 ands r3, r2 + 8001342: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 8001344: 68fb ldr r3, [r7, #12] + 8001346: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 8001348: 68bb ldr r3, [r7, #8] + 800134a: 4313 orrs r3, r2 + reg_value = (reg_value | + 800134c: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 8001350: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8001354: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 8001356: 4a04 ldr r2, [pc, #16] @ (8001368 <__NVIC_SetPriorityGrouping+0x44>) + 8001358: 68bb ldr r3, [r7, #8] + 800135a: 60d3 str r3, [r2, #12] +} + 800135c: bf00 nop + 800135e: 3714 adds r7, #20 + 8001360: 46bd mov sp, r7 + 8001362: f85d 7b04 ldr.w r7, [sp], #4 + 8001366: 4770 bx lr + 8001368: e000ed00 .word 0xe000ed00 + +0800136c <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 800136c: b480 push {r7} + 800136e: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8001370: 4b04 ldr r3, [pc, #16] @ (8001384 <__NVIC_GetPriorityGrouping+0x18>) + 8001372: 68db ldr r3, [r3, #12] + 8001374: 0a1b lsrs r3, r3, #8 + 8001376: f003 0307 and.w r3, r3, #7 +} + 800137a: 4618 mov r0, r3 + 800137c: 46bd mov sp, r7 + 800137e: f85d 7b04 ldr.w r7, [sp], #4 + 8001382: 4770 bx lr + 8001384: e000ed00 .word 0xe000ed00 + +08001388 <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8001388: b480 push {r7} + 800138a: b083 sub sp, #12 + 800138c: af00 add r7, sp, #0 + 800138e: 4603 mov r3, r0 + 8001390: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8001392: f997 3007 ldrsb.w r3, [r7, #7] + 8001396: 2b00 cmp r3, #0 + 8001398: db0b blt.n 80013b2 <__NVIC_EnableIRQ+0x2a> + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 800139a: 79fb ldrb r3, [r7, #7] + 800139c: f003 021f and.w r2, r3, #31 + 80013a0: 4907 ldr r1, [pc, #28] @ (80013c0 <__NVIC_EnableIRQ+0x38>) + 80013a2: f997 3007 ldrsb.w r3, [r7, #7] + 80013a6: 095b lsrs r3, r3, #5 + 80013a8: 2001 movs r0, #1 + 80013aa: fa00 f202 lsl.w r2, r0, r2 + 80013ae: f841 2023 str.w r2, [r1, r3, lsl #2] + __COMPILER_BARRIER(); + } +} + 80013b2: bf00 nop + 80013b4: 370c adds r7, #12 + 80013b6: 46bd mov sp, r7 + 80013b8: f85d 7b04 ldr.w r7, [sp], #4 + 80013bc: 4770 bx lr + 80013be: bf00 nop + 80013c0: e000e100 .word 0xe000e100 + +080013c4 <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 80013c4: b480 push {r7} + 80013c6: b083 sub sp, #12 + 80013c8: af00 add r7, sp, #0 + 80013ca: 4603 mov r3, r0 + 80013cc: 6039 str r1, [r7, #0] + 80013ce: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 80013d0: f997 3007 ldrsb.w r3, [r7, #7] + 80013d4: 2b00 cmp r3, #0 + 80013d6: db0a blt.n 80013ee <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 80013d8: 683b ldr r3, [r7, #0] + 80013da: b2da uxtb r2, r3 + 80013dc: 490c ldr r1, [pc, #48] @ (8001410 <__NVIC_SetPriority+0x4c>) + 80013de: f997 3007 ldrsb.w r3, [r7, #7] + 80013e2: 0112 lsls r2, r2, #4 + 80013e4: b2d2 uxtb r2, r2 + 80013e6: 440b add r3, r1 + 80013e8: f883 2300 strb.w r2, [r3, #768] @ 0x300 + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 80013ec: e00a b.n 8001404 <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 80013ee: 683b ldr r3, [r7, #0] + 80013f0: b2da uxtb r2, r3 + 80013f2: 4908 ldr r1, [pc, #32] @ (8001414 <__NVIC_SetPriority+0x50>) + 80013f4: 79fb ldrb r3, [r7, #7] + 80013f6: f003 030f and.w r3, r3, #15 + 80013fa: 3b04 subs r3, #4 + 80013fc: 0112 lsls r2, r2, #4 + 80013fe: b2d2 uxtb r2, r2 + 8001400: 440b add r3, r1 + 8001402: 761a strb r2, [r3, #24] +} + 8001404: bf00 nop + 8001406: 370c adds r7, #12 + 8001408: 46bd mov sp, r7 + 800140a: f85d 7b04 ldr.w r7, [sp], #4 + 800140e: 4770 bx lr + 8001410: e000e100 .word 0xe000e100 + 8001414: e000ed00 .word 0xe000ed00 + +08001418 <NVIC_EncodePriority>: + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8001418: b480 push {r7} + 800141a: b089 sub sp, #36 @ 0x24 + 800141c: af00 add r7, sp, #0 + 800141e: 60f8 str r0, [r7, #12] + 8001420: 60b9 str r1, [r7, #8] + 8001422: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8001424: 68fb ldr r3, [r7, #12] + 8001426: f003 0307 and.w r3, r3, #7 + 800142a: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 800142c: 69fb ldr r3, [r7, #28] + 800142e: f1c3 0307 rsb r3, r3, #7 + 8001432: 2b04 cmp r3, #4 + 8001434: bf28 it cs + 8001436: 2304 movcs r3, #4 + 8001438: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 800143a: 69fb ldr r3, [r7, #28] + 800143c: 3304 adds r3, #4 + 800143e: 2b06 cmp r3, #6 + 8001440: d902 bls.n 8001448 <NVIC_EncodePriority+0x30> + 8001442: 69fb ldr r3, [r7, #28] + 8001444: 3b03 subs r3, #3 + 8001446: e000 b.n 800144a <NVIC_EncodePriority+0x32> + 8001448: 2300 movs r3, #0 + 800144a: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 800144c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8001450: 69bb ldr r3, [r7, #24] + 8001452: fa02 f303 lsl.w r3, r2, r3 + 8001456: 43da mvns r2, r3 + 8001458: 68bb ldr r3, [r7, #8] + 800145a: 401a ands r2, r3 + 800145c: 697b ldr r3, [r7, #20] + 800145e: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8001460: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 8001464: 697b ldr r3, [r7, #20] + 8001466: fa01 f303 lsl.w r3, r1, r3 + 800146a: 43d9 mvns r1, r3 + 800146c: 687b ldr r3, [r7, #4] + 800146e: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8001470: 4313 orrs r3, r2 + ); +} + 8001472: 4618 mov r0, r3 + 8001474: 3724 adds r7, #36 @ 0x24 + 8001476: 46bd mov sp, r7 + 8001478: f85d 7b04 ldr.w r7, [sp], #4 + 800147c: 4770 bx lr + ... + +08001480 <SysTick_Config>: + \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the + function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 8001480: b580 push {r7, lr} + 8001482: b082 sub sp, #8 + 8001484: af00 add r7, sp, #0 + 8001486: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8001488: 687b ldr r3, [r7, #4] + 800148a: 3b01 subs r3, #1 + 800148c: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 8001490: d301 bcc.n 8001496 <SysTick_Config+0x16> + { + return (1UL); /* Reload value impossible */ + 8001492: 2301 movs r3, #1 + 8001494: e00f b.n 80014b6 <SysTick_Config+0x36> + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 8001496: 4a0a ldr r2, [pc, #40] @ (80014c0 <SysTick_Config+0x40>) + 8001498: 687b ldr r3, [r7, #4] + 800149a: 3b01 subs r3, #1 + 800149c: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 800149e: 210f movs r1, #15 + 80014a0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 80014a4: f7ff ff8e bl 80013c4 <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 80014a8: 4b05 ldr r3, [pc, #20] @ (80014c0 <SysTick_Config+0x40>) + 80014aa: 2200 movs r2, #0 + 80014ac: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 80014ae: 4b04 ldr r3, [pc, #16] @ (80014c0 <SysTick_Config+0x40>) + 80014b0: 2207 movs r2, #7 + 80014b2: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 80014b4: 2300 movs r3, #0 +} + 80014b6: 4618 mov r0, r3 + 80014b8: 3708 adds r7, #8 + 80014ba: 46bd mov sp, r7 + 80014bc: bd80 pop {r7, pc} + 80014be: bf00 nop + 80014c0: e000e010 .word 0xe000e010 + +080014c4 <HAL_NVIC_SetPriorityGrouping>: + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 80014c4: b580 push {r7, lr} + 80014c6: b082 sub sp, #8 + 80014c8: af00 add r7, sp, #0 + 80014ca: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 80014cc: 6878 ldr r0, [r7, #4] + 80014ce: f7ff ff29 bl 8001324 <__NVIC_SetPriorityGrouping> +} + 80014d2: bf00 nop + 80014d4: 3708 adds r7, #8 + 80014d6: 46bd mov sp, r7 + 80014d8: bd80 pop {r7, pc} + +080014da <HAL_NVIC_SetPriority>: + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 80014da: b580 push {r7, lr} + 80014dc: b086 sub sp, #24 + 80014de: af00 add r7, sp, #0 + 80014e0: 4603 mov r3, r0 + 80014e2: 60b9 str r1, [r7, #8] + 80014e4: 607a str r2, [r7, #4] + 80014e6: 73fb strb r3, [r7, #15] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 80014e8: f7ff ff40 bl 800136c <__NVIC_GetPriorityGrouping> + 80014ec: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 80014ee: 687a ldr r2, [r7, #4] + 80014f0: 68b9 ldr r1, [r7, #8] + 80014f2: 6978 ldr r0, [r7, #20] + 80014f4: f7ff ff90 bl 8001418 <NVIC_EncodePriority> + 80014f8: 4602 mov r2, r0 + 80014fa: f997 300f ldrsb.w r3, [r7, #15] + 80014fe: 4611 mov r1, r2 + 8001500: 4618 mov r0, r3 + 8001502: f7ff ff5f bl 80013c4 <__NVIC_SetPriority> +} + 8001506: bf00 nop + 8001508: 3718 adds r7, #24 + 800150a: 46bd mov sp, r7 + 800150c: bd80 pop {r7, pc} + +0800150e <HAL_NVIC_EnableIRQ>: + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 800150e: b580 push {r7, lr} + 8001510: b082 sub sp, #8 + 8001512: af00 add r7, sp, #0 + 8001514: 4603 mov r3, r0 + 8001516: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 8001518: f997 3007 ldrsb.w r3, [r7, #7] + 800151c: 4618 mov r0, r3 + 800151e: f7ff ff33 bl 8001388 <__NVIC_EnableIRQ> +} + 8001522: bf00 nop + 8001524: 3708 adds r7, #8 + 8001526: 46bd mov sp, r7 + 8001528: bd80 pop {r7, pc} + +0800152a <HAL_SYSTICK_Config>: + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 800152a: b580 push {r7, lr} + 800152c: b082 sub sp, #8 + 800152e: af00 add r7, sp, #0 + 8001530: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 8001532: 6878 ldr r0, [r7, #4] + 8001534: f7ff ffa4 bl 8001480 <SysTick_Config> + 8001538: 4603 mov r3, r0 +} + 800153a: 4618 mov r0, r3 + 800153c: 3708 adds r7, #8 + 800153e: 46bd mov sp, r7 + 8001540: bd80 pop {r7, pc} + ... + +08001544 <HAL_GPIO_Init>: + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 8001544: b480 push {r7} + 8001546: b087 sub sp, #28 + 8001548: af00 add r7, sp, #0 + 800154a: 6078 str r0, [r7, #4] + 800154c: 6039 str r1, [r7, #0] + uint32_t position = 0x00u; + 800154e: 2300 movs r3, #0 + 8001550: 617b str r3, [r7, #20] + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00u) + 8001552: e14c b.n 80017ee <HAL_GPIO_Init+0x2aa> + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1uL << position); + 8001554: 683b ldr r3, [r7, #0] + 8001556: 681a ldr r2, [r3, #0] + 8001558: 2101 movs r1, #1 + 800155a: 697b ldr r3, [r7, #20] + 800155c: fa01 f303 lsl.w r3, r1, r3 + 8001560: 4013 ands r3, r2 + 8001562: 60fb str r3, [r7, #12] + + if (iocurrent != 0x00u) + 8001564: 68fb ldr r3, [r7, #12] + 8001566: 2b00 cmp r3, #0 + 8001568: f000 813e beq.w 80017e8 <HAL_GPIO_Init+0x2a4> + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + 800156c: 683b ldr r3, [r7, #0] + 800156e: 685b ldr r3, [r3, #4] + 8001570: f003 0303 and.w r3, r3, #3 + 8001574: 2b01 cmp r3, #1 + 8001576: d005 beq.n 8001584 <HAL_GPIO_Init+0x40> + 8001578: 683b ldr r3, [r7, #0] + 800157a: 685b ldr r3, [r3, #4] + 800157c: f003 0303 and.w r3, r3, #3 + 8001580: 2b02 cmp r3, #2 + 8001582: d130 bne.n 80015e6 <HAL_GPIO_Init+0xa2> + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 8001584: 687b ldr r3, [r7, #4] + 8001586: 689b ldr r3, [r3, #8] + 8001588: 613b str r3, [r7, #16] + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); + 800158a: 697b ldr r3, [r7, #20] + 800158c: 005b lsls r3, r3, #1 + 800158e: 2203 movs r2, #3 + 8001590: fa02 f303 lsl.w r3, r2, r3 + 8001594: 43db mvns r3, r3 + 8001596: 693a ldr r2, [r7, #16] + 8001598: 4013 ands r3, r2 + 800159a: 613b str r3, [r7, #16] + temp |= (GPIO_Init->Speed << (position * 2u)); + 800159c: 683b ldr r3, [r7, #0] + 800159e: 68da ldr r2, [r3, #12] + 80015a0: 697b ldr r3, [r7, #20] + 80015a2: 005b lsls r3, r3, #1 + 80015a4: fa02 f303 lsl.w r3, r2, r3 + 80015a8: 693a ldr r2, [r7, #16] + 80015aa: 4313 orrs r3, r2 + 80015ac: 613b str r3, [r7, #16] + GPIOx->OSPEEDR = temp; + 80015ae: 687b ldr r3, [r7, #4] + 80015b0: 693a ldr r2, [r7, #16] + 80015b2: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 80015b4: 687b ldr r3, [r7, #4] + 80015b6: 685b ldr r3, [r3, #4] + 80015b8: 613b str r3, [r7, #16] + temp &= ~(GPIO_OTYPER_OT0 << position) ; + 80015ba: 2201 movs r2, #1 + 80015bc: 697b ldr r3, [r7, #20] + 80015be: fa02 f303 lsl.w r3, r2, r3 + 80015c2: 43db mvns r3, r3 + 80015c4: 693a ldr r2, [r7, #16] + 80015c6: 4013 ands r3, r2 + 80015c8: 613b str r3, [r7, #16] + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 80015ca: 683b ldr r3, [r7, #0] + 80015cc: 685b ldr r3, [r3, #4] + 80015ce: 091b lsrs r3, r3, #4 + 80015d0: f003 0201 and.w r2, r3, #1 + 80015d4: 697b ldr r3, [r7, #20] + 80015d6: fa02 f303 lsl.w r3, r2, r3 + 80015da: 693a ldr r2, [r7, #16] + 80015dc: 4313 orrs r3, r2 + 80015de: 613b str r3, [r7, #16] + GPIOx->OTYPER = temp; + 80015e0: 687b ldr r3, [r7, #4] + 80015e2: 693a ldr r2, [r7, #16] + 80015e4: 605a str r2, [r3, #4] + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 80015e6: 683b ldr r3, [r7, #0] + 80015e8: 685b ldr r3, [r3, #4] + 80015ea: f003 0303 and.w r3, r3, #3 + 80015ee: 2b03 cmp r3, #3 + 80015f0: d017 beq.n 8001622 <HAL_GPIO_Init+0xde> + { + temp = GPIOx->PUPDR; + 80015f2: 687b ldr r3, [r7, #4] + 80015f4: 68db ldr r3, [r3, #12] + 80015f6: 613b str r3, [r7, #16] + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + 80015f8: 697b ldr r3, [r7, #20] + 80015fa: 005b lsls r3, r3, #1 + 80015fc: 2203 movs r2, #3 + 80015fe: fa02 f303 lsl.w r3, r2, r3 + 8001602: 43db mvns r3, r3 + 8001604: 693a ldr r2, [r7, #16] + 8001606: 4013 ands r3, r2 + 8001608: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Pull) << (position * 2U)); + 800160a: 683b ldr r3, [r7, #0] + 800160c: 689a ldr r2, [r3, #8] + 800160e: 697b ldr r3, [r7, #20] + 8001610: 005b lsls r3, r3, #1 + 8001612: fa02 f303 lsl.w r3, r2, r3 + 8001616: 693a ldr r2, [r7, #16] + 8001618: 4313 orrs r3, r2 + 800161a: 613b str r3, [r7, #16] + GPIOx->PUPDR = temp; + 800161c: 687b ldr r3, [r7, #4] + 800161e: 693a ldr r2, [r7, #16] + 8001620: 60da str r2, [r3, #12] + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 8001622: 683b ldr r3, [r7, #0] + 8001624: 685b ldr r3, [r3, #4] + 8001626: f003 0303 and.w r3, r3, #3 + 800162a: 2b02 cmp r3, #2 + 800162c: d123 bne.n 8001676 <HAL_GPIO_Init+0x132> + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3u]; + 800162e: 697b ldr r3, [r7, #20] + 8001630: 08da lsrs r2, r3, #3 + 8001632: 687b ldr r3, [r7, #4] + 8001634: 3208 adds r2, #8 + 8001636: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800163a: 613b str r3, [r7, #16] + temp &= ~(0xFu << ((position & 0x07u) * 4u)); + 800163c: 697b ldr r3, [r7, #20] + 800163e: f003 0307 and.w r3, r3, #7 + 8001642: 009b lsls r3, r3, #2 + 8001644: 220f movs r2, #15 + 8001646: fa02 f303 lsl.w r3, r2, r3 + 800164a: 43db mvns r3, r3 + 800164c: 693a ldr r2, [r7, #16] + 800164e: 4013 ands r3, r2 + 8001650: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); + 8001652: 683b ldr r3, [r7, #0] + 8001654: 691a ldr r2, [r3, #16] + 8001656: 697b ldr r3, [r7, #20] + 8001658: f003 0307 and.w r3, r3, #7 + 800165c: 009b lsls r3, r3, #2 + 800165e: fa02 f303 lsl.w r3, r2, r3 + 8001662: 693a ldr r2, [r7, #16] + 8001664: 4313 orrs r3, r2 + 8001666: 613b str r3, [r7, #16] + GPIOx->AFR[position >> 3u] = temp; + 8001668: 697b ldr r3, [r7, #20] + 800166a: 08da lsrs r2, r3, #3 + 800166c: 687b ldr r3, [r7, #4] + 800166e: 3208 adds r2, #8 + 8001670: 6939 ldr r1, [r7, #16] + 8001672: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 8001676: 687b ldr r3, [r7, #4] + 8001678: 681b ldr r3, [r3, #0] + 800167a: 613b str r3, [r7, #16] + temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); + 800167c: 697b ldr r3, [r7, #20] + 800167e: 005b lsls r3, r3, #1 + 8001680: 2203 movs r2, #3 + 8001682: fa02 f303 lsl.w r3, r2, r3 + 8001686: 43db mvns r3, r3 + 8001688: 693a ldr r2, [r7, #16] + 800168a: 4013 ands r3, r2 + 800168c: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + 800168e: 683b ldr r3, [r7, #0] + 8001690: 685b ldr r3, [r3, #4] + 8001692: f003 0203 and.w r2, r3, #3 + 8001696: 697b ldr r3, [r7, #20] + 8001698: 005b lsls r3, r3, #1 + 800169a: fa02 f303 lsl.w r3, r2, r3 + 800169e: 693a ldr r2, [r7, #16] + 80016a0: 4313 orrs r3, r2 + 80016a2: 613b str r3, [r7, #16] + GPIOx->MODER = temp; + 80016a4: 687b ldr r3, [r7, #4] + 80016a6: 693a ldr r2, [r7, #16] + 80016a8: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + 80016aa: 683b ldr r3, [r7, #0] + 80016ac: 685b ldr r3, [r3, #4] + 80016ae: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 80016b2: 2b00 cmp r3, #0 + 80016b4: f000 8098 beq.w 80017e8 <HAL_GPIO_Init+0x2a4> + { + temp = SYSCFG->EXTICR[position >> 2u]; + 80016b8: 4a54 ldr r2, [pc, #336] @ (800180c <HAL_GPIO_Init+0x2c8>) + 80016ba: 697b ldr r3, [r7, #20] + 80016bc: 089b lsrs r3, r3, #2 + 80016be: 3302 adds r3, #2 + 80016c0: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80016c4: 613b str r3, [r7, #16] + temp &= ~(0x0FuL << (4u * (position & 0x03u))); + 80016c6: 697b ldr r3, [r7, #20] + 80016c8: f003 0303 and.w r3, r3, #3 + 80016cc: 009b lsls r3, r3, #2 + 80016ce: 220f movs r2, #15 + 80016d0: fa02 f303 lsl.w r3, r2, r3 + 80016d4: 43db mvns r3, r3 + 80016d6: 693a ldr r2, [r7, #16] + 80016d8: 4013 ands r3, r2 + 80016da: 613b str r3, [r7, #16] + temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); + 80016dc: 687b ldr r3, [r7, #4] + 80016de: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 + 80016e2: d019 beq.n 8001718 <HAL_GPIO_Init+0x1d4> + 80016e4: 687b ldr r3, [r7, #4] + 80016e6: 4a4a ldr r2, [pc, #296] @ (8001810 <HAL_GPIO_Init+0x2cc>) + 80016e8: 4293 cmp r3, r2 + 80016ea: d013 beq.n 8001714 <HAL_GPIO_Init+0x1d0> + 80016ec: 687b ldr r3, [r7, #4] + 80016ee: 4a49 ldr r2, [pc, #292] @ (8001814 <HAL_GPIO_Init+0x2d0>) + 80016f0: 4293 cmp r3, r2 + 80016f2: d00d beq.n 8001710 <HAL_GPIO_Init+0x1cc> + 80016f4: 687b ldr r3, [r7, #4] + 80016f6: 4a48 ldr r2, [pc, #288] @ (8001818 <HAL_GPIO_Init+0x2d4>) + 80016f8: 4293 cmp r3, r2 + 80016fa: d007 beq.n 800170c <HAL_GPIO_Init+0x1c8> + 80016fc: 687b ldr r3, [r7, #4] + 80016fe: 4a47 ldr r2, [pc, #284] @ (800181c <HAL_GPIO_Init+0x2d8>) + 8001700: 4293 cmp r3, r2 + 8001702: d101 bne.n 8001708 <HAL_GPIO_Init+0x1c4> + 8001704: 2304 movs r3, #4 + 8001706: e008 b.n 800171a <HAL_GPIO_Init+0x1d6> + 8001708: 2307 movs r3, #7 + 800170a: e006 b.n 800171a <HAL_GPIO_Init+0x1d6> + 800170c: 2303 movs r3, #3 + 800170e: e004 b.n 800171a <HAL_GPIO_Init+0x1d6> + 8001710: 2302 movs r3, #2 + 8001712: e002 b.n 800171a <HAL_GPIO_Init+0x1d6> + 8001714: 2301 movs r3, #1 + 8001716: e000 b.n 800171a <HAL_GPIO_Init+0x1d6> + 8001718: 2300 movs r3, #0 + 800171a: 697a ldr r2, [r7, #20] + 800171c: f002 0203 and.w r2, r2, #3 + 8001720: 0092 lsls r2, r2, #2 + 8001722: 4093 lsls r3, r2 + 8001724: 693a ldr r2, [r7, #16] + 8001726: 4313 orrs r3, r2 + 8001728: 613b str r3, [r7, #16] + SYSCFG->EXTICR[position >> 2u] = temp; + 800172a: 4938 ldr r1, [pc, #224] @ (800180c <HAL_GPIO_Init+0x2c8>) + 800172c: 697b ldr r3, [r7, #20] + 800172e: 089b lsrs r3, r3, #2 + 8001730: 3302 adds r3, #2 + 8001732: 693a ldr r2, [r7, #16] + 8001734: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR1; + 8001738: 4b39 ldr r3, [pc, #228] @ (8001820 <HAL_GPIO_Init+0x2dc>) + 800173a: 681b ldr r3, [r3, #0] + 800173c: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 800173e: 68fb ldr r3, [r7, #12] + 8001740: 43db mvns r3, r3 + 8001742: 693a ldr r2, [r7, #16] + 8001744: 4013 ands r3, r2 + 8001746: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + 8001748: 683b ldr r3, [r7, #0] + 800174a: 685b ldr r3, [r3, #4] + 800174c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8001750: 2b00 cmp r3, #0 + 8001752: d003 beq.n 800175c <HAL_GPIO_Init+0x218> + { + temp |= iocurrent; + 8001754: 693a ldr r2, [r7, #16] + 8001756: 68fb ldr r3, [r7, #12] + 8001758: 4313 orrs r3, r2 + 800175a: 613b str r3, [r7, #16] + } + EXTI->RTSR1 = temp; + 800175c: 4a30 ldr r2, [pc, #192] @ (8001820 <HAL_GPIO_Init+0x2dc>) + 800175e: 693b ldr r3, [r7, #16] + 8001760: 6013 str r3, [r2, #0] + + temp = EXTI->FTSR1; + 8001762: 4b2f ldr r3, [pc, #188] @ (8001820 <HAL_GPIO_Init+0x2dc>) + 8001764: 685b ldr r3, [r3, #4] + 8001766: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 8001768: 68fb ldr r3, [r7, #12] + 800176a: 43db mvns r3, r3 + 800176c: 693a ldr r2, [r7, #16] + 800176e: 4013 ands r3, r2 + 8001770: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + 8001772: 683b ldr r3, [r7, #0] + 8001774: 685b ldr r3, [r3, #4] + 8001776: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 800177a: 2b00 cmp r3, #0 + 800177c: d003 beq.n 8001786 <HAL_GPIO_Init+0x242> + { + temp |= iocurrent; + 800177e: 693a ldr r2, [r7, #16] + 8001780: 68fb ldr r3, [r7, #12] + 8001782: 4313 orrs r3, r2 + 8001784: 613b str r3, [r7, #16] + } + EXTI->FTSR1 = temp; + 8001786: 4a26 ldr r2, [pc, #152] @ (8001820 <HAL_GPIO_Init+0x2dc>) + 8001788: 693b ldr r3, [r7, #16] + 800178a: 6053 str r3, [r2, #4] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR1; + 800178c: 4b24 ldr r3, [pc, #144] @ (8001820 <HAL_GPIO_Init+0x2dc>) + 800178e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 8001792: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 8001794: 68fb ldr r3, [r7, #12] + 8001796: 43db mvns r3, r3 + 8001798: 693a ldr r2, [r7, #16] + 800179a: 4013 ands r3, r2 + 800179c: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) + 800179e: 683b ldr r3, [r7, #0] + 80017a0: 685b ldr r3, [r3, #4] + 80017a2: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 80017a6: 2b00 cmp r3, #0 + 80017a8: d003 beq.n 80017b2 <HAL_GPIO_Init+0x26e> + { + temp |= iocurrent; + 80017aa: 693a ldr r2, [r7, #16] + 80017ac: 68fb ldr r3, [r7, #12] + 80017ae: 4313 orrs r3, r2 + 80017b0: 613b str r3, [r7, #16] + } + EXTI->IMR1 = temp; + 80017b2: 4a1b ldr r2, [pc, #108] @ (8001820 <HAL_GPIO_Init+0x2dc>) + 80017b4: 693b ldr r3, [r7, #16] + 80017b6: f8c2 3080 str.w r3, [r2, #128] @ 0x80 + + temp = EXTI->EMR1; + 80017ba: 4b19 ldr r3, [pc, #100] @ (8001820 <HAL_GPIO_Init+0x2dc>) + 80017bc: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 + 80017c0: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 80017c2: 68fb ldr r3, [r7, #12] + 80017c4: 43db mvns r3, r3 + 80017c6: 693a ldr r2, [r7, #16] + 80017c8: 4013 ands r3, r2 + 80017ca: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) + 80017cc: 683b ldr r3, [r7, #0] + 80017ce: 685b ldr r3, [r3, #4] + 80017d0: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80017d4: 2b00 cmp r3, #0 + 80017d6: d003 beq.n 80017e0 <HAL_GPIO_Init+0x29c> + { + temp |= iocurrent; + 80017d8: 693a ldr r2, [r7, #16] + 80017da: 68fb ldr r3, [r7, #12] + 80017dc: 4313 orrs r3, r2 + 80017de: 613b str r3, [r7, #16] + } + EXTI->EMR1 = temp; + 80017e0: 4a0f ldr r2, [pc, #60] @ (8001820 <HAL_GPIO_Init+0x2dc>) + 80017e2: 693b ldr r3, [r7, #16] + 80017e4: f8c2 3084 str.w r3, [r2, #132] @ 0x84 + } + } + + position++; + 80017e8: 697b ldr r3, [r7, #20] + 80017ea: 3301 adds r3, #1 + 80017ec: 617b str r3, [r7, #20] + while (((GPIO_Init->Pin) >> position) != 0x00u) + 80017ee: 683b ldr r3, [r7, #0] + 80017f0: 681a ldr r2, [r3, #0] + 80017f2: 697b ldr r3, [r7, #20] + 80017f4: fa22 f303 lsr.w r3, r2, r3 + 80017f8: 2b00 cmp r3, #0 + 80017fa: f47f aeab bne.w 8001554 <HAL_GPIO_Init+0x10> + } +} + 80017fe: bf00 nop + 8001800: bf00 nop + 8001802: 371c adds r7, #28 + 8001804: 46bd mov sp, r7 + 8001806: f85d 7b04 ldr.w r7, [sp], #4 + 800180a: 4770 bx lr + 800180c: 40010000 .word 0x40010000 + 8001810: 48000400 .word 0x48000400 + 8001814: 48000800 .word 0x48000800 + 8001818: 48000c00 .word 0x48000c00 + 800181c: 48001000 .word 0x48001000 + 8001820: 58000800 .word 0x58000800 + +08001824 <HAL_GPIO_WritePin>: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 8001824: b480 push {r7} + 8001826: b083 sub sp, #12 + 8001828: af00 add r7, sp, #0 + 800182a: 6078 str r0, [r7, #4] + 800182c: 460b mov r3, r1 + 800182e: 807b strh r3, [r7, #2] + 8001830: 4613 mov r3, r2 + 8001832: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 8001834: 787b ldrb r3, [r7, #1] + 8001836: 2b00 cmp r3, #0 + 8001838: d003 beq.n 8001842 <HAL_GPIO_WritePin+0x1e> + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + 800183a: 887a ldrh r2, [r7, #2] + 800183c: 687b ldr r3, [r7, #4] + 800183e: 619a str r2, [r3, #24] + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + 8001840: e002 b.n 8001848 <HAL_GPIO_WritePin+0x24> + GPIOx->BRR = (uint32_t)GPIO_Pin; + 8001842: 887a ldrh r2, [r7, #2] + 8001844: 687b ldr r3, [r7, #4] + 8001846: 629a str r2, [r3, #40] @ 0x28 +} + 8001848: bf00 nop + 800184a: 370c adds r7, #12 + 800184c: 46bd mov sp, r7 + 800184e: f85d 7b04 ldr.w r7, [sp], #4 + 8001852: 4770 bx lr + +08001854 <HAL_HSEM_IRQHandler>: +/** + * @brief This function handles HSEM interrupt request + * @retval None + */ +void HAL_HSEM_IRQHandler(void) +{ + 8001854: b580 push {r7, lr} + 8001856: b082 sub sp, #8 + 8001858: af00 add r7, sp, #0 + uint32_t statusreg; + /* Get the list of masked freed semaphores*/ + statusreg = HSEM_COMMON->MISR; + 800185a: 4b0a ldr r3, [pc, #40] @ (8001884 <HAL_HSEM_IRQHandler+0x30>) + 800185c: 68db ldr r3, [r3, #12] + 800185e: 607b str r3, [r7, #4] + + /*Disable Interrupts*/ + HSEM_COMMON->IER &= ~((uint32_t)statusreg); + 8001860: 4b08 ldr r3, [pc, #32] @ (8001884 <HAL_HSEM_IRQHandler+0x30>) + 8001862: 681a ldr r2, [r3, #0] + 8001864: 687b ldr r3, [r7, #4] + 8001866: 43db mvns r3, r3 + 8001868: 4906 ldr r1, [pc, #24] @ (8001884 <HAL_HSEM_IRQHandler+0x30>) + 800186a: 4013 ands r3, r2 + 800186c: 600b str r3, [r1, #0] + + /*Clear Flags*/ + HSEM_COMMON->ICR = ((uint32_t)statusreg); + 800186e: 4a05 ldr r2, [pc, #20] @ (8001884 <HAL_HSEM_IRQHandler+0x30>) + 8001870: 687b ldr r3, [r7, #4] + 8001872: 6053 str r3, [r2, #4] + + /* Call FreeCallback */ + HAL_HSEM_FreeCallback(statusreg); + 8001874: 6878 ldr r0, [r7, #4] + 8001876: f000 f807 bl 8001888 <HAL_HSEM_FreeCallback> +} + 800187a: bf00 nop + 800187c: 3708 adds r7, #8 + 800187e: 46bd mov sp, r7 + 8001880: bd80 pop {r7, pc} + 8001882: bf00 nop + 8001884: 58001500 .word 0x58001500 + +08001888 <HAL_HSEM_FreeCallback>: + * @brief Semaphore Released Callback. + * @param SemMask: Mask of Released semaphores + * @retval None + */ +__weak void HAL_HSEM_FreeCallback(uint32_t SemMask) +{ + 8001888: b480 push {r7} + 800188a: b083 sub sp, #12 + 800188c: af00 add r7, sp, #0 + 800188e: 6078 str r0, [r7, #4] + UNUSED(SemMask); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HSEM_FreeCallback can be implemented in the user file + */ +} + 8001890: bf00 nop + 8001892: 370c adds r7, #12 + 8001894: 46bd mov sp, r7 + 8001896: f85d 7b04 ldr.w r7, [sp], #4 + 800189a: 4770 bx lr + +0800189c <HAL_I2C_Init>: + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + 800189c: b580 push {r7, lr} + 800189e: b082 sub sp, #8 + 80018a0: af00 add r7, sp, #0 + 80018a2: 6078 str r0, [r7, #4] + /* Check the I2C handle allocation */ + if (hi2c == NULL) + 80018a4: 687b ldr r3, [r7, #4] + 80018a6: 2b00 cmp r3, #0 + 80018a8: d101 bne.n 80018ae <HAL_I2C_Init+0x12> + { + return HAL_ERROR; + 80018aa: 2301 movs r3, #1 + 80018ac: e08d b.n 80019ca <HAL_I2C_Init+0x12e> + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + 80018ae: 687b ldr r3, [r7, #4] + 80018b0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 + 80018b4: b2db uxtb r3, r3 + 80018b6: 2b00 cmp r3, #0 + 80018b8: d106 bne.n 80018c8 <HAL_I2C_Init+0x2c> + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + 80018ba: 687b ldr r3, [r7, #4] + 80018bc: 2200 movs r2, #0 + 80018be: f883 2040 strb.w r2, [r3, #64] @ 0x40 + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); + 80018c2: 6878 ldr r0, [r7, #4] + 80018c4: f7ff fa80 bl 8000dc8 <HAL_I2C_MspInit> +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + 80018c8: 687b ldr r3, [r7, #4] + 80018ca: 2224 movs r2, #36 @ 0x24 + 80018cc: f883 2041 strb.w r2, [r3, #65] @ 0x41 + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + 80018d0: 687b ldr r3, [r7, #4] + 80018d2: 681b ldr r3, [r3, #0] + 80018d4: 681a ldr r2, [r3, #0] + 80018d6: 687b ldr r3, [r7, #4] + 80018d8: 681b ldr r3, [r3, #0] + 80018da: f022 0201 bic.w r2, r2, #1 + 80018de: 601a str r2, [r3, #0] + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + 80018e0: 687b ldr r3, [r7, #4] + 80018e2: 685a ldr r2, [r3, #4] + 80018e4: 687b ldr r3, [r7, #4] + 80018e6: 681b ldr r3, [r3, #0] + 80018e8: f022 6270 bic.w r2, r2, #251658240 @ 0xf000000 + 80018ec: 611a str r2, [r3, #16] + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + 80018ee: 687b ldr r3, [r7, #4] + 80018f0: 681b ldr r3, [r3, #0] + 80018f2: 689a ldr r2, [r3, #8] + 80018f4: 687b ldr r3, [r7, #4] + 80018f6: 681b ldr r3, [r3, #0] + 80018f8: f422 4200 bic.w r2, r2, #32768 @ 0x8000 + 80018fc: 609a str r2, [r3, #8] + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + 80018fe: 687b ldr r3, [r7, #4] + 8001900: 68db ldr r3, [r3, #12] + 8001902: 2b01 cmp r3, #1 + 8001904: d107 bne.n 8001916 <HAL_I2C_Init+0x7a> + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + 8001906: 687b ldr r3, [r7, #4] + 8001908: 689a ldr r2, [r3, #8] + 800190a: 687b ldr r3, [r7, #4] + 800190c: 681b ldr r3, [r3, #0] + 800190e: f442 4200 orr.w r2, r2, #32768 @ 0x8000 + 8001912: 609a str r2, [r3, #8] + 8001914: e006 b.n 8001924 <HAL_I2C_Init+0x88> + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + 8001916: 687b ldr r3, [r7, #4] + 8001918: 689a ldr r2, [r3, #8] + 800191a: 687b ldr r3, [r7, #4] + 800191c: 681b ldr r3, [r3, #0] + 800191e: f442 4204 orr.w r2, r2, #33792 @ 0x8400 + 8001922: 609a str r2, [r3, #8] + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + 8001924: 687b ldr r3, [r7, #4] + 8001926: 68db ldr r3, [r3, #12] + 8001928: 2b02 cmp r3, #2 + 800192a: d108 bne.n 800193e <HAL_I2C_Init+0xa2> + { + SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + 800192c: 687b ldr r3, [r7, #4] + 800192e: 681b ldr r3, [r3, #0] + 8001930: 685a ldr r2, [r3, #4] + 8001932: 687b ldr r3, [r7, #4] + 8001934: 681b ldr r3, [r3, #0] + 8001936: f442 6200 orr.w r2, r2, #2048 @ 0x800 + 800193a: 605a str r2, [r3, #4] + 800193c: e007 b.n 800194e <HAL_I2C_Init+0xb2> + } + else + { + /* Clear the I2C ADD10 bit */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + 800193e: 687b ldr r3, [r7, #4] + 8001940: 681b ldr r3, [r3, #0] + 8001942: 685a ldr r2, [r3, #4] + 8001944: 687b ldr r3, [r7, #4] + 8001946: 681b ldr r3, [r3, #0] + 8001948: f422 6200 bic.w r2, r2, #2048 @ 0x800 + 800194c: 605a str r2, [r3, #4] + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + 800194e: 687b ldr r3, [r7, #4] + 8001950: 681b ldr r3, [r3, #0] + 8001952: 685b ldr r3, [r3, #4] + 8001954: 687a ldr r2, [r7, #4] + 8001956: 6812 ldr r2, [r2, #0] + 8001958: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 + 800195c: f443 4300 orr.w r3, r3, #32768 @ 0x8000 + 8001960: 6053 str r3, [r2, #4] + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + 8001962: 687b ldr r3, [r7, #4] + 8001964: 681b ldr r3, [r3, #0] + 8001966: 68da ldr r2, [r3, #12] + 8001968: 687b ldr r3, [r7, #4] + 800196a: 681b ldr r3, [r3, #0] + 800196c: f422 4200 bic.w r2, r2, #32768 @ 0x8000 + 8001970: 60da str r2, [r3, #12] + + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + 8001972: 687b ldr r3, [r7, #4] + 8001974: 691a ldr r2, [r3, #16] + 8001976: 687b ldr r3, [r7, #4] + 8001978: 695b ldr r3, [r3, #20] + 800197a: ea42 0103 orr.w r1, r2, r3 + (hi2c->Init.OwnAddress2Masks << 8)); + 800197e: 687b ldr r3, [r7, #4] + 8001980: 699b ldr r3, [r3, #24] + 8001982: 021a lsls r2, r3, #8 + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + 8001984: 687b ldr r3, [r7, #4] + 8001986: 681b ldr r3, [r3, #0] + 8001988: 430a orrs r2, r1 + 800198a: 60da str r2, [r3, #12] + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + 800198c: 687b ldr r3, [r7, #4] + 800198e: 69d9 ldr r1, [r3, #28] + 8001990: 687b ldr r3, [r7, #4] + 8001992: 6a1a ldr r2, [r3, #32] + 8001994: 687b ldr r3, [r7, #4] + 8001996: 681b ldr r3, [r3, #0] + 8001998: 430a orrs r2, r1 + 800199a: 601a str r2, [r3, #0] + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + 800199c: 687b ldr r3, [r7, #4] + 800199e: 681b ldr r3, [r3, #0] + 80019a0: 681a ldr r2, [r3, #0] + 80019a2: 687b ldr r3, [r7, #4] + 80019a4: 681b ldr r3, [r3, #0] + 80019a6: f042 0201 orr.w r2, r2, #1 + 80019aa: 601a str r2, [r3, #0] + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 80019ac: 687b ldr r3, [r7, #4] + 80019ae: 2200 movs r2, #0 + 80019b0: 645a str r2, [r3, #68] @ 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 80019b2: 687b ldr r3, [r7, #4] + 80019b4: 2220 movs r2, #32 + 80019b6: f883 2041 strb.w r2, [r3, #65] @ 0x41 + hi2c->PreviousState = I2C_STATE_NONE; + 80019ba: 687b ldr r3, [r7, #4] + 80019bc: 2200 movs r2, #0 + 80019be: 631a str r2, [r3, #48] @ 0x30 + hi2c->Mode = HAL_I2C_MODE_NONE; + 80019c0: 687b ldr r3, [r7, #4] + 80019c2: 2200 movs r2, #0 + 80019c4: f883 2042 strb.w r2, [r3, #66] @ 0x42 + + return HAL_OK; + 80019c8: 2300 movs r3, #0 +} + 80019ca: 4618 mov r0, r3 + 80019cc: 3708 adds r7, #8 + 80019ce: 46bd mov sp, r7 + 80019d0: bd80 pop {r7, pc} + +080019d2 <HAL_I2CEx_ConfigAnalogFilter>: + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + 80019d2: b480 push {r7} + 80019d4: b083 sub sp, #12 + 80019d6: af00 add r7, sp, #0 + 80019d8: 6078 str r0, [r7, #4] + 80019da: 6039 str r1, [r7, #0] + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + 80019dc: 687b ldr r3, [r7, #4] + 80019de: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 + 80019e2: b2db uxtb r3, r3 + 80019e4: 2b20 cmp r3, #32 + 80019e6: d138 bne.n 8001a5a <HAL_I2CEx_ConfigAnalogFilter+0x88> + { + /* Process Locked */ + __HAL_LOCK(hi2c); + 80019e8: 687b ldr r3, [r7, #4] + 80019ea: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 + 80019ee: 2b01 cmp r3, #1 + 80019f0: d101 bne.n 80019f6 <HAL_I2CEx_ConfigAnalogFilter+0x24> + 80019f2: 2302 movs r3, #2 + 80019f4: e032 b.n 8001a5c <HAL_I2CEx_ConfigAnalogFilter+0x8a> + 80019f6: 687b ldr r3, [r7, #4] + 80019f8: 2201 movs r2, #1 + 80019fa: f883 2040 strb.w r2, [r3, #64] @ 0x40 + + hi2c->State = HAL_I2C_STATE_BUSY; + 80019fe: 687b ldr r3, [r7, #4] + 8001a00: 2224 movs r2, #36 @ 0x24 + 8001a02: f883 2041 strb.w r2, [r3, #65] @ 0x41 + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + 8001a06: 687b ldr r3, [r7, #4] + 8001a08: 681b ldr r3, [r3, #0] + 8001a0a: 681a ldr r2, [r3, #0] + 8001a0c: 687b ldr r3, [r7, #4] + 8001a0e: 681b ldr r3, [r3, #0] + 8001a10: f022 0201 bic.w r2, r2, #1 + 8001a14: 601a str r2, [r3, #0] + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + 8001a16: 687b ldr r3, [r7, #4] + 8001a18: 681b ldr r3, [r3, #0] + 8001a1a: 681a ldr r2, [r3, #0] + 8001a1c: 687b ldr r3, [r7, #4] + 8001a1e: 681b ldr r3, [r3, #0] + 8001a20: f422 5280 bic.w r2, r2, #4096 @ 0x1000 + 8001a24: 601a str r2, [r3, #0] + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + 8001a26: 687b ldr r3, [r7, #4] + 8001a28: 681b ldr r3, [r3, #0] + 8001a2a: 6819 ldr r1, [r3, #0] + 8001a2c: 687b ldr r3, [r7, #4] + 8001a2e: 681b ldr r3, [r3, #0] + 8001a30: 683a ldr r2, [r7, #0] + 8001a32: 430a orrs r2, r1 + 8001a34: 601a str r2, [r3, #0] + + __HAL_I2C_ENABLE(hi2c); + 8001a36: 687b ldr r3, [r7, #4] + 8001a38: 681b ldr r3, [r3, #0] + 8001a3a: 681a ldr r2, [r3, #0] + 8001a3c: 687b ldr r3, [r7, #4] + 8001a3e: 681b ldr r3, [r3, #0] + 8001a40: f042 0201 orr.w r2, r2, #1 + 8001a44: 601a str r2, [r3, #0] + + hi2c->State = HAL_I2C_STATE_READY; + 8001a46: 687b ldr r3, [r7, #4] + 8001a48: 2220 movs r2, #32 + 8001a4a: f883 2041 strb.w r2, [r3, #65] @ 0x41 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8001a4e: 687b ldr r3, [r7, #4] + 8001a50: 2200 movs r2, #0 + 8001a52: f883 2040 strb.w r2, [r3, #64] @ 0x40 + + return HAL_OK; + 8001a56: 2300 movs r3, #0 + 8001a58: e000 b.n 8001a5c <HAL_I2CEx_ConfigAnalogFilter+0x8a> + } + else + { + return HAL_BUSY; + 8001a5a: 2302 movs r3, #2 + } +} + 8001a5c: 4618 mov r0, r3 + 8001a5e: 370c adds r7, #12 + 8001a60: 46bd mov sp, r7 + 8001a62: f85d 7b04 ldr.w r7, [sp], #4 + 8001a66: 4770 bx lr + +08001a68 <HAL_I2CEx_ConfigDigitalFilter>: + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + 8001a68: b480 push {r7} + 8001a6a: b085 sub sp, #20 + 8001a6c: af00 add r7, sp, #0 + 8001a6e: 6078 str r0, [r7, #4] + 8001a70: 6039 str r1, [r7, #0] + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + 8001a72: 687b ldr r3, [r7, #4] + 8001a74: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 + 8001a78: b2db uxtb r3, r3 + 8001a7a: 2b20 cmp r3, #32 + 8001a7c: d139 bne.n 8001af2 <HAL_I2CEx_ConfigDigitalFilter+0x8a> + { + /* Process Locked */ + __HAL_LOCK(hi2c); + 8001a7e: 687b ldr r3, [r7, #4] + 8001a80: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 + 8001a84: 2b01 cmp r3, #1 + 8001a86: d101 bne.n 8001a8c <HAL_I2CEx_ConfigDigitalFilter+0x24> + 8001a88: 2302 movs r3, #2 + 8001a8a: e033 b.n 8001af4 <HAL_I2CEx_ConfigDigitalFilter+0x8c> + 8001a8c: 687b ldr r3, [r7, #4] + 8001a8e: 2201 movs r2, #1 + 8001a90: f883 2040 strb.w r2, [r3, #64] @ 0x40 + + hi2c->State = HAL_I2C_STATE_BUSY; + 8001a94: 687b ldr r3, [r7, #4] + 8001a96: 2224 movs r2, #36 @ 0x24 + 8001a98: f883 2041 strb.w r2, [r3, #65] @ 0x41 + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + 8001a9c: 687b ldr r3, [r7, #4] + 8001a9e: 681b ldr r3, [r3, #0] + 8001aa0: 681a ldr r2, [r3, #0] + 8001aa2: 687b ldr r3, [r7, #4] + 8001aa4: 681b ldr r3, [r3, #0] + 8001aa6: f022 0201 bic.w r2, r2, #1 + 8001aaa: 601a str r2, [r3, #0] + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + 8001aac: 687b ldr r3, [r7, #4] + 8001aae: 681b ldr r3, [r3, #0] + 8001ab0: 681b ldr r3, [r3, #0] + 8001ab2: 60fb str r3, [r7, #12] + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + 8001ab4: 68fb ldr r3, [r7, #12] + 8001ab6: f423 6370 bic.w r3, r3, #3840 @ 0xf00 + 8001aba: 60fb str r3, [r7, #12] + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8U; + 8001abc: 683b ldr r3, [r7, #0] + 8001abe: 021b lsls r3, r3, #8 + 8001ac0: 68fa ldr r2, [r7, #12] + 8001ac2: 4313 orrs r3, r2 + 8001ac4: 60fb str r3, [r7, #12] + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + 8001ac6: 687b ldr r3, [r7, #4] + 8001ac8: 681b ldr r3, [r3, #0] + 8001aca: 68fa ldr r2, [r7, #12] + 8001acc: 601a str r2, [r3, #0] + + __HAL_I2C_ENABLE(hi2c); + 8001ace: 687b ldr r3, [r7, #4] + 8001ad0: 681b ldr r3, [r3, #0] + 8001ad2: 681a ldr r2, [r3, #0] + 8001ad4: 687b ldr r3, [r7, #4] + 8001ad6: 681b ldr r3, [r3, #0] + 8001ad8: f042 0201 orr.w r2, r2, #1 + 8001adc: 601a str r2, [r3, #0] + + hi2c->State = HAL_I2C_STATE_READY; + 8001ade: 687b ldr r3, [r7, #4] + 8001ae0: 2220 movs r2, #32 + 8001ae2: f883 2041 strb.w r2, [r3, #65] @ 0x41 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8001ae6: 687b ldr r3, [r7, #4] + 8001ae8: 2200 movs r2, #0 + 8001aea: f883 2040 strb.w r2, [r3, #64] @ 0x40 + + return HAL_OK; + 8001aee: 2300 movs r3, #0 + 8001af0: e000 b.n 8001af4 <HAL_I2CEx_ConfigDigitalFilter+0x8c> + } + else + { + return HAL_BUSY; + 8001af2: 2302 movs r3, #2 + } +} + 8001af4: 4618 mov r0, r3 + 8001af6: 3714 adds r7, #20 + 8001af8: 46bd mov sp, r7 + 8001afa: f85d 7b04 ldr.w r7, [sp], #4 + 8001afe: 4770 bx lr + +08001b00 <HAL_IPCC_Init>: + * @brief Initialize the IPCC peripheral. + * @param hipcc IPCC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IPCC_Init(IPCC_HandleTypeDef *hipcc) +{ + 8001b00: b580 push {r7, lr} + 8001b02: b084 sub sp, #16 + 8001b04: af00 add r7, sp, #0 + 8001b06: 6078 str r0, [r7, #4] + HAL_StatusTypeDef err = HAL_OK; + 8001b08: 2300 movs r3, #0 + 8001b0a: 73fb strb r3, [r7, #15] + + /* Check the IPCC handle allocation */ + if (hipcc != NULL) + 8001b0c: 687b ldr r3, [r7, #4] + 8001b0e: 2b00 cmp r3, #0 + 8001b10: d01e beq.n 8001b50 <HAL_IPCC_Init+0x50> + { + /* Check the parameters */ + assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance)); + + IPCC_CommonTypeDef *currentInstance = IPCC_C1; + 8001b12: 4b13 ldr r3, [pc, #76] @ (8001b60 <HAL_IPCC_Init+0x60>) + 8001b14: 60bb str r3, [r7, #8] + + if (hipcc->State == HAL_IPCC_STATE_RESET) + 8001b16: 687b ldr r3, [r7, #4] + 8001b18: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 8001b1c: b2db uxtb r3, r3 + 8001b1e: 2b00 cmp r3, #0 + 8001b20: d102 bne.n 8001b28 <HAL_IPCC_Init+0x28> + { + /* Init the low level hardware : CLOCK, NVIC */ + HAL_IPCC_MspInit(hipcc); + 8001b22: 6878 ldr r0, [r7, #4] + 8001b24: f7ff f996 bl 8000e54 <HAL_IPCC_MspInit> + } + + /* Reset all registers of the current cpu to default state */ + IPCC_Reset_Register(currentInstance); + 8001b28: 68b8 ldr r0, [r7, #8] + 8001b2a: f000 f8f5 bl 8001d18 <IPCC_Reset_Register> + + /* Activate the interrupts */ + currentInstance->CR |= (IPCC_CR_RXOIE | IPCC_CR_TXFIE); + 8001b2e: 68bb ldr r3, [r7, #8] + 8001b30: 681b ldr r3, [r3, #0] + 8001b32: f043 1201 orr.w r2, r3, #65537 @ 0x10001 + 8001b36: 68bb ldr r3, [r7, #8] + 8001b38: 601a str r2, [r3, #0] + + /* Clear callback pointers */ + IPCC_SetDefaultCallbacks(hipcc); + 8001b3a: 6878 ldr r0, [r7, #4] + 8001b3c: f000 f8c6 bl 8001ccc <IPCC_SetDefaultCallbacks> + + /* Reset all callback notification request */ + hipcc->callbackRequest = 0; + 8001b40: 687b ldr r3, [r7, #4] + 8001b42: 2200 movs r2, #0 + 8001b44: 635a str r2, [r3, #52] @ 0x34 + + hipcc->State = HAL_IPCC_STATE_READY; + 8001b46: 687b ldr r3, [r7, #4] + 8001b48: 2201 movs r2, #1 + 8001b4a: f883 2038 strb.w r2, [r3, #56] @ 0x38 + 8001b4e: e001 b.n 8001b54 <HAL_IPCC_Init+0x54> + } + else + { + err = HAL_ERROR; + 8001b50: 2301 movs r3, #1 + 8001b52: 73fb strb r3, [r7, #15] + } + + return err; + 8001b54: 7bfb ldrb r3, [r7, #15] +} + 8001b56: 4618 mov r0, r3 + 8001b58: 3710 adds r7, #16 + 8001b5a: 46bd mov sp, r7 + 8001b5c: bd80 pop {r7, pc} + 8001b5e: bf00 nop + 8001b60: 58000c00 .word 0x58000c00 + +08001b64 <HAL_IPCC_TX_IRQHandler>: + * @brief This function handles IPCC Tx Free interrupt request. + * @param hipcc IPCC handle + * @retval None + */ +void HAL_IPCC_TX_IRQHandler(IPCC_HandleTypeDef *const hipcc) +{ + 8001b64: b580 push {r7, lr} + 8001b66: b086 sub sp, #24 + 8001b68: af00 add r7, sp, #0 + 8001b6a: 6078 str r0, [r7, #4] + uint32_t irqmask; + uint32_t bit_pos; + uint32_t ch_count = 0U; + 8001b6c: 2300 movs r3, #0 + 8001b6e: 613b str r3, [r7, #16] + IPCC_CommonTypeDef *currentInstance = IPCC_C1; + 8001b70: 4b22 ldr r3, [pc, #136] @ (8001bfc <HAL_IPCC_TX_IRQHandler+0x98>) + 8001b72: 60fb str r3, [r7, #12] + + /* check the Tx free channels which are not masked */ + irqmask = ~(currentInstance->MR) & IPCC_ALL_TX_BUF; + 8001b74: 68fb ldr r3, [r7, #12] + 8001b76: 685b ldr r3, [r3, #4] + 8001b78: 43db mvns r3, r3 + 8001b7a: f403 137c and.w r3, r3, #4128768 @ 0x3f0000 + 8001b7e: 617b str r3, [r7, #20] + irqmask = irqmask & ~(currentInstance->SR << IPCC_MR_CH1FM_Pos); + 8001b80: 68fb ldr r3, [r7, #12] + 8001b82: 68db ldr r3, [r3, #12] + 8001b84: 041b lsls r3, r3, #16 + 8001b86: 43db mvns r3, r3 + 8001b88: 697a ldr r2, [r7, #20] + 8001b8a: 4013 ands r3, r2 + 8001b8c: 617b str r3, [r7, #20] + + while (irqmask != 0UL) /* if several bits are set, it loops to serve all of them */ + 8001b8e: e02c b.n 8001bea <HAL_IPCC_TX_IRQHandler+0x86> + { + bit_pos = 1UL << (IPCC_MR_CH1FM_Pos + (ch_count & CHANNEL_INDEX_MASK)); + 8001b90: 693b ldr r3, [r7, #16] + 8001b92: f003 030f and.w r3, r3, #15 + 8001b96: 3310 adds r3, #16 + 8001b98: 2201 movs r2, #1 + 8001b9a: fa02 f303 lsl.w r3, r2, r3 + 8001b9e: 60bb str r3, [r7, #8] + + if ((irqmask & bit_pos) != 0U) + 8001ba0: 697a ldr r2, [r7, #20] + 8001ba2: 68bb ldr r3, [r7, #8] + 8001ba4: 4013 ands r3, r2 + 8001ba6: 2b00 cmp r3, #0 + 8001ba8: d01c beq.n 8001be4 <HAL_IPCC_TX_IRQHandler+0x80> + { + /* mask the channel Free interrupt */ + currentInstance->MR |= bit_pos; + 8001baa: 68fb ldr r3, [r7, #12] + 8001bac: 685a ldr r2, [r3, #4] + 8001bae: 68bb ldr r3, [r7, #8] + 8001bb0: 431a orrs r2, r3 + 8001bb2: 68fb ldr r3, [r7, #12] + 8001bb4: 605a str r2, [r3, #4] + if (hipcc->ChannelCallbackTx[ch_count] != NULL) + 8001bb6: 687a ldr r2, [r7, #4] + 8001bb8: 693b ldr r3, [r7, #16] + 8001bba: 3306 adds r3, #6 + 8001bbc: 009b lsls r3, r3, #2 + 8001bbe: 4413 add r3, r2 + 8001bc0: 685b ldr r3, [r3, #4] + 8001bc2: 2b00 cmp r3, #0 + 8001bc4: d009 beq.n 8001bda <HAL_IPCC_TX_IRQHandler+0x76> + { + hipcc->ChannelCallbackTx[ch_count](hipcc, ch_count, IPCC_CHANNEL_DIR_TX); + 8001bc6: 687a ldr r2, [r7, #4] + 8001bc8: 693b ldr r3, [r7, #16] + 8001bca: 3306 adds r3, #6 + 8001bcc: 009b lsls r3, r3, #2 + 8001bce: 4413 add r3, r2 + 8001bd0: 685b ldr r3, [r3, #4] + 8001bd2: 2200 movs r2, #0 + 8001bd4: 6939 ldr r1, [r7, #16] + 8001bd6: 6878 ldr r0, [r7, #4] + 8001bd8: 4798 blx r3 + } + irqmask = irqmask & ~(bit_pos); + 8001bda: 68bb ldr r3, [r7, #8] + 8001bdc: 43db mvns r3, r3 + 8001bde: 697a ldr r2, [r7, #20] + 8001be0: 4013 ands r3, r2 + 8001be2: 617b str r3, [r7, #20] + } + ch_count++; + 8001be4: 693b ldr r3, [r7, #16] + 8001be6: 3301 adds r3, #1 + 8001be8: 613b str r3, [r7, #16] + while (irqmask != 0UL) /* if several bits are set, it loops to serve all of them */ + 8001bea: 697b ldr r3, [r7, #20] + 8001bec: 2b00 cmp r3, #0 + 8001bee: d1cf bne.n 8001b90 <HAL_IPCC_TX_IRQHandler+0x2c> + } +} + 8001bf0: bf00 nop + 8001bf2: bf00 nop + 8001bf4: 3718 adds r7, #24 + 8001bf6: 46bd mov sp, r7 + 8001bf8: bd80 pop {r7, pc} + 8001bfa: bf00 nop + 8001bfc: 58000c00 .word 0x58000c00 + +08001c00 <HAL_IPCC_RX_IRQHandler>: + * @brief This function handles IPCC Rx Occupied interrupt request. + * @param hipcc : IPCC handle + * @retval None + */ +void HAL_IPCC_RX_IRQHandler(IPCC_HandleTypeDef *const hipcc) +{ + 8001c00: b580 push {r7, lr} + 8001c02: b088 sub sp, #32 + 8001c04: af00 add r7, sp, #0 + 8001c06: 6078 str r0, [r7, #4] + uint32_t irqmask; + uint32_t bit_pos; + uint32_t ch_count = 0U; + 8001c08: 2300 movs r3, #0 + 8001c0a: 61bb str r3, [r7, #24] + IPCC_CommonTypeDef *currentInstance = IPCC_C1; + 8001c0c: 4b20 ldr r3, [pc, #128] @ (8001c90 <HAL_IPCC_RX_IRQHandler+0x90>) + 8001c0e: 617b str r3, [r7, #20] + IPCC_CommonTypeDef *otherInstance = IPCC_C2; + 8001c10: 4b20 ldr r3, [pc, #128] @ (8001c94 <HAL_IPCC_RX_IRQHandler+0x94>) + 8001c12: 613b str r3, [r7, #16] + + /* check the Rx occupied channels which are not masked */ + irqmask = ~(currentInstance->MR) & IPCC_ALL_RX_BUF; + 8001c14: 697b ldr r3, [r7, #20] + 8001c16: 685b ldr r3, [r3, #4] + 8001c18: 43db mvns r3, r3 + 8001c1a: f003 033f and.w r3, r3, #63 @ 0x3f + 8001c1e: 61fb str r3, [r7, #28] + irqmask = irqmask & otherInstance->SR; + 8001c20: 693b ldr r3, [r7, #16] + 8001c22: 68db ldr r3, [r3, #12] + 8001c24: 69fa ldr r2, [r7, #28] + 8001c26: 4013 ands r3, r2 + 8001c28: 61fb str r3, [r7, #28] + + while (irqmask != 0UL) /* if several bits are set, it loops to serve all of them */ + 8001c2a: e029 b.n 8001c80 <HAL_IPCC_RX_IRQHandler+0x80> + { + bit_pos = 1UL << (ch_count & CHANNEL_INDEX_MASK); + 8001c2c: 69bb ldr r3, [r7, #24] + 8001c2e: f003 030f and.w r3, r3, #15 + 8001c32: 2201 movs r2, #1 + 8001c34: fa02 f303 lsl.w r3, r2, r3 + 8001c38: 60fb str r3, [r7, #12] + + if ((irqmask & bit_pos) != 0U) + 8001c3a: 69fa ldr r2, [r7, #28] + 8001c3c: 68fb ldr r3, [r7, #12] + 8001c3e: 4013 ands r3, r2 + 8001c40: 2b00 cmp r3, #0 + 8001c42: d01a beq.n 8001c7a <HAL_IPCC_RX_IRQHandler+0x7a> + { + /* mask the channel occupied interrupt */ + currentInstance->MR |= bit_pos; + 8001c44: 697b ldr r3, [r7, #20] + 8001c46: 685a ldr r2, [r3, #4] + 8001c48: 68fb ldr r3, [r7, #12] + 8001c4a: 431a orrs r2, r3 + 8001c4c: 697b ldr r3, [r7, #20] + 8001c4e: 605a str r2, [r3, #4] + if (hipcc->ChannelCallbackRx[ch_count] != NULL) + 8001c50: 687a ldr r2, [r7, #4] + 8001c52: 69bb ldr r3, [r7, #24] + 8001c54: 009b lsls r3, r3, #2 + 8001c56: 4413 add r3, r2 + 8001c58: 685b ldr r3, [r3, #4] + 8001c5a: 2b00 cmp r3, #0 + 8001c5c: d008 beq.n 8001c70 <HAL_IPCC_RX_IRQHandler+0x70> + { + hipcc->ChannelCallbackRx[ch_count](hipcc, ch_count, IPCC_CHANNEL_DIR_RX); + 8001c5e: 687a ldr r2, [r7, #4] + 8001c60: 69bb ldr r3, [r7, #24] + 8001c62: 009b lsls r3, r3, #2 + 8001c64: 4413 add r3, r2 + 8001c66: 685b ldr r3, [r3, #4] + 8001c68: 2201 movs r2, #1 + 8001c6a: 69b9 ldr r1, [r7, #24] + 8001c6c: 6878 ldr r0, [r7, #4] + 8001c6e: 4798 blx r3 + } + irqmask = irqmask & ~(bit_pos); + 8001c70: 68fb ldr r3, [r7, #12] + 8001c72: 43db mvns r3, r3 + 8001c74: 69fa ldr r2, [r7, #28] + 8001c76: 4013 ands r3, r2 + 8001c78: 61fb str r3, [r7, #28] + } + ch_count++; + 8001c7a: 69bb ldr r3, [r7, #24] + 8001c7c: 3301 adds r3, #1 + 8001c7e: 61bb str r3, [r7, #24] + while (irqmask != 0UL) /* if several bits are set, it loops to serve all of them */ + 8001c80: 69fb ldr r3, [r7, #28] + 8001c82: 2b00 cmp r3, #0 + 8001c84: d1d2 bne.n 8001c2c <HAL_IPCC_RX_IRQHandler+0x2c> + } +} + 8001c86: bf00 nop + 8001c88: bf00 nop + 8001c8a: 3720 adds r7, #32 + 8001c8c: 46bd mov sp, r7 + 8001c8e: bd80 pop {r7, pc} + 8001c90: 58000c00 .word 0x58000c00 + 8001c94: 58000c10 .word 0x58000c10 + +08001c98 <HAL_IPCC_RxCallback>: + * @arg IPCC_CHANNEL_5: IPCC Channel 5 + * @arg IPCC_CHANNEL_6: IPCC Channel 6 + * @param ChannelDir Channel direction + */ +__weak void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir) +{ + 8001c98: b480 push {r7} + 8001c9a: b085 sub sp, #20 + 8001c9c: af00 add r7, sp, #0 + 8001c9e: 60f8 str r0, [r7, #12] + 8001ca0: 60b9 str r1, [r7, #8] + 8001ca2: 4613 mov r3, r2 + 8001ca4: 71fb strb r3, [r7, #7] + UNUSED(ChannelDir); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IPCC_RxCallback can be implemented in the user file + */ +} + 8001ca6: bf00 nop + 8001ca8: 3714 adds r7, #20 + 8001caa: 46bd mov sp, r7 + 8001cac: f85d 7b04 ldr.w r7, [sp], #4 + 8001cb0: 4770 bx lr + +08001cb2 <HAL_IPCC_TxCallback>: + * @arg IPCC_CHANNEL_5: IPCC Channel 5 + * @arg IPCC_CHANNEL_6: IPCC Channel 6 + * @param ChannelDir Channel direction + */ +__weak void HAL_IPCC_TxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir) +{ + 8001cb2: b480 push {r7} + 8001cb4: b085 sub sp, #20 + 8001cb6: af00 add r7, sp, #0 + 8001cb8: 60f8 str r0, [r7, #12] + 8001cba: 60b9 str r1, [r7, #8] + 8001cbc: 4613 mov r3, r2 + 8001cbe: 71fb strb r3, [r7, #7] + UNUSED(ChannelDir); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IPCC_TxCallback can be implemented in the user file + */ +} + 8001cc0: bf00 nop + 8001cc2: 3714 adds r7, #20 + 8001cc4: 46bd mov sp, r7 + 8001cc6: f85d 7b04 ldr.w r7, [sp], #4 + 8001cca: 4770 bx lr + +08001ccc <IPCC_SetDefaultCallbacks>: +/** + * @brief Reset all callbacks of the handle to NULL. + * @param hipcc IPCC handle + */ +void IPCC_SetDefaultCallbacks(IPCC_HandleTypeDef *hipcc) +{ + 8001ccc: b480 push {r7} + 8001cce: b085 sub sp, #20 + 8001cd0: af00 add r7, sp, #0 + 8001cd2: 6078 str r0, [r7, #4] + uint32_t i; + /* Set all callbacks to default */ + for (i = 0; i < IPCC_CHANNEL_NUMBER; i++) + 8001cd4: 2300 movs r3, #0 + 8001cd6: 60fb str r3, [r7, #12] + 8001cd8: e00f b.n 8001cfa <IPCC_SetDefaultCallbacks+0x2e> + { + hipcc->ChannelCallbackRx[i] = HAL_IPCC_RxCallback; + 8001cda: 687a ldr r2, [r7, #4] + 8001cdc: 68fb ldr r3, [r7, #12] + 8001cde: 009b lsls r3, r3, #2 + 8001ce0: 4413 add r3, r2 + 8001ce2: 4a0b ldr r2, [pc, #44] @ (8001d10 <IPCC_SetDefaultCallbacks+0x44>) + 8001ce4: 605a str r2, [r3, #4] + hipcc->ChannelCallbackTx[i] = HAL_IPCC_TxCallback; + 8001ce6: 687a ldr r2, [r7, #4] + 8001ce8: 68fb ldr r3, [r7, #12] + 8001cea: 3306 adds r3, #6 + 8001cec: 009b lsls r3, r3, #2 + 8001cee: 4413 add r3, r2 + 8001cf0: 4a08 ldr r2, [pc, #32] @ (8001d14 <IPCC_SetDefaultCallbacks+0x48>) + 8001cf2: 605a str r2, [r3, #4] + for (i = 0; i < IPCC_CHANNEL_NUMBER; i++) + 8001cf4: 68fb ldr r3, [r7, #12] + 8001cf6: 3301 adds r3, #1 + 8001cf8: 60fb str r3, [r7, #12] + 8001cfa: 68fb ldr r3, [r7, #12] + 8001cfc: 2b05 cmp r3, #5 + 8001cfe: d9ec bls.n 8001cda <IPCC_SetDefaultCallbacks+0xe> + } +} + 8001d00: bf00 nop + 8001d02: bf00 nop + 8001d04: 3714 adds r7, #20 + 8001d06: 46bd mov sp, r7 + 8001d08: f85d 7b04 ldr.w r7, [sp], #4 + 8001d0c: 4770 bx lr + 8001d0e: bf00 nop + 8001d10: 08001c99 .word 0x08001c99 + 8001d14: 08001cb3 .word 0x08001cb3 + +08001d18 <IPCC_Reset_Register>: +/** + * @brief Reset IPCC register to default value for the concerned instance. + * @param Instance pointer to register + */ +void IPCC_Reset_Register(IPCC_CommonTypeDef *Instance) +{ + 8001d18: b480 push {r7} + 8001d1a: b083 sub sp, #12 + 8001d1c: af00 add r7, sp, #0 + 8001d1e: 6078 str r0, [r7, #4] + /* Disable RX and TX interrupts */ + Instance->CR = 0x00000000U; + 8001d20: 687b ldr r3, [r7, #4] + 8001d22: 2200 movs r2, #0 + 8001d24: 601a str r2, [r3, #0] + + /* Mask RX and TX interrupts */ + Instance->MR = (IPCC_ALL_TX_BUF | IPCC_ALL_RX_BUF); + 8001d26: 687b ldr r3, [r7, #4] + 8001d28: f04f 123f mov.w r2, #4128831 @ 0x3f003f + 8001d2c: 605a str r2, [r3, #4] + + /* Clear RX status */ + Instance->SCR = IPCC_ALL_RX_BUF; + 8001d2e: 687b ldr r3, [r7, #4] + 8001d30: 223f movs r2, #63 @ 0x3f + 8001d32: 609a str r2, [r3, #8] +} + 8001d34: bf00 nop + 8001d36: 370c adds r7, #12 + 8001d38: 46bd mov sp, r7 + 8001d3a: f85d 7b04 ldr.w r7, [sp], #4 + 8001d3e: 4770 bx lr + +08001d40 <HAL_PWR_EnableBkUpAccess>: + * @note LSEON bit that switches on and off the LSE crystal belongs as well to the + * back-up domain. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + 8001d40: b480 push {r7} + 8001d42: af00 add r7, sp, #0 + SET_BIT(PWR->CR1, PWR_CR1_DBP); + 8001d44: 4b05 ldr r3, [pc, #20] @ (8001d5c <HAL_PWR_EnableBkUpAccess+0x1c>) + 8001d46: 681b ldr r3, [r3, #0] + 8001d48: 4a04 ldr r2, [pc, #16] @ (8001d5c <HAL_PWR_EnableBkUpAccess+0x1c>) + 8001d4a: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8001d4e: 6013 str r3, [r2, #0] +} + 8001d50: bf00 nop + 8001d52: 46bd mov sp, r7 + 8001d54: f85d 7b04 ldr.w r7, [sp], #4 + 8001d58: 4770 bx lr + 8001d5a: bf00 nop + 8001d5c: 58000400 .word 0x58000400 + +08001d60 <HAL_PWREx_GetVoltageRange>: +/** + * @brief Return Voltage Scaling Range. + * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2) + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + 8001d60: b480 push {r7} + 8001d62: af00 add r7, sp, #0 + return (PWR->CR1 & PWR_CR1_VOS); + 8001d64: 4b04 ldr r3, [pc, #16] @ (8001d78 <HAL_PWREx_GetVoltageRange+0x18>) + 8001d66: 681b ldr r3, [r3, #0] + 8001d68: f403 63c0 and.w r3, r3, #1536 @ 0x600 +} + 8001d6c: 4618 mov r0, r3 + 8001d6e: 46bd mov sp, r7 + 8001d70: f85d 7b04 ldr.w r7, [sp], #4 + 8001d74: 4770 bx lr + 8001d76: bf00 nop + 8001d78: 58000400 .word 0x58000400 + +08001d7c <HAL_PWREx_EnterSTOP2Mode>: + * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction + * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry) +{ + 8001d7c: b480 push {r7} + 8001d7e: b083 sub sp, #12 + 8001d80: af00 add r7, sp, #0 + 8001d82: 4603 mov r3, r0 + 8001d84: 71fb strb r3, [r7, #7] + /* Check the parameter */ + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Set Stop mode 2 */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP2); + 8001d86: 4b11 ldr r3, [pc, #68] @ (8001dcc <HAL_PWREx_EnterSTOP2Mode+0x50>) + 8001d88: 681b ldr r3, [r3, #0] + 8001d8a: f023 0307 bic.w r3, r3, #7 + 8001d8e: 4a0f ldr r2, [pc, #60] @ (8001dcc <HAL_PWREx_EnterSTOP2Mode+0x50>) + 8001d90: f043 0302 orr.w r3, r3, #2 + 8001d94: 6013 str r3, [r2, #0] + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 8001d96: 4b0e ldr r3, [pc, #56] @ (8001dd0 <HAL_PWREx_EnterSTOP2Mode+0x54>) + 8001d98: 691b ldr r3, [r3, #16] + 8001d9a: 4a0d ldr r2, [pc, #52] @ (8001dd0 <HAL_PWREx_EnterSTOP2Mode+0x54>) + 8001d9c: f043 0304 orr.w r3, r3, #4 + 8001da0: 6113 str r3, [r2, #16] + + /* Select Stop mode entry --------------------------------------------------*/ + if (STOPEntry == PWR_STOPENTRY_WFI) + 8001da2: 79fb ldrb r3, [r7, #7] + 8001da4: 2b01 cmp r3, #1 + 8001da6: d101 bne.n 8001dac <HAL_PWREx_EnterSTOP2Mode+0x30> + { + /* Request Wait For Interrupt */ + __WFI(); + 8001da8: bf30 wfi + 8001daa: e002 b.n 8001db2 <HAL_PWREx_EnterSTOP2Mode+0x36> + } + else + { + /* Request Wait For Event */ + __SEV(); + 8001dac: bf40 sev + __WFE(); + 8001dae: bf20 wfe + __WFE(); + 8001db0: bf20 wfe + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 8001db2: 4b07 ldr r3, [pc, #28] @ (8001dd0 <HAL_PWREx_EnterSTOP2Mode+0x54>) + 8001db4: 691b ldr r3, [r3, #16] + 8001db6: 4a06 ldr r2, [pc, #24] @ (8001dd0 <HAL_PWREx_EnterSTOP2Mode+0x54>) + 8001db8: f023 0304 bic.w r3, r3, #4 + 8001dbc: 6113 str r3, [r2, #16] +} + 8001dbe: bf00 nop + 8001dc0: 370c adds r7, #12 + 8001dc2: 46bd mov sp, r7 + 8001dc4: f85d 7b04 ldr.w r7, [sp], #4 + 8001dc8: 4770 bx lr + 8001dca: bf00 nop + 8001dcc: 58000400 .word 0x58000400 + 8001dd0: e000ed00 .word 0xe000ed00 + +08001dd4 <LL_RCC_HSE_IsEnabledDiv2>: +{ + 8001dd4: b480 push {r7} + 8001dd6: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == (RCC_CR_HSEPRE)) ? 1UL : 0UL); + 8001dd8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001ddc: 681b ldr r3, [r3, #0] + 8001dde: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8001de2: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 8001de6: d101 bne.n 8001dec <LL_RCC_HSE_IsEnabledDiv2+0x18> + 8001de8: 2301 movs r3, #1 + 8001dea: e000 b.n 8001dee <LL_RCC_HSE_IsEnabledDiv2+0x1a> + 8001dec: 2300 movs r3, #0 +} + 8001dee: 4618 mov r0, r3 + 8001df0: 46bd mov sp, r7 + 8001df2: f85d 7b04 ldr.w r7, [sp], #4 + 8001df6: 4770 bx lr + +08001df8 <LL_RCC_HSE_Enable>: +{ + 8001df8: b480 push {r7} + 8001dfa: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_HSEON); + 8001dfc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001e00: 681b ldr r3, [r3, #0] + 8001e02: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8001e06: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8001e0a: 6013 str r3, [r2, #0] +} + 8001e0c: bf00 nop + 8001e0e: 46bd mov sp, r7 + 8001e10: f85d 7b04 ldr.w r7, [sp], #4 + 8001e14: 4770 bx lr + +08001e16 <LL_RCC_HSE_Disable>: +{ + 8001e16: b480 push {r7} + 8001e18: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); + 8001e1a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001e1e: 681b ldr r3, [r3, #0] + 8001e20: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8001e24: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8001e28: 6013 str r3, [r2, #0] +} + 8001e2a: bf00 nop + 8001e2c: 46bd mov sp, r7 + 8001e2e: f85d 7b04 ldr.w r7, [sp], #4 + 8001e32: 4770 bx lr + +08001e34 <LL_RCC_HSE_IsReady>: +{ + 8001e34: b480 push {r7} + 8001e36: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); + 8001e38: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001e3c: 681b ldr r3, [r3, #0] + 8001e3e: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001e42: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 + 8001e46: d101 bne.n 8001e4c <LL_RCC_HSE_IsReady+0x18> + 8001e48: 2301 movs r3, #1 + 8001e4a: e000 b.n 8001e4e <LL_RCC_HSE_IsReady+0x1a> + 8001e4c: 2300 movs r3, #0 +} + 8001e4e: 4618 mov r0, r3 + 8001e50: 46bd mov sp, r7 + 8001e52: f85d 7b04 ldr.w r7, [sp], #4 + 8001e56: 4770 bx lr + +08001e58 <LL_RCC_HSI_Enable>: +{ + 8001e58: b480 push {r7} + 8001e5a: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_HSION); + 8001e5c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001e60: 681b ldr r3, [r3, #0] + 8001e62: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8001e66: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8001e6a: 6013 str r3, [r2, #0] +} + 8001e6c: bf00 nop + 8001e6e: 46bd mov sp, r7 + 8001e70: f85d 7b04 ldr.w r7, [sp], #4 + 8001e74: 4770 bx lr + +08001e76 <LL_RCC_HSI_Disable>: +{ + 8001e76: b480 push {r7} + 8001e78: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_HSION); + 8001e7a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001e7e: 681b ldr r3, [r3, #0] + 8001e80: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8001e84: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8001e88: 6013 str r3, [r2, #0] +} + 8001e8a: bf00 nop + 8001e8c: 46bd mov sp, r7 + 8001e8e: f85d 7b04 ldr.w r7, [sp], #4 + 8001e92: 4770 bx lr + +08001e94 <LL_RCC_HSI_IsReady>: +{ + 8001e94: b480 push {r7} + 8001e96: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL); + 8001e98: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001e9c: 681b ldr r3, [r3, #0] + 8001e9e: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8001ea2: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8001ea6: d101 bne.n 8001eac <LL_RCC_HSI_IsReady+0x18> + 8001ea8: 2301 movs r3, #1 + 8001eaa: e000 b.n 8001eae <LL_RCC_HSI_IsReady+0x1a> + 8001eac: 2300 movs r3, #0 +} + 8001eae: 4618 mov r0, r3 + 8001eb0: 46bd mov sp, r7 + 8001eb2: f85d 7b04 ldr.w r7, [sp], #4 + 8001eb6: 4770 bx lr + +08001eb8 <LL_RCC_HSI_SetCalibTrimming>: +{ + 8001eb8: b480 push {r7} + 8001eba: b083 sub sp, #12 + 8001ebc: af00 add r7, sp, #0 + 8001ebe: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos); + 8001ec0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001ec4: 685b ldr r3, [r3, #4] + 8001ec6: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 + 8001eca: 687b ldr r3, [r7, #4] + 8001ecc: 061b lsls r3, r3, #24 + 8001ece: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8001ed2: 4313 orrs r3, r2 + 8001ed4: 604b str r3, [r1, #4] +} + 8001ed6: bf00 nop + 8001ed8: 370c adds r7, #12 + 8001eda: 46bd mov sp, r7 + 8001edc: f85d 7b04 ldr.w r7, [sp], #4 + 8001ee0: 4770 bx lr + +08001ee2 <LL_RCC_HSI48_Enable>: +{ + 8001ee2: b480 push {r7} + 8001ee4: af00 add r7, sp, #0 + SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); + 8001ee6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001eea: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 + 8001eee: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8001ef2: f043 0301 orr.w r3, r3, #1 + 8001ef6: f8c2 3098 str.w r3, [r2, #152] @ 0x98 +} + 8001efa: bf00 nop + 8001efc: 46bd mov sp, r7 + 8001efe: f85d 7b04 ldr.w r7, [sp], #4 + 8001f02: 4770 bx lr + +08001f04 <LL_RCC_HSI48_Disable>: +{ + 8001f04: b480 push {r7} + 8001f06: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); + 8001f08: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001f0c: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 + 8001f10: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8001f14: f023 0301 bic.w r3, r3, #1 + 8001f18: f8c2 3098 str.w r3, [r2, #152] @ 0x98 +} + 8001f1c: bf00 nop + 8001f1e: 46bd mov sp, r7 + 8001f20: f85d 7b04 ldr.w r7, [sp], #4 + 8001f24: 4770 bx lr + +08001f26 <LL_RCC_HSI48_IsReady>: +{ + 8001f26: b480 push {r7} + 8001f28: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)) ? 1UL : 0UL); + 8001f2a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001f2e: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 + 8001f32: f003 0302 and.w r3, r3, #2 + 8001f36: 2b02 cmp r3, #2 + 8001f38: d101 bne.n 8001f3e <LL_RCC_HSI48_IsReady+0x18> + 8001f3a: 2301 movs r3, #1 + 8001f3c: e000 b.n 8001f40 <LL_RCC_HSI48_IsReady+0x1a> + 8001f3e: 2300 movs r3, #0 +} + 8001f40: 4618 mov r0, r3 + 8001f42: 46bd mov sp, r7 + 8001f44: f85d 7b04 ldr.w r7, [sp], #4 + 8001f48: 4770 bx lr + +08001f4a <LL_RCC_LSE_Enable>: +{ + 8001f4a: b480 push {r7} + 8001f4c: af00 add r7, sp, #0 + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); + 8001f4e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001f52: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8001f56: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8001f5a: f043 0301 orr.w r3, r3, #1 + 8001f5e: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 8001f62: bf00 nop + 8001f64: 46bd mov sp, r7 + 8001f66: f85d 7b04 ldr.w r7, [sp], #4 + 8001f6a: 4770 bx lr + +08001f6c <LL_RCC_LSE_Disable>: +{ + 8001f6c: b480 push {r7} + 8001f6e: af00 add r7, sp, #0 + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); + 8001f70: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001f74: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8001f78: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8001f7c: f023 0301 bic.w r3, r3, #1 + 8001f80: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 8001f84: bf00 nop + 8001f86: 46bd mov sp, r7 + 8001f88: f85d 7b04 ldr.w r7, [sp], #4 + 8001f8c: 4770 bx lr + +08001f8e <LL_RCC_LSE_EnableBypass>: +{ + 8001f8e: b480 push {r7} + 8001f90: af00 add r7, sp, #0 + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); + 8001f92: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001f96: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8001f9a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8001f9e: f043 0304 orr.w r3, r3, #4 + 8001fa2: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 8001fa6: bf00 nop + 8001fa8: 46bd mov sp, r7 + 8001faa: f85d 7b04 ldr.w r7, [sp], #4 + 8001fae: 4770 bx lr + +08001fb0 <LL_RCC_LSE_DisableBypass>: +{ + 8001fb0: b480 push {r7} + 8001fb2: af00 add r7, sp, #0 + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); + 8001fb4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001fb8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8001fbc: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8001fc0: f023 0304 bic.w r3, r3, #4 + 8001fc4: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 8001fc8: bf00 nop + 8001fca: 46bd mov sp, r7 + 8001fcc: f85d 7b04 ldr.w r7, [sp], #4 + 8001fd0: 4770 bx lr + +08001fd2 <LL_RCC_LSE_IsReady>: +{ + 8001fd2: b480 push {r7} + 8001fd4: af00 add r7, sp, #0 + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); + 8001fd6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001fda: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8001fde: f003 0302 and.w r3, r3, #2 + 8001fe2: 2b02 cmp r3, #2 + 8001fe4: d101 bne.n 8001fea <LL_RCC_LSE_IsReady+0x18> + 8001fe6: 2301 movs r3, #1 + 8001fe8: e000 b.n 8001fec <LL_RCC_LSE_IsReady+0x1a> + 8001fea: 2300 movs r3, #0 +} + 8001fec: 4618 mov r0, r3 + 8001fee: 46bd mov sp, r7 + 8001ff0: f85d 7b04 ldr.w r7, [sp], #4 + 8001ff4: 4770 bx lr + +08001ff6 <LL_RCC_LSI1_Enable>: +{ + 8001ff6: b480 push {r7} + 8001ff8: af00 add r7, sp, #0 + SET_BIT(RCC->CSR, RCC_CSR_LSI1ON); + 8001ffa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8001ffe: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8002002: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002006: f043 0301 orr.w r3, r3, #1 + 800200a: f8c2 3094 str.w r3, [r2, #148] @ 0x94 +} + 800200e: bf00 nop + 8002010: 46bd mov sp, r7 + 8002012: f85d 7b04 ldr.w r7, [sp], #4 + 8002016: 4770 bx lr + +08002018 <LL_RCC_LSI1_Disable>: +{ + 8002018: b480 push {r7} + 800201a: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CSR, RCC_CSR_LSI1ON); + 800201c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002020: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8002024: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002028: f023 0301 bic.w r3, r3, #1 + 800202c: f8c2 3094 str.w r3, [r2, #148] @ 0x94 +} + 8002030: bf00 nop + 8002032: 46bd mov sp, r7 + 8002034: f85d 7b04 ldr.w r7, [sp], #4 + 8002038: 4770 bx lr + +0800203a <LL_RCC_LSI1_IsReady>: +{ + 800203a: b480 push {r7} + 800203c: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CSR, RCC_CSR_LSI1RDY) == (RCC_CSR_LSI1RDY)) ? 1UL : 0UL); + 800203e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002042: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8002046: f003 0302 and.w r3, r3, #2 + 800204a: 2b02 cmp r3, #2 + 800204c: d101 bne.n 8002052 <LL_RCC_LSI1_IsReady+0x18> + 800204e: 2301 movs r3, #1 + 8002050: e000 b.n 8002054 <LL_RCC_LSI1_IsReady+0x1a> + 8002052: 2300 movs r3, #0 +} + 8002054: 4618 mov r0, r3 + 8002056: 46bd mov sp, r7 + 8002058: f85d 7b04 ldr.w r7, [sp], #4 + 800205c: 4770 bx lr + +0800205e <LL_RCC_LSI2_Enable>: +{ + 800205e: b480 push {r7} + 8002060: af00 add r7, sp, #0 + SET_BIT(RCC->CSR, RCC_CSR_LSI2ON); + 8002062: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002066: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 800206a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 800206e: f043 0304 orr.w r3, r3, #4 + 8002072: f8c2 3094 str.w r3, [r2, #148] @ 0x94 +} + 8002076: bf00 nop + 8002078: 46bd mov sp, r7 + 800207a: f85d 7b04 ldr.w r7, [sp], #4 + 800207e: 4770 bx lr + +08002080 <LL_RCC_LSI2_Disable>: +{ + 8002080: b480 push {r7} + 8002082: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CSR, RCC_CSR_LSI2ON); + 8002084: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002088: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 800208c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002090: f023 0304 bic.w r3, r3, #4 + 8002094: f8c2 3094 str.w r3, [r2, #148] @ 0x94 +} + 8002098: bf00 nop + 800209a: 46bd mov sp, r7 + 800209c: f85d 7b04 ldr.w r7, [sp], #4 + 80020a0: 4770 bx lr + +080020a2 <LL_RCC_LSI2_IsReady>: +{ + 80020a2: b480 push {r7} + 80020a4: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CSR, RCC_CSR_LSI2RDY) == (RCC_CSR_LSI2RDY)) ? 1UL : 0UL); + 80020a6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80020aa: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 80020ae: f003 0308 and.w r3, r3, #8 + 80020b2: 2b08 cmp r3, #8 + 80020b4: d101 bne.n 80020ba <LL_RCC_LSI2_IsReady+0x18> + 80020b6: 2301 movs r3, #1 + 80020b8: e000 b.n 80020bc <LL_RCC_LSI2_IsReady+0x1a> + 80020ba: 2300 movs r3, #0 +} + 80020bc: 4618 mov r0, r3 + 80020be: 46bd mov sp, r7 + 80020c0: f85d 7b04 ldr.w r7, [sp], #4 + 80020c4: 4770 bx lr + +080020c6 <LL_RCC_LSI2_SetTrimming>: +{ + 80020c6: b480 push {r7} + 80020c8: b083 sub sp, #12 + 80020ca: af00 add r7, sp, #0 + 80020cc: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CSR, RCC_CSR_LSI2TRIM, Value << RCC_CSR_LSI2TRIM_Pos); + 80020ce: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80020d2: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 80020d6: f423 6270 bic.w r2, r3, #3840 @ 0xf00 + 80020da: 687b ldr r3, [r7, #4] + 80020dc: 021b lsls r3, r3, #8 + 80020de: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80020e2: 4313 orrs r3, r2 + 80020e4: f8c1 3094 str.w r3, [r1, #148] @ 0x94 +} + 80020e8: bf00 nop + 80020ea: 370c adds r7, #12 + 80020ec: 46bd mov sp, r7 + 80020ee: f85d 7b04 ldr.w r7, [sp], #4 + 80020f2: 4770 bx lr + +080020f4 <LL_RCC_MSI_Enable>: +{ + 80020f4: b480 push {r7} + 80020f6: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_MSION); + 80020f8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80020fc: 681b ldr r3, [r3, #0] + 80020fe: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002102: f043 0301 orr.w r3, r3, #1 + 8002106: 6013 str r3, [r2, #0] +} + 8002108: bf00 nop + 800210a: 46bd mov sp, r7 + 800210c: f85d 7b04 ldr.w r7, [sp], #4 + 8002110: 4770 bx lr + +08002112 <LL_RCC_MSI_Disable>: +{ + 8002112: b480 push {r7} + 8002114: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_MSION); + 8002116: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800211a: 681b ldr r3, [r3, #0] + 800211c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002120: f023 0301 bic.w r3, r3, #1 + 8002124: 6013 str r3, [r2, #0] +} + 8002126: bf00 nop + 8002128: 46bd mov sp, r7 + 800212a: f85d 7b04 ldr.w r7, [sp], #4 + 800212e: 4770 bx lr + +08002130 <LL_RCC_MSI_IsReady>: +{ + 8002130: b480 push {r7} + 8002132: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)) ? 1UL : 0UL); + 8002134: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002138: 681b ldr r3, [r3, #0] + 800213a: f003 0302 and.w r3, r3, #2 + 800213e: 2b02 cmp r3, #2 + 8002140: d101 bne.n 8002146 <LL_RCC_MSI_IsReady+0x16> + 8002142: 2301 movs r3, #1 + 8002144: e000 b.n 8002148 <LL_RCC_MSI_IsReady+0x18> + 8002146: 2300 movs r3, #0 +} + 8002148: 4618 mov r0, r3 + 800214a: 46bd mov sp, r7 + 800214c: f85d 7b04 ldr.w r7, [sp], #4 + 8002150: 4770 bx lr + +08002152 <LL_RCC_MSI_SetRange>: +{ + 8002152: b480 push {r7} + 8002154: b083 sub sp, #12 + 8002156: af00 add r7, sp, #0 + 8002158: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range); + 800215a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800215e: 681b ldr r3, [r3, #0] + 8002160: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 8002164: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002168: 687b ldr r3, [r7, #4] + 800216a: 4313 orrs r3, r2 + 800216c: 600b str r3, [r1, #0] +} + 800216e: bf00 nop + 8002170: 370c adds r7, #12 + 8002172: 46bd mov sp, r7 + 8002174: f85d 7b04 ldr.w r7, [sp], #4 + 8002178: 4770 bx lr + +0800217a <LL_RCC_MSI_GetRange>: +{ + 800217a: b480 push {r7} + 800217c: b083 sub sp, #12 + 800217e: af00 add r7, sp, #0 + uint32_t msiRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE); + 8002180: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002184: 681b ldr r3, [r3, #0] + 8002186: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 800218a: 607b str r3, [r7, #4] + if (msiRange > LL_RCC_MSIRANGE_11) + 800218c: 687b ldr r3, [r7, #4] + 800218e: 2bb0 cmp r3, #176 @ 0xb0 + 8002190: d901 bls.n 8002196 <LL_RCC_MSI_GetRange+0x1c> + msiRange = LL_RCC_MSIRANGE_11; + 8002192: 23b0 movs r3, #176 @ 0xb0 + 8002194: 607b str r3, [r7, #4] + return msiRange; + 8002196: 687b ldr r3, [r7, #4] +} + 8002198: 4618 mov r0, r3 + 800219a: 370c adds r7, #12 + 800219c: 46bd mov sp, r7 + 800219e: f85d 7b04 ldr.w r7, [sp], #4 + 80021a2: 4770 bx lr + +080021a4 <LL_RCC_MSI_SetCalibTrimming>: +{ + 80021a4: b480 push {r7} + 80021a6: b083 sub sp, #12 + 80021a8: af00 add r7, sp, #0 + 80021aa: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos); + 80021ac: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80021b0: 685b ldr r3, [r3, #4] + 80021b2: f423 427f bic.w r2, r3, #65280 @ 0xff00 + 80021b6: 687b ldr r3, [r7, #4] + 80021b8: 021b lsls r3, r3, #8 + 80021ba: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80021be: 4313 orrs r3, r2 + 80021c0: 604b str r3, [r1, #4] +} + 80021c2: bf00 nop + 80021c4: 370c adds r7, #12 + 80021c6: 46bd mov sp, r7 + 80021c8: f85d 7b04 ldr.w r7, [sp], #4 + 80021cc: 4770 bx lr + +080021ce <LL_RCC_SetSysClkSource>: +{ + 80021ce: b480 push {r7} + 80021d0: b083 sub sp, #12 + 80021d2: af00 add r7, sp, #0 + 80021d4: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); + 80021d6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80021da: 689b ldr r3, [r3, #8] + 80021dc: f023 0203 bic.w r2, r3, #3 + 80021e0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80021e4: 687b ldr r3, [r7, #4] + 80021e6: 4313 orrs r3, r2 + 80021e8: 608b str r3, [r1, #8] +} + 80021ea: bf00 nop + 80021ec: 370c adds r7, #12 + 80021ee: 46bd mov sp, r7 + 80021f0: f85d 7b04 ldr.w r7, [sp], #4 + 80021f4: 4770 bx lr + +080021f6 <LL_RCC_GetSysClkSource>: +{ + 80021f6: b480 push {r7} + 80021f8: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); + 80021fa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80021fe: 689b ldr r3, [r3, #8] + 8002200: f003 030c and.w r3, r3, #12 +} + 8002204: 4618 mov r0, r3 + 8002206: 46bd mov sp, r7 + 8002208: f85d 7b04 ldr.w r7, [sp], #4 + 800220c: 4770 bx lr + +0800220e <LL_RCC_SetAHBPrescaler>: +{ + 800220e: b480 push {r7} + 8002210: b083 sub sp, #12 + 8002212: af00 add r7, sp, #0 + 8002214: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); + 8002216: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800221a: 689b ldr r3, [r3, #8] + 800221c: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 8002220: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002224: 687b ldr r3, [r7, #4] + 8002226: 4313 orrs r3, r2 + 8002228: 608b str r3, [r1, #8] +} + 800222a: bf00 nop + 800222c: 370c adds r7, #12 + 800222e: 46bd mov sp, r7 + 8002230: f85d 7b04 ldr.w r7, [sp], #4 + 8002234: 4770 bx lr + +08002236 <LL_C2_RCC_SetAHBPrescaler>: +{ + 8002236: b480 push {r7} + 8002238: b083 sub sp, #12 + 800223a: af00 add r7, sp, #0 + 800223c: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE, Prescaler); + 800223e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002242: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 + 8002246: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 800224a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800224e: 687b ldr r3, [r7, #4] + 8002250: 4313 orrs r3, r2 + 8002252: f8c1 3108 str.w r3, [r1, #264] @ 0x108 +} + 8002256: bf00 nop + 8002258: 370c adds r7, #12 + 800225a: 46bd mov sp, r7 + 800225c: f85d 7b04 ldr.w r7, [sp], #4 + 8002260: 4770 bx lr + +08002262 <LL_RCC_SetAHB4Prescaler>: +{ + 8002262: b480 push {r7} + 8002264: b083 sub sp, #12 + 8002266: af00 add r7, sp, #0 + 8002268: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE, Prescaler >> 4); + 800226a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800226e: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 + 8002272: f023 020f bic.w r2, r3, #15 + 8002276: 687b ldr r3, [r7, #4] + 8002278: 091b lsrs r3, r3, #4 + 800227a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800227e: 4313 orrs r3, r2 + 8002280: f8c1 3108 str.w r3, [r1, #264] @ 0x108 +} + 8002284: bf00 nop + 8002286: 370c adds r7, #12 + 8002288: 46bd mov sp, r7 + 800228a: f85d 7b04 ldr.w r7, [sp], #4 + 800228e: 4770 bx lr + +08002290 <LL_RCC_SetAPB1Prescaler>: +{ + 8002290: b480 push {r7} + 8002292: b083 sub sp, #12 + 8002294: af00 add r7, sp, #0 + 8002296: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); + 8002298: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800229c: 689b ldr r3, [r3, #8] + 800229e: f423 62e0 bic.w r2, r3, #1792 @ 0x700 + 80022a2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80022a6: 687b ldr r3, [r7, #4] + 80022a8: 4313 orrs r3, r2 + 80022aa: 608b str r3, [r1, #8] +} + 80022ac: bf00 nop + 80022ae: 370c adds r7, #12 + 80022b0: 46bd mov sp, r7 + 80022b2: f85d 7b04 ldr.w r7, [sp], #4 + 80022b6: 4770 bx lr + +080022b8 <LL_RCC_SetAPB2Prescaler>: +{ + 80022b8: b480 push {r7} + 80022ba: b083 sub sp, #12 + 80022bc: af00 add r7, sp, #0 + 80022be: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); + 80022c0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80022c4: 689b ldr r3, [r3, #8] + 80022c6: f423 5260 bic.w r2, r3, #14336 @ 0x3800 + 80022ca: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80022ce: 687b ldr r3, [r7, #4] + 80022d0: 4313 orrs r3, r2 + 80022d2: 608b str r3, [r1, #8] +} + 80022d4: bf00 nop + 80022d6: 370c adds r7, #12 + 80022d8: 46bd mov sp, r7 + 80022da: f85d 7b04 ldr.w r7, [sp], #4 + 80022de: 4770 bx lr + +080022e0 <LL_RCC_GetAHBPrescaler>: +{ + 80022e0: b480 push {r7} + 80022e2: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); + 80022e4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80022e8: 689b ldr r3, [r3, #8] + 80022ea: f003 03f0 and.w r3, r3, #240 @ 0xf0 +} + 80022ee: 4618 mov r0, r3 + 80022f0: 46bd mov sp, r7 + 80022f2: f85d 7b04 ldr.w r7, [sp], #4 + 80022f6: 4770 bx lr + +080022f8 <LL_RCC_GetAHB4Prescaler>: +{ + 80022f8: b480 push {r7} + 80022fa: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE) << 4); + 80022fc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002300: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 + 8002304: 011b lsls r3, r3, #4 + 8002306: f003 03f0 and.w r3, r3, #240 @ 0xf0 +} + 800230a: 4618 mov r0, r3 + 800230c: 46bd mov sp, r7 + 800230e: f85d 7b04 ldr.w r7, [sp], #4 + 8002312: 4770 bx lr + +08002314 <LL_RCC_PLL_Enable>: + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + 8002314: b480 push {r7} + 8002316: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_PLLON); + 8002318: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800231c: 681b ldr r3, [r3, #0] + 800231e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002322: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 + 8002326: 6013 str r3, [r2, #0] +} + 8002328: bf00 nop + 800232a: 46bd mov sp, r7 + 800232c: f85d 7b04 ldr.w r7, [sp], #4 + 8002330: 4770 bx lr + +08002332 <LL_RCC_PLL_Disable>: + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + 8002332: b480 push {r7} + 8002334: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + 8002336: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800233a: 681b ldr r3, [r3, #0] + 800233c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002340: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 + 8002344: 6013 str r3, [r2, #0] +} + 8002346: bf00 nop + 8002348: 46bd mov sp, r7 + 800234a: f85d 7b04 ldr.w r7, [sp], #4 + 800234e: 4770 bx lr + +08002350 <LL_RCC_PLL_IsReady>: + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + 8002350: b480 push {r7} + 8002352: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL); + 8002354: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002358: 681b ldr r3, [r3, #0] + 800235a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 800235e: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 + 8002362: d101 bne.n 8002368 <LL_RCC_PLL_IsReady+0x18> + 8002364: 2301 movs r3, #1 + 8002366: e000 b.n 800236a <LL_RCC_PLL_IsReady+0x1a> + 8002368: 2300 movs r3, #0 +} + 800236a: 4618 mov r0, r3 + 800236c: 46bd mov sp, r7 + 800236e: f85d 7b04 ldr.w r7, [sp], #4 + 8002372: 4770 bx lr + +08002374 <LL_RCC_PLL_GetN>: + * @brief Get Main PLL multiplication factor for VCO + * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN + * @retval Between 6 and 127 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) +{ + 8002374: b480 push {r7} + 8002376: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + 8002378: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800237c: 68db ldr r3, [r3, #12] + 800237e: 0a1b lsrs r3, r3, #8 + 8002380: f003 037f and.w r3, r3, #127 @ 0x7f +} + 8002384: 4618 mov r0, r3 + 8002386: 46bd mov sp, r7 + 8002388: f85d 7b04 ldr.w r7, [sp], #4 + 800238c: 4770 bx lr + +0800238e <LL_RCC_PLL_GetR>: + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @arg @ref LL_RCC_PLLR_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) +{ + 800238e: b480 push {r7} + 8002390: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); + 8002392: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002396: 68db ldr r3, [r3, #12] + 8002398: f003 4360 and.w r3, r3, #3758096384 @ 0xe0000000 +} + 800239c: 4618 mov r0, r3 + 800239e: 46bd mov sp, r7 + 80023a0: f85d 7b04 ldr.w r7, [sp], #4 + 80023a4: 4770 bx lr + +080023a6 <LL_RCC_PLL_GetDivider>: + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) +{ + 80023a6: b480 push {r7} + 80023a8: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); + 80023aa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80023ae: 68db ldr r3, [r3, #12] + 80023b0: f003 0370 and.w r3, r3, #112 @ 0x70 +} + 80023b4: 4618 mov r0, r3 + 80023b6: 46bd mov sp, r7 + 80023b8: f85d 7b04 ldr.w r7, [sp], #4 + 80023bc: 4770 bx lr + +080023be <LL_RCC_PLL_GetMainSource>: + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + 80023be: b480 push {r7} + 80023c0: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); + 80023c2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80023c6: 68db ldr r3, [r3, #12] + 80023c8: f003 0303 and.w r3, r3, #3 +} + 80023cc: 4618 mov r0, r3 + 80023ce: 46bd mov sp, r7 + 80023d0: f85d 7b04 ldr.w r7, [sp], #4 + 80023d4: 4770 bx lr + +080023d6 <LL_RCC_IsActiveFlag_HPRE>: + * @brief Check if HCLK1 prescaler flag value has been applied or not + * @rmtoll CFGR HPREF LL_RCC_IsActiveFlag_HPRE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HPRE(void) +{ + 80023d6: b480 push {r7} + 80023d8: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CFGR, RCC_CFGR_HPREF) == (RCC_CFGR_HPREF)) ? 1UL : 0UL); + 80023da: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80023de: 689b ldr r3, [r3, #8] + 80023e0: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 80023e4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 80023e8: d101 bne.n 80023ee <LL_RCC_IsActiveFlag_HPRE+0x18> + 80023ea: 2301 movs r3, #1 + 80023ec: e000 b.n 80023f0 <LL_RCC_IsActiveFlag_HPRE+0x1a> + 80023ee: 2300 movs r3, #0 +} + 80023f0: 4618 mov r0, r3 + 80023f2: 46bd mov sp, r7 + 80023f4: f85d 7b04 ldr.w r7, [sp], #4 + 80023f8: 4770 bx lr + +080023fa <LL_RCC_IsActiveFlag_C2HPRE>: + * @brief Check if HCLK2 prescaler flag value has been applied or not + * @rmtoll EXTCFGR C2HPREF LL_RCC_IsActiveFlag_C2HPRE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_C2HPRE(void) +{ + 80023fa: b480 push {r7} + 80023fc: af00 add r7, sp, #0 + return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPREF) == (RCC_EXTCFGR_C2HPREF)) ? 1UL : 0UL); + 80023fe: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002402: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 + 8002406: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 800240a: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 + 800240e: d101 bne.n 8002414 <LL_RCC_IsActiveFlag_C2HPRE+0x1a> + 8002410: 2301 movs r3, #1 + 8002412: e000 b.n 8002416 <LL_RCC_IsActiveFlag_C2HPRE+0x1c> + 8002414: 2300 movs r3, #0 +} + 8002416: 4618 mov r0, r3 + 8002418: 46bd mov sp, r7 + 800241a: f85d 7b04 ldr.w r7, [sp], #4 + 800241e: 4770 bx lr + +08002420 <LL_RCC_IsActiveFlag_SHDHPRE>: + * @brief Check if HCLK4 prescaler flag value has been applied or not + * @rmtoll EXTCFGR SHDHPREF LL_RCC_IsActiveFlag_SHDHPRE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHDHPRE(void) +{ + 8002420: b480 push {r7} + 8002422: af00 add r7, sp, #0 + return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPREF) == (RCC_EXTCFGR_SHDHPREF)) ? 1UL : 0UL); + 8002424: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002428: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 + 800242c: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8002430: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8002434: d101 bne.n 800243a <LL_RCC_IsActiveFlag_SHDHPRE+0x1a> + 8002436: 2301 movs r3, #1 + 8002438: e000 b.n 800243c <LL_RCC_IsActiveFlag_SHDHPRE+0x1c> + 800243a: 2300 movs r3, #0 +} + 800243c: 4618 mov r0, r3 + 800243e: 46bd mov sp, r7 + 8002440: f85d 7b04 ldr.w r7, [sp], #4 + 8002444: 4770 bx lr + +08002446 <LL_RCC_IsActiveFlag_PPRE1>: + * @brief Check if PLCK1 prescaler flag value has been applied or not + * @rmtoll CFGR PPRE1F LL_RCC_IsActiveFlag_PPRE1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE1(void) +{ + 8002446: b480 push {r7} + 8002448: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1F) == (RCC_CFGR_PPRE1F)) ? 1UL : 0UL); + 800244a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800244e: 689b ldr r3, [r3, #8] + 8002450: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8002454: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 + 8002458: d101 bne.n 800245e <LL_RCC_IsActiveFlag_PPRE1+0x18> + 800245a: 2301 movs r3, #1 + 800245c: e000 b.n 8002460 <LL_RCC_IsActiveFlag_PPRE1+0x1a> + 800245e: 2300 movs r3, #0 +} + 8002460: 4618 mov r0, r3 + 8002462: 46bd mov sp, r7 + 8002464: f85d 7b04 ldr.w r7, [sp], #4 + 8002468: 4770 bx lr + +0800246a <LL_RCC_IsActiveFlag_PPRE2>: + * @brief Check if PLCK2 prescaler flag value has been applied or not + * @rmtoll CFGR PPRE2F LL_RCC_IsActiveFlag_PPRE2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE2(void) +{ + 800246a: b480 push {r7} + 800246c: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2F) == (RCC_CFGR_PPRE2F)) ? 1UL : 0UL); + 800246e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002472: 689b ldr r3, [r3, #8] + 8002474: f403 2380 and.w r3, r3, #262144 @ 0x40000 + 8002478: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 + 800247c: d101 bne.n 8002482 <LL_RCC_IsActiveFlag_PPRE2+0x18> + 800247e: 2301 movs r3, #1 + 8002480: e000 b.n 8002484 <LL_RCC_IsActiveFlag_PPRE2+0x1a> + 8002482: 2300 movs r3, #0 +} + 8002484: 4618 mov r0, r3 + 8002486: 46bd mov sp, r7 + 8002488: f85d 7b04 ldr.w r7, [sp], #4 + 800248c: 4770 bx lr + ... + +08002490 <HAL_RCC_OscConfig>: + * @note The PLL is not disabled when used as system clock. + * @note The PLL source is not updated when used as PLLSAI1 clock source. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8002490: b590 push {r4, r7, lr} + 8002492: b08d sub sp, #52 @ 0x34 + 8002494: af00 add r7, sp, #0 + 8002496: 6078 str r0, [r7, #4] + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + 8002498: 687b ldr r3, [r7, #4] + 800249a: 2b00 cmp r3, #0 + 800249c: d101 bne.n 80024a2 <HAL_RCC_OscConfig+0x12> + { + return HAL_ERROR; + 800249e: 2301 movs r3, #1 + 80024a0: e363 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*----------------------------- MSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + 80024a2: 687b ldr r3, [r7, #4] + 80024a4: 681b ldr r3, [r3, #0] + 80024a6: f003 0320 and.w r3, r3, #32 + 80024aa: 2b00 cmp r3, #0 + 80024ac: f000 808d beq.w 80025ca <HAL_RCC_OscConfig+0x13a> + assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); + assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* When the MSI is used as system clock it will not be disabled */ + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 80024b0: f7ff fea1 bl 80021f6 <LL_RCC_GetSysClkSource> + 80024b4: 62f8 str r0, [r7, #44] @ 0x2c + const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE(); + 80024b6: f7ff ff82 bl 80023be <LL_RCC_PLL_GetMainSource> + 80024ba: 62b8 str r0, [r7, #40] @ 0x28 + if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_MSI) || + 80024bc: 6afb ldr r3, [r7, #44] @ 0x2c + 80024be: 2b00 cmp r3, #0 + 80024c0: d005 beq.n 80024ce <HAL_RCC_OscConfig+0x3e> + 80024c2: 6afb ldr r3, [r7, #44] @ 0x2c + 80024c4: 2b0c cmp r3, #12 + 80024c6: d147 bne.n 8002558 <HAL_RCC_OscConfig+0xc8> + ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_MSI))) + 80024c8: 6abb ldr r3, [r7, #40] @ 0x28 + 80024ca: 2b01 cmp r3, #1 + 80024cc: d144 bne.n 8002558 <HAL_RCC_OscConfig+0xc8> + { + if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF) + 80024ce: 687b ldr r3, [r7, #4] + 80024d0: 69db ldr r3, [r3, #28] + 80024d2: 2b00 cmp r3, #0 + 80024d4: d101 bne.n 80024da <HAL_RCC_OscConfig+0x4a> + { + return HAL_ERROR; + 80024d6: 2301 movs r3, #1 + 80024d8: e347 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + else + { + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the AHB4 clock + and the supply voltage of the device. */ + if (RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) + 80024da: 687b ldr r3, [r7, #4] + 80024dc: 6a5c ldr r4, [r3, #36] @ 0x24 + 80024de: f7ff fe4c bl 800217a <LL_RCC_MSI_GetRange> + 80024e2: 4603 mov r3, r0 + 80024e4: 429c cmp r4, r3 + 80024e6: d914 bls.n 8002512 <HAL_RCC_OscConfig+0x82> + { + /* First increase number of wait states update if necessary */ + if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 80024e8: 687b ldr r3, [r7, #4] + 80024ea: 6a5b ldr r3, [r3, #36] @ 0x24 + 80024ec: 4618 mov r0, r3 + 80024ee: f000 fd03 bl 8002ef8 <RCC_SetFlashLatencyFromMSIRange> + 80024f2: 4603 mov r3, r0 + 80024f4: 2b00 cmp r3, #0 + 80024f6: d001 beq.n 80024fc <HAL_RCC_OscConfig+0x6c> + { + return HAL_ERROR; + 80024f8: 2301 movs r3, #1 + 80024fa: e336 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + } + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 80024fc: 687b ldr r3, [r7, #4] + 80024fe: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002500: 4618 mov r0, r3 + 8002502: f7ff fe26 bl 8002152 <LL_RCC_MSI_SetRange> + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8002506: 687b ldr r3, [r7, #4] + 8002508: 6a1b ldr r3, [r3, #32] + 800250a: 4618 mov r0, r3 + 800250c: f7ff fe4a bl 80021a4 <LL_RCC_MSI_SetCalibTrimming> + 8002510: e013 b.n 800253a <HAL_RCC_OscConfig+0xaa> + } + else + { + /* Else, keep current flash latency while decreasing applies */ + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8002512: 687b ldr r3, [r7, #4] + 8002514: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002516: 4618 mov r0, r3 + 8002518: f7ff fe1b bl 8002152 <LL_RCC_MSI_SetRange> + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 800251c: 687b ldr r3, [r7, #4] + 800251e: 6a1b ldr r3, [r3, #32] + 8002520: 4618 mov r0, r3 + 8002522: f7ff fe3f bl 80021a4 <LL_RCC_MSI_SetCalibTrimming> + + /* Decrease number of wait states update if necessary */ + if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 8002526: 687b ldr r3, [r7, #4] + 8002528: 6a5b ldr r3, [r3, #36] @ 0x24 + 800252a: 4618 mov r0, r3 + 800252c: f000 fce4 bl 8002ef8 <RCC_SetFlashLatencyFromMSIRange> + 8002530: 4603 mov r3, r0 + 8002532: 2b00 cmp r3, #0 + 8002534: d001 beq.n 800253a <HAL_RCC_OscConfig+0xaa> + { + return HAL_ERROR; + 8002536: 2301 movs r3, #1 + 8002538: e317 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetHCLKFreq(); + 800253a: f000 fcc9 bl 8002ed0 <HAL_RCC_GetHCLKFreq> + 800253e: 4603 mov r3, r0 + 8002540: 4aa4 ldr r2, [pc, #656] @ (80027d4 <HAL_RCC_OscConfig+0x344>) + 8002542: 6013 str r3, [r2, #0] + + if (HAL_InitTick(uwTickPrio) != HAL_OK) + 8002544: 4ba4 ldr r3, [pc, #656] @ (80027d8 <HAL_RCC_OscConfig+0x348>) + 8002546: 681b ldr r3, [r3, #0] + 8002548: 4618 mov r0, r3 + 800254a: f7fe fe41 bl 80011d0 <HAL_InitTick> + 800254e: 4603 mov r3, r0 + 8002550: 2b00 cmp r3, #0 + 8002552: d039 beq.n 80025c8 <HAL_RCC_OscConfig+0x138> + { + return HAL_ERROR; + 8002554: 2301 movs r3, #1 + 8002556: e308 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + } + } + else + { + /* Check the MSI State */ + if (RCC_OscInitStruct->MSIState != RCC_MSI_OFF) + 8002558: 687b ldr r3, [r7, #4] + 800255a: 69db ldr r3, [r3, #28] + 800255c: 2b00 cmp r3, #0 + 800255e: d01e beq.n 800259e <HAL_RCC_OscConfig+0x10e> + { + /* Enable the Internal High Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + 8002560: f7ff fdc8 bl 80020f4 <LL_RCC_MSI_Enable> + + /* Get timeout */ + tickstart = HAL_GetTick(); + 8002564: f7fe fe82 bl 800126c <HAL_GetTick> + 8002568: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till MSI is ready */ + while (LL_RCC_MSI_IsReady() == 0U) + 800256a: e008 b.n 800257e <HAL_RCC_OscConfig+0xee> + { + if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 800256c: f7fe fe7e bl 800126c <HAL_GetTick> + 8002570: 4602 mov r2, r0 + 8002572: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002574: 1ad3 subs r3, r2, r3 + 8002576: 2b02 cmp r3, #2 + 8002578: d901 bls.n 800257e <HAL_RCC_OscConfig+0xee> + { + return HAL_TIMEOUT; + 800257a: 2303 movs r3, #3 + 800257c: e2f5 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_MSI_IsReady() == 0U) + 800257e: f7ff fdd7 bl 8002130 <LL_RCC_MSI_IsReady> + 8002582: 4603 mov r3, r0 + 8002584: 2b00 cmp r3, #0 + 8002586: d0f1 beq.n 800256c <HAL_RCC_OscConfig+0xdc> + } + } + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8002588: 687b ldr r3, [r7, #4] + 800258a: 6a5b ldr r3, [r3, #36] @ 0x24 + 800258c: 4618 mov r0, r3 + 800258e: f7ff fde0 bl 8002152 <LL_RCC_MSI_SetRange> + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8002592: 687b ldr r3, [r7, #4] + 8002594: 6a1b ldr r3, [r3, #32] + 8002596: 4618 mov r0, r3 + 8002598: f7ff fe04 bl 80021a4 <LL_RCC_MSI_SetCalibTrimming> + 800259c: e015 b.n 80025ca <HAL_RCC_OscConfig+0x13a> + + } + else + { + /* Disable the Internal High Speed oscillator (MSI). */ + __HAL_RCC_MSI_DISABLE(); + 800259e: f7ff fdb8 bl 8002112 <LL_RCC_MSI_Disable> + + /* Get timeout */ + tickstart = HAL_GetTick(); + 80025a2: f7fe fe63 bl 800126c <HAL_GetTick> + 80025a6: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till MSI is disabled */ + while (LL_RCC_MSI_IsReady() != 0U) + 80025a8: e008 b.n 80025bc <HAL_RCC_OscConfig+0x12c> + { + if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 80025aa: f7fe fe5f bl 800126c <HAL_GetTick> + 80025ae: 4602 mov r2, r0 + 80025b0: 6a7b ldr r3, [r7, #36] @ 0x24 + 80025b2: 1ad3 subs r3, r2, r3 + 80025b4: 2b02 cmp r3, #2 + 80025b6: d901 bls.n 80025bc <HAL_RCC_OscConfig+0x12c> + { + return HAL_TIMEOUT; + 80025b8: 2303 movs r3, #3 + 80025ba: e2d6 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_MSI_IsReady() != 0U) + 80025bc: f7ff fdb8 bl 8002130 <LL_RCC_MSI_IsReady> + 80025c0: 4603 mov r3, r0 + 80025c2: 2b00 cmp r3, #0 + 80025c4: d1f1 bne.n 80025aa <HAL_RCC_OscConfig+0x11a> + 80025c6: e000 b.n 80025ca <HAL_RCC_OscConfig+0x13a> + if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF) + 80025c8: bf00 nop + } + } + } + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 80025ca: 687b ldr r3, [r7, #4] + 80025cc: 681b ldr r3, [r3, #0] + 80025ce: f003 0301 and.w r3, r3, #1 + 80025d2: 2b00 cmp r3, #0 + 80025d4: d047 beq.n 8002666 <HAL_RCC_OscConfig+0x1d6> + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 80025d6: f7ff fe0e bl 80021f6 <LL_RCC_GetSysClkSource> + 80025da: 6238 str r0, [r7, #32] + const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE(); + 80025dc: f7ff feef bl 80023be <LL_RCC_PLL_GetMainSource> + 80025e0: 61f8 str r0, [r7, #28] + if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE) || + 80025e2: 6a3b ldr r3, [r7, #32] + 80025e4: 2b08 cmp r3, #8 + 80025e6: d005 beq.n 80025f4 <HAL_RCC_OscConfig+0x164> + 80025e8: 6a3b ldr r3, [r7, #32] + 80025ea: 2b0c cmp r3, #12 + 80025ec: d108 bne.n 8002600 <HAL_RCC_OscConfig+0x170> + ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_HSE))) + 80025ee: 69fb ldr r3, [r7, #28] + 80025f0: 2b03 cmp r3, #3 + 80025f2: d105 bne.n 8002600 <HAL_RCC_OscConfig+0x170> + { + if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF) + 80025f4: 687b ldr r3, [r7, #4] + 80025f6: 685b ldr r3, [r3, #4] + 80025f8: 2b00 cmp r3, #0 + 80025fa: d134 bne.n 8002666 <HAL_RCC_OscConfig+0x1d6> + { + return HAL_ERROR; + 80025fc: 2301 movs r3, #1 + 80025fe: e2b4 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 8002600: 687b ldr r3, [r7, #4] + 8002602: 685b ldr r3, [r3, #4] + 8002604: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8002608: d102 bne.n 8002610 <HAL_RCC_OscConfig+0x180> + 800260a: f7ff fbf5 bl 8001df8 <LL_RCC_HSE_Enable> + 800260e: e001 b.n 8002614 <HAL_RCC_OscConfig+0x184> + 8002610: f7ff fc01 bl 8001e16 <LL_RCC_HSE_Disable> + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 8002614: 687b ldr r3, [r7, #4] + 8002616: 685b ldr r3, [r3, #4] + 8002618: 2b00 cmp r3, #0 + 800261a: d012 beq.n 8002642 <HAL_RCC_OscConfig+0x1b2> + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800261c: f7fe fe26 bl 800126c <HAL_GetTick> + 8002620: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till HSE is ready */ + while (LL_RCC_HSE_IsReady() == 0U) + 8002622: e008 b.n 8002636 <HAL_RCC_OscConfig+0x1a6> + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 8002624: f7fe fe22 bl 800126c <HAL_GetTick> + 8002628: 4602 mov r2, r0 + 800262a: 6a7b ldr r3, [r7, #36] @ 0x24 + 800262c: 1ad3 subs r3, r2, r3 + 800262e: 2b64 cmp r3, #100 @ 0x64 + 8002630: d901 bls.n 8002636 <HAL_RCC_OscConfig+0x1a6> + { + return HAL_TIMEOUT; + 8002632: 2303 movs r3, #3 + 8002634: e299 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_HSE_IsReady() == 0U) + 8002636: f7ff fbfd bl 8001e34 <LL_RCC_HSE_IsReady> + 800263a: 4603 mov r3, r0 + 800263c: 2b00 cmp r3, #0 + 800263e: d0f1 beq.n 8002624 <HAL_RCC_OscConfig+0x194> + 8002640: e011 b.n 8002666 <HAL_RCC_OscConfig+0x1d6> + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002642: f7fe fe13 bl 800126c <HAL_GetTick> + 8002646: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till HSE is disabled */ + while (LL_RCC_HSE_IsReady() != 0U) + 8002648: e008 b.n 800265c <HAL_RCC_OscConfig+0x1cc> + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 800264a: f7fe fe0f bl 800126c <HAL_GetTick> + 800264e: 4602 mov r2, r0 + 8002650: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002652: 1ad3 subs r3, r2, r3 + 8002654: 2b64 cmp r3, #100 @ 0x64 + 8002656: d901 bls.n 800265c <HAL_RCC_OscConfig+0x1cc> + { + return HAL_TIMEOUT; + 8002658: 2303 movs r3, #3 + 800265a: e286 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_HSE_IsReady() != 0U) + 800265c: f7ff fbea bl 8001e34 <LL_RCC_HSE_IsReady> + 8002660: 4603 mov r3, r0 + 8002662: 2b00 cmp r3, #0 + 8002664: d1f1 bne.n 800264a <HAL_RCC_OscConfig+0x1ba> + } + } + } + + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 8002666: 687b ldr r3, [r7, #4] + 8002668: 681b ldr r3, [r3, #0] + 800266a: f003 0302 and.w r3, r3, #2 + 800266e: 2b00 cmp r3, #0 + 8002670: d04c beq.n 800270c <HAL_RCC_OscConfig+0x27c> + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8002672: f7ff fdc0 bl 80021f6 <LL_RCC_GetSysClkSource> + 8002676: 61b8 str r0, [r7, #24] + const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE(); + 8002678: f7ff fea1 bl 80023be <LL_RCC_PLL_GetMainSource> + 800267c: 6178 str r0, [r7, #20] + if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) || + 800267e: 69bb ldr r3, [r7, #24] + 8002680: 2b04 cmp r3, #4 + 8002682: d005 beq.n 8002690 <HAL_RCC_OscConfig+0x200> + 8002684: 69bb ldr r3, [r7, #24] + 8002686: 2b0c cmp r3, #12 + 8002688: d10e bne.n 80026a8 <HAL_RCC_OscConfig+0x218> + ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_HSI))) + 800268a: 697b ldr r3, [r7, #20] + 800268c: 2b02 cmp r3, #2 + 800268e: d10b bne.n 80026a8 <HAL_RCC_OscConfig+0x218> + { + /* When HSI is used as system clock it will not be disabled */ + if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) + 8002690: 687b ldr r3, [r7, #4] + 8002692: 68db ldr r3, [r3, #12] + 8002694: 2b00 cmp r3, #0 + 8002696: d101 bne.n 800269c <HAL_RCC_OscConfig+0x20c> + { + return HAL_ERROR; + 8002698: 2301 movs r3, #1 + 800269a: e266 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 800269c: 687b ldr r3, [r7, #4] + 800269e: 691b ldr r3, [r3, #16] + 80026a0: 4618 mov r0, r3 + 80026a2: f7ff fc09 bl 8001eb8 <LL_RCC_HSI_SetCalibTrimming> + if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) + 80026a6: e031 b.n 800270c <HAL_RCC_OscConfig+0x27c> + } + } + else + { + /* Check the HSI State */ + if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 80026a8: 687b ldr r3, [r7, #4] + 80026aa: 68db ldr r3, [r3, #12] + 80026ac: 2b00 cmp r3, #0 + 80026ae: d019 beq.n 80026e4 <HAL_RCC_OscConfig+0x254> + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 80026b0: f7ff fbd2 bl 8001e58 <LL_RCC_HSI_Enable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80026b4: f7fe fdda bl 800126c <HAL_GetTick> + 80026b8: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till HSI is ready */ + while (LL_RCC_HSI_IsReady() == 0U) + 80026ba: e008 b.n 80026ce <HAL_RCC_OscConfig+0x23e> + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 80026bc: f7fe fdd6 bl 800126c <HAL_GetTick> + 80026c0: 4602 mov r2, r0 + 80026c2: 6a7b ldr r3, [r7, #36] @ 0x24 + 80026c4: 1ad3 subs r3, r2, r3 + 80026c6: 2b02 cmp r3, #2 + 80026c8: d901 bls.n 80026ce <HAL_RCC_OscConfig+0x23e> + { + return HAL_TIMEOUT; + 80026ca: 2303 movs r3, #3 + 80026cc: e24d b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_HSI_IsReady() == 0U) + 80026ce: f7ff fbe1 bl 8001e94 <LL_RCC_HSI_IsReady> + 80026d2: 4603 mov r3, r0 + 80026d4: 2b00 cmp r3, #0 + 80026d6: d0f1 beq.n 80026bc <HAL_RCC_OscConfig+0x22c> + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 80026d8: 687b ldr r3, [r7, #4] + 80026da: 691b ldr r3, [r3, #16] + 80026dc: 4618 mov r0, r3 + 80026de: f7ff fbeb bl 8001eb8 <LL_RCC_HSI_SetCalibTrimming> + 80026e2: e013 b.n 800270c <HAL_RCC_OscConfig+0x27c> + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 80026e4: f7ff fbc7 bl 8001e76 <LL_RCC_HSI_Disable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80026e8: f7fe fdc0 bl 800126c <HAL_GetTick> + 80026ec: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till HSI is disabled */ + while (LL_RCC_HSI_IsReady() != 0U) + 80026ee: e008 b.n 8002702 <HAL_RCC_OscConfig+0x272> + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 80026f0: f7fe fdbc bl 800126c <HAL_GetTick> + 80026f4: 4602 mov r2, r0 + 80026f6: 6a7b ldr r3, [r7, #36] @ 0x24 + 80026f8: 1ad3 subs r3, r2, r3 + 80026fa: 2b02 cmp r3, #2 + 80026fc: d901 bls.n 8002702 <HAL_RCC_OscConfig+0x272> + { + return HAL_TIMEOUT; + 80026fe: 2303 movs r3, #3 + 8002700: e233 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_HSI_IsReady() != 0U) + 8002702: f7ff fbc7 bl 8001e94 <LL_RCC_HSI_IsReady> + 8002706: 4603 mov r3, r0 + 8002708: 2b00 cmp r3, #0 + 800270a: d1f1 bne.n 80026f0 <HAL_RCC_OscConfig+0x260> + } + } + } + /*------------------------------ LSI Configuration (LSI1 or LSI2) -------------------------*/ + + if ((((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \ + 800270c: 687b ldr r3, [r7, #4] + 800270e: 681b ldr r3, [r3, #0] + 8002710: f003 0308 and.w r3, r3, #8 + 8002714: 2b00 cmp r3, #0 + 8002716: d106 bne.n 8002726 <HAL_RCC_OscConfig+0x296> + (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2)) + 8002718: 687b ldr r3, [r7, #4] + 800271a: 681b ldr r3, [r3, #0] + 800271c: f003 0310 and.w r3, r3, #16 + if ((((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \ + 8002720: 2b00 cmp r3, #0 + 8002722: f000 80a3 beq.w 800286c <HAL_RCC_OscConfig+0x3dc> + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 8002726: 687b ldr r3, [r7, #4] + 8002728: 695b ldr r3, [r3, #20] + 800272a: 2b00 cmp r3, #0 + 800272c: d076 beq.n 800281c <HAL_RCC_OscConfig+0x38c> + { + /*------------------------------ LSI2 selected by default (when Switch ON) -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2) + 800272e: 687b ldr r3, [r7, #4] + 8002730: 681b ldr r3, [r3, #0] + 8002732: f003 0310 and.w r3, r3, #16 + 8002736: 2b00 cmp r3, #0 + 8002738: d046 beq.n 80027c8 <HAL_RCC_OscConfig+0x338> + { + assert_param(IS_RCC_LSI2_CALIBRATION_VALUE(RCC_OscInitStruct->LSI2CalibrationValue)); + + /* 1. Check LSI1 state and enable if required */ + if (LL_RCC_LSI1_IsReady() == 0U) + 800273a: f7ff fc7e bl 800203a <LL_RCC_LSI1_IsReady> + 800273e: 4603 mov r3, r0 + 8002740: 2b00 cmp r3, #0 + 8002742: d113 bne.n 800276c <HAL_RCC_OscConfig+0x2dc> + { + /* This is required to enable LSI1 before enabling LSI2 */ + __HAL_RCC_LSI1_ENABLE(); + 8002744: f7ff fc57 bl 8001ff6 <LL_RCC_LSI1_Enable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002748: f7fe fd90 bl 800126c <HAL_GetTick> + 800274c: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till LSI1 is ready */ + while (LL_RCC_LSI1_IsReady() == 0U) + 800274e: e008 b.n 8002762 <HAL_RCC_OscConfig+0x2d2> + { + if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE) + 8002750: f7fe fd8c bl 800126c <HAL_GetTick> + 8002754: 4602 mov r2, r0 + 8002756: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002758: 1ad3 subs r3, r2, r3 + 800275a: 2b02 cmp r3, #2 + 800275c: d901 bls.n 8002762 <HAL_RCC_OscConfig+0x2d2> + { + return HAL_TIMEOUT; + 800275e: 2303 movs r3, #3 + 8002760: e203 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_LSI1_IsReady() == 0U) + 8002762: f7ff fc6a bl 800203a <LL_RCC_LSI1_IsReady> + 8002766: 4603 mov r3, r0 + 8002768: 2b00 cmp r3, #0 + 800276a: d0f1 beq.n 8002750 <HAL_RCC_OscConfig+0x2c0> + } + } + } + + /* 2. Enable the Internal Low Speed oscillator (LSI2) and set trimming value */ + __HAL_RCC_LSI2_ENABLE(); + 800276c: f7ff fc77 bl 800205e <LL_RCC_LSI2_Enable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002770: f7fe fd7c bl 800126c <HAL_GetTick> + 8002774: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till LSI2 is ready */ + while (LL_RCC_LSI2_IsReady() == 0U) + 8002776: e008 b.n 800278a <HAL_RCC_OscConfig+0x2fa> + { + if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE) + 8002778: f7fe fd78 bl 800126c <HAL_GetTick> + 800277c: 4602 mov r2, r0 + 800277e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002780: 1ad3 subs r3, r2, r3 + 8002782: 2b03 cmp r3, #3 + 8002784: d901 bls.n 800278a <HAL_RCC_OscConfig+0x2fa> + { + return HAL_TIMEOUT; + 8002786: 2303 movs r3, #3 + 8002788: e1ef b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_LSI2_IsReady() == 0U) + 800278a: f7ff fc8a bl 80020a2 <LL_RCC_LSI2_IsReady> + 800278e: 4603 mov r3, r0 + 8002790: 2b00 cmp r3, #0 + 8002792: d0f1 beq.n 8002778 <HAL_RCC_OscConfig+0x2e8> + } + } + /* Adjusts the Internal Low Spee oscillator (LSI2) calibration value */ + __HAL_RCC_LSI2_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->LSI2CalibrationValue); + 8002794: 687b ldr r3, [r7, #4] + 8002796: 699b ldr r3, [r3, #24] + 8002798: 4618 mov r0, r3 + 800279a: f7ff fc94 bl 80020c6 <LL_RCC_LSI2_SetTrimming> + + /* 3. Disable LSI1 */ + + /* LSI1 was initially not enable, require to disable it */ + __HAL_RCC_LSI1_DISABLE(); + 800279e: f7ff fc3b bl 8002018 <LL_RCC_LSI1_Disable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80027a2: f7fe fd63 bl 800126c <HAL_GetTick> + 80027a6: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till LSI1 is disabled */ + while (LL_RCC_LSI1_IsReady() != 0U) + 80027a8: e008 b.n 80027bc <HAL_RCC_OscConfig+0x32c> + { + if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE) + 80027aa: f7fe fd5f bl 800126c <HAL_GetTick> + 80027ae: 4602 mov r2, r0 + 80027b0: 6a7b ldr r3, [r7, #36] @ 0x24 + 80027b2: 1ad3 subs r3, r2, r3 + 80027b4: 2b02 cmp r3, #2 + 80027b6: d901 bls.n 80027bc <HAL_RCC_OscConfig+0x32c> + { + return HAL_TIMEOUT; + 80027b8: 2303 movs r3, #3 + 80027ba: e1d6 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_LSI1_IsReady() != 0U) + 80027bc: f7ff fc3d bl 800203a <LL_RCC_LSI1_IsReady> + 80027c0: 4603 mov r3, r0 + 80027c2: 2b00 cmp r3, #0 + 80027c4: d1f1 bne.n 80027aa <HAL_RCC_OscConfig+0x31a> + 80027c6: e051 b.n 800286c <HAL_RCC_OscConfig+0x3dc> + else + { + /*------------------------------ LSI1 selected (only if LSI2 OFF)-------------------------*/ + + /* 1. Enable the Internal Low Speed oscillator (LSI1). */ + __HAL_RCC_LSI1_ENABLE(); + 80027c8: f7ff fc15 bl 8001ff6 <LL_RCC_LSI1_Enable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80027cc: f7fe fd4e bl 800126c <HAL_GetTick> + 80027d0: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till LSI1 is ready */ + while (LL_RCC_LSI1_IsReady() == 0U) + 80027d2: e00c b.n 80027ee <HAL_RCC_OscConfig+0x35e> + 80027d4: 200006c8 .word 0x200006c8 + 80027d8: 200006cc .word 0x200006cc + { + if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE) + 80027dc: f7fe fd46 bl 800126c <HAL_GetTick> + 80027e0: 4602 mov r2, r0 + 80027e2: 6a7b ldr r3, [r7, #36] @ 0x24 + 80027e4: 1ad3 subs r3, r2, r3 + 80027e6: 2b02 cmp r3, #2 + 80027e8: d901 bls.n 80027ee <HAL_RCC_OscConfig+0x35e> + { + return HAL_TIMEOUT; + 80027ea: 2303 movs r3, #3 + 80027ec: e1bd b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_LSI1_IsReady() == 0U) + 80027ee: f7ff fc24 bl 800203a <LL_RCC_LSI1_IsReady> + 80027f2: 4603 mov r3, r0 + 80027f4: 2b00 cmp r3, #0 + 80027f6: d0f1 beq.n 80027dc <HAL_RCC_OscConfig+0x34c> + } + } + /*2. Switch OFF LSI2*/ + + /* Disable the Internal Low Speed oscillator (LSI2). */ + __HAL_RCC_LSI2_DISABLE(); + 80027f8: f7ff fc42 bl 8002080 <LL_RCC_LSI2_Disable> + + /* Wait till LSI2 is disabled */ + while (LL_RCC_LSI2_IsReady() != 0U) + 80027fc: e008 b.n 8002810 <HAL_RCC_OscConfig+0x380> + { + if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE) + 80027fe: f7fe fd35 bl 800126c <HAL_GetTick> + 8002802: 4602 mov r2, r0 + 8002804: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002806: 1ad3 subs r3, r2, r3 + 8002808: 2b03 cmp r3, #3 + 800280a: d901 bls.n 8002810 <HAL_RCC_OscConfig+0x380> + { + return HAL_TIMEOUT; + 800280c: 2303 movs r3, #3 + 800280e: e1ac b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_LSI2_IsReady() != 0U) + 8002810: f7ff fc47 bl 80020a2 <LL_RCC_LSI2_IsReady> + 8002814: 4603 mov r3, r0 + 8002816: 2b00 cmp r3, #0 + 8002818: d1f1 bne.n 80027fe <HAL_RCC_OscConfig+0x36e> + 800281a: e027 b.n 800286c <HAL_RCC_OscConfig+0x3dc> + } + else + { + + /* Disable the Internal Low Speed oscillator (LSI2). */ + __HAL_RCC_LSI2_DISABLE(); + 800281c: f7ff fc30 bl 8002080 <LL_RCC_LSI2_Disable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002820: f7fe fd24 bl 800126c <HAL_GetTick> + 8002824: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till LSI2 is disabled */ + while (LL_RCC_LSI2_IsReady() != 0U) + 8002826: e008 b.n 800283a <HAL_RCC_OscConfig+0x3aa> + { + if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE) + 8002828: f7fe fd20 bl 800126c <HAL_GetTick> + 800282c: 4602 mov r2, r0 + 800282e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002830: 1ad3 subs r3, r2, r3 + 8002832: 2b03 cmp r3, #3 + 8002834: d901 bls.n 800283a <HAL_RCC_OscConfig+0x3aa> + { + return HAL_TIMEOUT; + 8002836: 2303 movs r3, #3 + 8002838: e197 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_LSI2_IsReady() != 0U) + 800283a: f7ff fc32 bl 80020a2 <LL_RCC_LSI2_IsReady> + 800283e: 4603 mov r3, r0 + 8002840: 2b00 cmp r3, #0 + 8002842: d1f1 bne.n 8002828 <HAL_RCC_OscConfig+0x398> + } + } + + /* Disable the Internal Low Speed oscillator (LSI1). */ + __HAL_RCC_LSI1_DISABLE(); + 8002844: f7ff fbe8 bl 8002018 <LL_RCC_LSI1_Disable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002848: f7fe fd10 bl 800126c <HAL_GetTick> + 800284c: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till LSI1 is disabled */ + while (LL_RCC_LSI1_IsReady() != 0U) + 800284e: e008 b.n 8002862 <HAL_RCC_OscConfig+0x3d2> + { + if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE) + 8002850: f7fe fd0c bl 800126c <HAL_GetTick> + 8002854: 4602 mov r2, r0 + 8002856: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002858: 1ad3 subs r3, r2, r3 + 800285a: 2b02 cmp r3, #2 + 800285c: d901 bls.n 8002862 <HAL_RCC_OscConfig+0x3d2> + { + return HAL_TIMEOUT; + 800285e: 2303 movs r3, #3 + 8002860: e183 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_LSI1_IsReady() != 0U) + 8002862: f7ff fbea bl 800203a <LL_RCC_LSI1_IsReady> + 8002866: 4603 mov r3, r0 + 8002868: 2b00 cmp r3, #0 + 800286a: d1f1 bne.n 8002850 <HAL_RCC_OscConfig+0x3c0> + } + } + } + + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 800286c: 687b ldr r3, [r7, #4] + 800286e: 681b ldr r3, [r3, #0] + 8002870: f003 0304 and.w r3, r3, #4 + 8002874: 2b00 cmp r3, #0 + 8002876: d05b beq.n 8002930 <HAL_RCC_OscConfig+0x4a0> + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + + if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 8002878: 4ba7 ldr r3, [pc, #668] @ (8002b18 <HAL_RCC_OscConfig+0x688>) + 800287a: 681b ldr r3, [r3, #0] + 800287c: f403 7380 and.w r3, r3, #256 @ 0x100 + 8002880: 2b00 cmp r3, #0 + 8002882: d114 bne.n 80028ae <HAL_RCC_OscConfig+0x41e> + { + /* Enable write access to Backup domain */ + HAL_PWR_EnableBkUpAccess(); + 8002884: f7ff fa5c bl 8001d40 <HAL_PWR_EnableBkUpAccess> + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8002888: f7fe fcf0 bl 800126c <HAL_GetTick> + 800288c: 6278 str r0, [r7, #36] @ 0x24 + + while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 800288e: e008 b.n 80028a2 <HAL_RCC_OscConfig+0x412> + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8002890: f7fe fcec bl 800126c <HAL_GetTick> + 8002894: 4602 mov r2, r0 + 8002896: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002898: 1ad3 subs r3, r2, r3 + 800289a: 2b02 cmp r3, #2 + 800289c: d901 bls.n 80028a2 <HAL_RCC_OscConfig+0x412> + { + return HAL_TIMEOUT; + 800289e: 2303 movs r3, #3 + 80028a0: e163 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 80028a2: 4b9d ldr r3, [pc, #628] @ (8002b18 <HAL_RCC_OscConfig+0x688>) + 80028a4: 681b ldr r3, [r3, #0] + 80028a6: f403 7380 and.w r3, r3, #256 @ 0x100 + 80028aa: 2b00 cmp r3, #0 + 80028ac: d0f0 beq.n 8002890 <HAL_RCC_OscConfig+0x400> + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 80028ae: 687b ldr r3, [r7, #4] + 80028b0: 689b ldr r3, [r3, #8] + 80028b2: 2b01 cmp r3, #1 + 80028b4: d102 bne.n 80028bc <HAL_RCC_OscConfig+0x42c> + 80028b6: f7ff fb48 bl 8001f4a <LL_RCC_LSE_Enable> + 80028ba: e00c b.n 80028d6 <HAL_RCC_OscConfig+0x446> + 80028bc: 687b ldr r3, [r7, #4] + 80028be: 689b ldr r3, [r3, #8] + 80028c0: 2b05 cmp r3, #5 + 80028c2: d104 bne.n 80028ce <HAL_RCC_OscConfig+0x43e> + 80028c4: f7ff fb63 bl 8001f8e <LL_RCC_LSE_EnableBypass> + 80028c8: f7ff fb3f bl 8001f4a <LL_RCC_LSE_Enable> + 80028cc: e003 b.n 80028d6 <HAL_RCC_OscConfig+0x446> + 80028ce: f7ff fb4d bl 8001f6c <LL_RCC_LSE_Disable> + 80028d2: f7ff fb6d bl 8001fb0 <LL_RCC_LSE_DisableBypass> + + /* Check the LSE State */ + if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 80028d6: 687b ldr r3, [r7, #4] + 80028d8: 689b ldr r3, [r3, #8] + 80028da: 2b00 cmp r3, #0 + 80028dc: d014 beq.n 8002908 <HAL_RCC_OscConfig+0x478> + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80028de: f7fe fcc5 bl 800126c <HAL_GetTick> + 80028e2: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till LSE is ready */ + while (LL_RCC_LSE_IsReady() == 0U) + 80028e4: e00a b.n 80028fc <HAL_RCC_OscConfig+0x46c> + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 80028e6: f7fe fcc1 bl 800126c <HAL_GetTick> + 80028ea: 4602 mov r2, r0 + 80028ec: 6a7b ldr r3, [r7, #36] @ 0x24 + 80028ee: 1ad3 subs r3, r2, r3 + 80028f0: f241 3288 movw r2, #5000 @ 0x1388 + 80028f4: 4293 cmp r3, r2 + 80028f6: d901 bls.n 80028fc <HAL_RCC_OscConfig+0x46c> + { + return HAL_TIMEOUT; + 80028f8: 2303 movs r3, #3 + 80028fa: e136 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_LSE_IsReady() == 0U) + 80028fc: f7ff fb69 bl 8001fd2 <LL_RCC_LSE_IsReady> + 8002900: 4603 mov r3, r0 + 8002902: 2b00 cmp r3, #0 + 8002904: d0ef beq.n 80028e6 <HAL_RCC_OscConfig+0x456> + 8002906: e013 b.n 8002930 <HAL_RCC_OscConfig+0x4a0> + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002908: f7fe fcb0 bl 800126c <HAL_GetTick> + 800290c: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till LSE is disabled */ + while (LL_RCC_LSE_IsReady() != 0U) + 800290e: e00a b.n 8002926 <HAL_RCC_OscConfig+0x496> + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8002910: f7fe fcac bl 800126c <HAL_GetTick> + 8002914: 4602 mov r2, r0 + 8002916: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002918: 1ad3 subs r3, r2, r3 + 800291a: f241 3288 movw r2, #5000 @ 0x1388 + 800291e: 4293 cmp r3, r2 + 8002920: d901 bls.n 8002926 <HAL_RCC_OscConfig+0x496> + { + return HAL_TIMEOUT; + 8002922: 2303 movs r3, #3 + 8002924: e121 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_LSE_IsReady() != 0U) + 8002926: f7ff fb54 bl 8001fd2 <LL_RCC_LSE_IsReady> + 800292a: 4603 mov r3, r0 + 800292c: 2b00 cmp r3, #0 + 800292e: d1ef bne.n 8002910 <HAL_RCC_OscConfig+0x480> + } + + } +#if defined(RCC_HSI48_SUPPORT) + /*------------------------------ HSI48 Configuration -----------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + 8002930: 687b ldr r3, [r7, #4] + 8002932: 681b ldr r3, [r3, #0] + 8002934: f003 0340 and.w r3, r3, #64 @ 0x40 + 8002938: 2b00 cmp r3, #0 + 800293a: d02c beq.n 8002996 <HAL_RCC_OscConfig+0x506> + { + /* Check the parameters */ + assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + + /* Check the HSI State */ + if (RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) + 800293c: 687b ldr r3, [r7, #4] + 800293e: 6a9b ldr r3, [r3, #40] @ 0x28 + 8002940: 2b00 cmp r3, #0 + 8002942: d014 beq.n 800296e <HAL_RCC_OscConfig+0x4de> + { + /* Enable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_ENABLE(); + 8002944: f7ff facd bl 8001ee2 <LL_RCC_HSI48_Enable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002948: f7fe fc90 bl 800126c <HAL_GetTick> + 800294c: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till HSI48 is ready */ + while (LL_RCC_HSI48_IsReady() == 0U) + 800294e: e008 b.n 8002962 <HAL_RCC_OscConfig+0x4d2> + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + 8002950: f7fe fc8c bl 800126c <HAL_GetTick> + 8002954: 4602 mov r2, r0 + 8002956: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002958: 1ad3 subs r3, r2, r3 + 800295a: 2b02 cmp r3, #2 + 800295c: d901 bls.n 8002962 <HAL_RCC_OscConfig+0x4d2> + { + return HAL_TIMEOUT; + 800295e: 2303 movs r3, #3 + 8002960: e103 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_HSI48_IsReady() == 0U) + 8002962: f7ff fae0 bl 8001f26 <LL_RCC_HSI48_IsReady> + 8002966: 4603 mov r3, r0 + 8002968: 2b00 cmp r3, #0 + 800296a: d0f1 beq.n 8002950 <HAL_RCC_OscConfig+0x4c0> + 800296c: e013 b.n 8002996 <HAL_RCC_OscConfig+0x506> + } + } + else + { + /* Disable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_DISABLE(); + 800296e: f7ff fac9 bl 8001f04 <LL_RCC_HSI48_Disable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002972: f7fe fc7b bl 800126c <HAL_GetTick> + 8002976: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till HSI48 is disabled */ + while (LL_RCC_HSI48_IsReady() != 0U) + 8002978: e008 b.n 800298c <HAL_RCC_OscConfig+0x4fc> + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + 800297a: f7fe fc77 bl 800126c <HAL_GetTick> + 800297e: 4602 mov r2, r0 + 8002980: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002982: 1ad3 subs r3, r2, r3 + 8002984: 2b02 cmp r3, #2 + 8002986: d901 bls.n 800298c <HAL_RCC_OscConfig+0x4fc> + { + return HAL_TIMEOUT; + 8002988: 2303 movs r3, #3 + 800298a: e0ee b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (LL_RCC_HSI48_IsReady() != 0U) + 800298c: f7ff facb bl 8001f26 <LL_RCC_HSI48_IsReady> + 8002990: 4603 mov r3, r0 + 8002992: 2b00 cmp r3, #0 + 8002994: d1f1 bne.n 800297a <HAL_RCC_OscConfig+0x4ea> +#endif /* RCC_HSI48_SUPPORT */ + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + + if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) + 8002996: 687b ldr r3, [r7, #4] + 8002998: 6adb ldr r3, [r3, #44] @ 0x2c + 800299a: 2b00 cmp r3, #0 + 800299c: f000 80e4 beq.w 8002b68 <HAL_RCC_OscConfig+0x6d8> + { + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 80029a0: f7ff fc29 bl 80021f6 <LL_RCC_GetSysClkSource> + 80029a4: 6138 str r0, [r7, #16] + const uint32_t temp_pllconfig = RCC->PLLCFGR; + 80029a6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80029aa: 68db ldr r3, [r3, #12] + 80029ac: 60fb str r3, [r7, #12] + + /* PLL On ? */ + if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) + 80029ae: 687b ldr r3, [r7, #4] + 80029b0: 6adb ldr r3, [r3, #44] @ 0x2c + 80029b2: 2b02 cmp r3, #2 + 80029b4: f040 80b4 bne.w 8002b20 <HAL_RCC_OscConfig+0x690> + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + + /* Do nothing if PLL configuration is unchanged */ + if ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 80029b8: 68fb ldr r3, [r7, #12] + 80029ba: f003 0203 and.w r2, r3, #3 + 80029be: 687b ldr r3, [r7, #4] + 80029c0: 6b1b ldr r3, [r3, #48] @ 0x30 + 80029c2: 429a cmp r2, r3 + 80029c4: d123 bne.n 8002a0e <HAL_RCC_OscConfig+0x57e> + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 80029c6: 68fb ldr r3, [r7, #12] + 80029c8: f003 0270 and.w r2, r3, #112 @ 0x70 + 80029cc: 687b ldr r3, [r7, #4] + 80029ce: 6b5b ldr r3, [r3, #52] @ 0x34 + if ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 80029d0: 429a cmp r2, r3 + 80029d2: d11c bne.n 8002a0e <HAL_RCC_OscConfig+0x57e> + ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) || + 80029d4: 68fb ldr r3, [r7, #12] + 80029d6: 0a1b lsrs r3, r3, #8 + 80029d8: f003 027f and.w r2, r3, #127 @ 0x7f + 80029dc: 687b ldr r3, [r7, #4] + 80029de: 6b9b ldr r3, [r3, #56] @ 0x38 + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 80029e0: 429a cmp r2, r3 + 80029e2: d114 bne.n 8002a0e <HAL_RCC_OscConfig+0x57e> + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || + 80029e4: 68fb ldr r3, [r7, #12] + 80029e6: f403 1278 and.w r2, r3, #4063232 @ 0x3e0000 + 80029ea: 687b ldr r3, [r7, #4] + 80029ec: 6bdb ldr r3, [r3, #60] @ 0x3c + ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) || + 80029ee: 429a cmp r2, r3 + 80029f0: d10d bne.n 8002a0e <HAL_RCC_OscConfig+0x57e> + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || + 80029f2: 68fb ldr r3, [r7, #12] + 80029f4: f003 6260 and.w r2, r3, #234881024 @ 0xe000000 + 80029f8: 687b ldr r3, [r7, #4] + 80029fa: 6c1b ldr r3, [r3, #64] @ 0x40 + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || + 80029fc: 429a cmp r2, r3 + 80029fe: d106 bne.n 8002a0e <HAL_RCC_OscConfig+0x57e> + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) + 8002a00: 68fb ldr r3, [r7, #12] + 8002a02: f003 4260 and.w r2, r3, #3758096384 @ 0xe0000000 + 8002a06: 687b ldr r3, [r7, #4] + 8002a08: 6c5b ldr r3, [r3, #68] @ 0x44 + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || + 8002a0a: 429a cmp r2, r3 + 8002a0c: d05d beq.n 8002aca <HAL_RCC_OscConfig+0x63a> + { + /* Check if the PLL is used as system clock or not */ + if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8002a0e: 693b ldr r3, [r7, #16] + 8002a10: 2b0c cmp r3, #12 + 8002a12: d058 beq.n 8002ac6 <HAL_RCC_OscConfig+0x636> + { +#if defined(SAI1) + /* Check if main PLL can be updated */ + /* Not possible if the source is shared by other enabled PLLSAIx */ + if (READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U) + 8002a14: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002a18: 681b ldr r3, [r3, #0] + 8002a1a: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 + 8002a1e: 2b00 cmp r3, #0 + 8002a20: d001 beq.n 8002a26 <HAL_RCC_OscConfig+0x596> + + { + return HAL_ERROR; + 8002a22: 2301 movs r3, #1 + 8002a24: e0a1 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + } + else +#endif /* SAI1 */ + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8002a26: f7ff fc84 bl 8002332 <LL_RCC_PLL_Disable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002a2a: f7fe fc1f bl 800126c <HAL_GetTick> + 8002a2e: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 8002a30: e008 b.n 8002a44 <HAL_RCC_OscConfig+0x5b4> + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8002a32: f7fe fc1b bl 800126c <HAL_GetTick> + 8002a36: 4602 mov r2, r0 + 8002a38: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002a3a: 1ad3 subs r3, r2, r3 + 8002a3c: 2b02 cmp r3, #2 + 8002a3e: d901 bls.n 8002a44 <HAL_RCC_OscConfig+0x5b4> + { + return HAL_TIMEOUT; + 8002a40: 2303 movs r3, #3 + 8002a42: e092 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 8002a44: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002a48: 681b ldr r3, [r3, #0] + 8002a4a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8002a4e: 2b00 cmp r3, #0 + 8002a50: d1ef bne.n 8002a32 <HAL_RCC_OscConfig+0x5a2> + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8002a52: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002a56: 68da ldr r2, [r3, #12] + 8002a58: 4b30 ldr r3, [pc, #192] @ (8002b1c <HAL_RCC_OscConfig+0x68c>) + 8002a5a: 4013 ands r3, r2 + 8002a5c: 687a ldr r2, [r7, #4] + 8002a5e: 6b11 ldr r1, [r2, #48] @ 0x30 + 8002a60: 687a ldr r2, [r7, #4] + 8002a62: 6b52 ldr r2, [r2, #52] @ 0x34 + 8002a64: 4311 orrs r1, r2 + 8002a66: 687a ldr r2, [r7, #4] + 8002a68: 6b92 ldr r2, [r2, #56] @ 0x38 + 8002a6a: 0212 lsls r2, r2, #8 + 8002a6c: 4311 orrs r1, r2 + 8002a6e: 687a ldr r2, [r7, #4] + 8002a70: 6bd2 ldr r2, [r2, #60] @ 0x3c + 8002a72: 4311 orrs r1, r2 + 8002a74: 687a ldr r2, [r7, #4] + 8002a76: 6c12 ldr r2, [r2, #64] @ 0x40 + 8002a78: 4311 orrs r1, r2 + 8002a7a: 687a ldr r2, [r7, #4] + 8002a7c: 6c52 ldr r2, [r2, #68] @ 0x44 + 8002a7e: 430a orrs r2, r1 + 8002a80: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002a84: 4313 orrs r3, r2 + 8002a86: 60cb str r3, [r1, #12] + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8002a88: f7ff fc44 bl 8002314 <LL_RCC_PLL_Enable> + + /* Enable PLL System Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); + 8002a8c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002a90: 68db ldr r3, [r3, #12] + 8002a92: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002a96: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8002a9a: 60d3 str r3, [r2, #12] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002a9c: f7fe fbe6 bl 800126c <HAL_GetTick> + 8002aa0: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 8002aa2: e008 b.n 8002ab6 <HAL_RCC_OscConfig+0x626> + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8002aa4: f7fe fbe2 bl 800126c <HAL_GetTick> + 8002aa8: 4602 mov r2, r0 + 8002aaa: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002aac: 1ad3 subs r3, r2, r3 + 8002aae: 2b02 cmp r3, #2 + 8002ab0: d901 bls.n 8002ab6 <HAL_RCC_OscConfig+0x626> + { + return HAL_TIMEOUT; + 8002ab2: 2303 movs r3, #3 + 8002ab4: e059 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 8002ab6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002aba: 681b ldr r3, [r3, #0] + 8002abc: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8002ac0: 2b00 cmp r3, #0 + 8002ac2: d0ef beq.n 8002aa4 <HAL_RCC_OscConfig+0x614> + if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8002ac4: e050 b.n 8002b68 <HAL_RCC_OscConfig+0x6d8> + } + } + else + { + /* PLL is already used as System core clock */ + return HAL_ERROR; + 8002ac6: 2301 movs r3, #1 + 8002ac8: e04f b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + } + else + { + /* PLL configuration is unchanged */ + /* Re-enable PLL if it was disabled (ie. low power mode) */ + if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 8002aca: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002ace: 681b ldr r3, [r3, #0] + 8002ad0: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8002ad4: 2b00 cmp r3, #0 + 8002ad6: d147 bne.n 8002b68 <HAL_RCC_OscConfig+0x6d8> + { + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8002ad8: f7ff fc1c bl 8002314 <LL_RCC_PLL_Enable> + + /* Enable PLL System Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); + 8002adc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002ae0: 68db ldr r3, [r3, #12] + 8002ae2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8002ae6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8002aea: 60d3 str r3, [r2, #12] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002aec: f7fe fbbe bl 800126c <HAL_GetTick> + 8002af0: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 8002af2: e008 b.n 8002b06 <HAL_RCC_OscConfig+0x676> + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8002af4: f7fe fbba bl 800126c <HAL_GetTick> + 8002af8: 4602 mov r2, r0 + 8002afa: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002afc: 1ad3 subs r3, r2, r3 + 8002afe: 2b02 cmp r3, #2 + 8002b00: d901 bls.n 8002b06 <HAL_RCC_OscConfig+0x676> + { + return HAL_TIMEOUT; + 8002b02: 2303 movs r3, #3 + 8002b04: e031 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 8002b06: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002b0a: 681b ldr r3, [r3, #0] + 8002b0c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8002b10: 2b00 cmp r3, #0 + 8002b12: d0ef beq.n 8002af4 <HAL_RCC_OscConfig+0x664> + 8002b14: e028 b.n 8002b68 <HAL_RCC_OscConfig+0x6d8> + 8002b16: bf00 nop + 8002b18: 58000400 .word 0x58000400 + 8002b1c: 11c1808c .word 0x11c1808c + } + } + else + { + /* Check that PLL is not used as system clock or not */ + if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8002b20: 693b ldr r3, [r7, #16] + 8002b22: 2b0c cmp r3, #12 + 8002b24: d01e beq.n 8002b64 <HAL_RCC_OscConfig+0x6d4> + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8002b26: f7ff fc04 bl 8002332 <LL_RCC_PLL_Disable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002b2a: f7fe fb9f bl 800126c <HAL_GetTick> + 8002b2e: 6278 str r0, [r7, #36] @ 0x24 + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 8002b30: e008 b.n 8002b44 <HAL_RCC_OscConfig+0x6b4> + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8002b32: f7fe fb9b bl 800126c <HAL_GetTick> + 8002b36: 4602 mov r2, r0 + 8002b38: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002b3a: 1ad3 subs r3, r2, r3 + 8002b3c: 2b02 cmp r3, #2 + 8002b3e: d901 bls.n 8002b44 <HAL_RCC_OscConfig+0x6b4> + { + return HAL_TIMEOUT; + 8002b40: 2303 movs r3, #3 + 8002b42: e012 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 8002b44: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002b48: 681b ldr r3, [r3, #0] + 8002b4a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8002b4e: 2b00 cmp r3, #0 + 8002b50: d1ef bne.n 8002b32 <HAL_RCC_OscConfig+0x6a2> + } + } + + /* Disable the PLL source and outputs to save power when PLL is off */ +#if defined(SAI1) && defined(USB) + CLEAR_BIT(RCC->PLLCFGR, (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN)); + 8002b52: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8002b56: 68da ldr r2, [r3, #12] + 8002b58: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8002b5c: 4b05 ldr r3, [pc, #20] @ (8002b74 <HAL_RCC_OscConfig+0x6e4>) + 8002b5e: 4013 ands r3, r2 + 8002b60: 60cb str r3, [r1, #12] + 8002b62: e001 b.n 8002b68 <HAL_RCC_OscConfig+0x6d8> +#endif /* SAI1 && USB */ + } + else + { + /* PLL is already used as System core clock */ + return HAL_ERROR; + 8002b64: 2301 movs r3, #1 + 8002b66: e000 b.n 8002b6a <HAL_RCC_OscConfig+0x6da> + } + } + } + return HAL_OK; + 8002b68: 2300 movs r3, #0 +} + 8002b6a: 4618 mov r0, r3 + 8002b6c: 3734 adds r7, #52 @ 0x34 + 8002b6e: 46bd mov sp, r7 + 8002b70: bd90 pop {r4, r7, pc} + 8002b72: bf00 nop + 8002b74: eefefffc .word 0xeefefffc + +08002b78 <HAL_RCC_ClockConfig>: + * HPRE[3:0] bits to ensure that HCLK1 not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 8002b78: b580 push {r7, lr} + 8002b7a: b084 sub sp, #16 + 8002b7c: af00 add r7, sp, #0 + 8002b7e: 6078 str r0, [r7, #4] + 8002b80: 6039 str r1, [r7, #0] + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + 8002b82: 687b ldr r3, [r7, #4] + 8002b84: 2b00 cmp r3, #0 + 8002b86: d101 bne.n 8002b8c <HAL_RCC_ClockConfig+0x14> + { + return HAL_ERROR; + 8002b88: 2301 movs r3, #1 + 8002b8a: e12d b.n 8002de8 <HAL_RCC_ClockConfig+0x270> + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the FLASH clock + (HCLK4) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + 8002b8c: 4b98 ldr r3, [pc, #608] @ (8002df0 <HAL_RCC_ClockConfig+0x278>) + 8002b8e: 681b ldr r3, [r3, #0] + 8002b90: f003 0307 and.w r3, r3, #7 + 8002b94: 683a ldr r2, [r7, #0] + 8002b96: 429a cmp r2, r3 + 8002b98: d91b bls.n 8002bd2 <HAL_RCC_ClockConfig+0x5a> + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8002b9a: 4b95 ldr r3, [pc, #596] @ (8002df0 <HAL_RCC_ClockConfig+0x278>) + 8002b9c: 681b ldr r3, [r3, #0] + 8002b9e: f023 0207 bic.w r2, r3, #7 + 8002ba2: 4993 ldr r1, [pc, #588] @ (8002df0 <HAL_RCC_ClockConfig+0x278>) + 8002ba4: 683b ldr r3, [r7, #0] + 8002ba6: 4313 orrs r3, r2 + 8002ba8: 600b str r3, [r1, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002baa: f7fe fb5f bl 800126c <HAL_GetTick> + 8002bae: 60f8 str r0, [r7, #12] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 8002bb0: e008 b.n 8002bc4 <HAL_RCC_ClockConfig+0x4c> + { + if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) + 8002bb2: f7fe fb5b bl 800126c <HAL_GetTick> + 8002bb6: 4602 mov r2, r0 + 8002bb8: 68fb ldr r3, [r7, #12] + 8002bba: 1ad3 subs r3, r2, r3 + 8002bbc: 2b02 cmp r3, #2 + 8002bbe: d901 bls.n 8002bc4 <HAL_RCC_ClockConfig+0x4c> + { + return HAL_TIMEOUT; + 8002bc0: 2303 movs r3, #3 + 8002bc2: e111 b.n 8002de8 <HAL_RCC_ClockConfig+0x270> + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 8002bc4: 4b8a ldr r3, [pc, #552] @ (8002df0 <HAL_RCC_ClockConfig+0x278>) + 8002bc6: 681b ldr r3, [r3, #0] + 8002bc8: f003 0307 and.w r3, r3, #7 + 8002bcc: 683a ldr r2, [r7, #0] + 8002bce: 429a cmp r2, r3 + 8002bd0: d1ef bne.n 8002bb2 <HAL_RCC_ClockConfig+0x3a> + } + } + } + + /*-------------------------- HCLK1 Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8002bd2: 687b ldr r3, [r7, #4] + 8002bd4: 681b ldr r3, [r3, #0] + 8002bd6: f003 0302 and.w r3, r3, #2 + 8002bda: 2b00 cmp r3, #0 + 8002bdc: d016 beq.n 8002c0c <HAL_RCC_ClockConfig+0x94> + { + assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLKDivider)); + LL_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLKDivider); + 8002bde: 687b ldr r3, [r7, #4] + 8002be0: 689b ldr r3, [r3, #8] + 8002be2: 4618 mov r0, r3 + 8002be4: f7ff fb13 bl 800220e <LL_RCC_SetAHBPrescaler> + + /* HCLK1 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 8002be8: f7fe fb40 bl 800126c <HAL_GetTick> + 8002bec: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_HPRE() == 0U) + 8002bee: e008 b.n 8002c02 <HAL_RCC_ClockConfig+0x8a> + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 8002bf0: f7fe fb3c bl 800126c <HAL_GetTick> + 8002bf4: 4602 mov r2, r0 + 8002bf6: 68fb ldr r3, [r7, #12] + 8002bf8: 1ad3 subs r3, r2, r3 + 8002bfa: 2b02 cmp r3, #2 + 8002bfc: d901 bls.n 8002c02 <HAL_RCC_ClockConfig+0x8a> + { + return HAL_TIMEOUT; + 8002bfe: 2303 movs r3, #3 + 8002c00: e0f2 b.n 8002de8 <HAL_RCC_ClockConfig+0x270> + while (LL_RCC_IsActiveFlag_HPRE() == 0U) + 8002c02: f7ff fbe8 bl 80023d6 <LL_RCC_IsActiveFlag_HPRE> + 8002c06: 4603 mov r3, r0 + 8002c08: 2b00 cmp r3, #0 + 8002c0a: d0f1 beq.n 8002bf0 <HAL_RCC_ClockConfig+0x78> + } + } + } + + /*-------------------------- HCLK2 Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK2) == RCC_CLOCKTYPE_HCLK2) + 8002c0c: 687b ldr r3, [r7, #4] + 8002c0e: 681b ldr r3, [r3, #0] + 8002c10: f003 0320 and.w r3, r3, #32 + 8002c14: 2b00 cmp r3, #0 + 8002c16: d016 beq.n 8002c46 <HAL_RCC_ClockConfig+0xce> + { + assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK2Divider)); + LL_C2_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLK2Divider); + 8002c18: 687b ldr r3, [r7, #4] + 8002c1a: 695b ldr r3, [r3, #20] + 8002c1c: 4618 mov r0, r3 + 8002c1e: f7ff fb0a bl 8002236 <LL_C2_RCC_SetAHBPrescaler> + + /* HCLK2 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 8002c22: f7fe fb23 bl 800126c <HAL_GetTick> + 8002c26: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_C2HPRE() == 0U) + 8002c28: e008 b.n 8002c3c <HAL_RCC_ClockConfig+0xc4> + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 8002c2a: f7fe fb1f bl 800126c <HAL_GetTick> + 8002c2e: 4602 mov r2, r0 + 8002c30: 68fb ldr r3, [r7, #12] + 8002c32: 1ad3 subs r3, r2, r3 + 8002c34: 2b02 cmp r3, #2 + 8002c36: d901 bls.n 8002c3c <HAL_RCC_ClockConfig+0xc4> + { + return HAL_TIMEOUT; + 8002c38: 2303 movs r3, #3 + 8002c3a: e0d5 b.n 8002de8 <HAL_RCC_ClockConfig+0x270> + while (LL_RCC_IsActiveFlag_C2HPRE() == 0U) + 8002c3c: f7ff fbdd bl 80023fa <LL_RCC_IsActiveFlag_C2HPRE> + 8002c40: 4603 mov r3, r0 + 8002c42: 2b00 cmp r3, #0 + 8002c44: d0f1 beq.n 8002c2a <HAL_RCC_ClockConfig+0xb2> + } + } + } + /*-------------------------- HCLK4 Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK4) == RCC_CLOCKTYPE_HCLK4) + 8002c46: 687b ldr r3, [r7, #4] + 8002c48: 681b ldr r3, [r3, #0] + 8002c4a: f003 0340 and.w r3, r3, #64 @ 0x40 + 8002c4e: 2b00 cmp r3, #0 + 8002c50: d016 beq.n 8002c80 <HAL_RCC_ClockConfig+0x108> + { + assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK4Divider)); + LL_RCC_SetAHB4Prescaler(RCC_ClkInitStruct->AHBCLK4Divider); + 8002c52: 687b ldr r3, [r7, #4] + 8002c54: 699b ldr r3, [r3, #24] + 8002c56: 4618 mov r0, r3 + 8002c58: f7ff fb03 bl 8002262 <LL_RCC_SetAHB4Prescaler> + + /* AHB shared prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 8002c5c: f7fe fb06 bl 800126c <HAL_GetTick> + 8002c60: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U) + 8002c62: e008 b.n 8002c76 <HAL_RCC_ClockConfig+0xfe> + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 8002c64: f7fe fb02 bl 800126c <HAL_GetTick> + 8002c68: 4602 mov r2, r0 + 8002c6a: 68fb ldr r3, [r7, #12] + 8002c6c: 1ad3 subs r3, r2, r3 + 8002c6e: 2b02 cmp r3, #2 + 8002c70: d901 bls.n 8002c76 <HAL_RCC_ClockConfig+0xfe> + { + return HAL_TIMEOUT; + 8002c72: 2303 movs r3, #3 + 8002c74: e0b8 b.n 8002de8 <HAL_RCC_ClockConfig+0x270> + while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U) + 8002c76: f7ff fbd3 bl 8002420 <LL_RCC_IsActiveFlag_SHDHPRE> + 8002c7a: 4603 mov r3, r0 + 8002c7c: 2b00 cmp r3, #0 + 8002c7e: d0f1 beq.n 8002c64 <HAL_RCC_ClockConfig+0xec> + } + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8002c80: 687b ldr r3, [r7, #4] + 8002c82: 681b ldr r3, [r3, #0] + 8002c84: f003 0304 and.w r3, r3, #4 + 8002c88: 2b00 cmp r3, #0 + 8002c8a: d016 beq.n 8002cba <HAL_RCC_ClockConfig+0x142> + { + assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB1CLKDivider)); + LL_RCC_SetAPB1Prescaler(RCC_ClkInitStruct->APB1CLKDivider); + 8002c8c: 687b ldr r3, [r7, #4] + 8002c8e: 68db ldr r3, [r3, #12] + 8002c90: 4618 mov r0, r3 + 8002c92: f7ff fafd bl 8002290 <LL_RCC_SetAPB1Prescaler> + + /* APB1 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 8002c96: f7fe fae9 bl 800126c <HAL_GetTick> + 8002c9a: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_PPRE1() == 0U) + 8002c9c: e008 b.n 8002cb0 <HAL_RCC_ClockConfig+0x138> + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 8002c9e: f7fe fae5 bl 800126c <HAL_GetTick> + 8002ca2: 4602 mov r2, r0 + 8002ca4: 68fb ldr r3, [r7, #12] + 8002ca6: 1ad3 subs r3, r2, r3 + 8002ca8: 2b02 cmp r3, #2 + 8002caa: d901 bls.n 8002cb0 <HAL_RCC_ClockConfig+0x138> + { + return HAL_TIMEOUT; + 8002cac: 2303 movs r3, #3 + 8002cae: e09b b.n 8002de8 <HAL_RCC_ClockConfig+0x270> + while (LL_RCC_IsActiveFlag_PPRE1() == 0U) + 8002cb0: f7ff fbc9 bl 8002446 <LL_RCC_IsActiveFlag_PPRE1> + 8002cb4: 4603 mov r3, r0 + 8002cb6: 2b00 cmp r3, #0 + 8002cb8: d0f1 beq.n 8002c9e <HAL_RCC_ClockConfig+0x126> + } + } + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8002cba: 687b ldr r3, [r7, #4] + 8002cbc: 681b ldr r3, [r3, #0] + 8002cbe: f003 0308 and.w r3, r3, #8 + 8002cc2: 2b00 cmp r3, #0 + 8002cc4: d017 beq.n 8002cf6 <HAL_RCC_ClockConfig+0x17e> + { + assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB2CLKDivider)); + LL_RCC_SetAPB2Prescaler((RCC_ClkInitStruct->APB2CLKDivider) << 3U); + 8002cc6: 687b ldr r3, [r7, #4] + 8002cc8: 691b ldr r3, [r3, #16] + 8002cca: 00db lsls r3, r3, #3 + 8002ccc: 4618 mov r0, r3 + 8002cce: f7ff faf3 bl 80022b8 <LL_RCC_SetAPB2Prescaler> + + /* APB2 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 8002cd2: f7fe facb bl 800126c <HAL_GetTick> + 8002cd6: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_PPRE2() == 0U) + 8002cd8: e008 b.n 8002cec <HAL_RCC_ClockConfig+0x174> + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 8002cda: f7fe fac7 bl 800126c <HAL_GetTick> + 8002cde: 4602 mov r2, r0 + 8002ce0: 68fb ldr r3, [r7, #12] + 8002ce2: 1ad3 subs r3, r2, r3 + 8002ce4: 2b02 cmp r3, #2 + 8002ce6: d901 bls.n 8002cec <HAL_RCC_ClockConfig+0x174> + { + return HAL_TIMEOUT; + 8002ce8: 2303 movs r3, #3 + 8002cea: e07d b.n 8002de8 <HAL_RCC_ClockConfig+0x270> + while (LL_RCC_IsActiveFlag_PPRE2() == 0U) + 8002cec: f7ff fbbd bl 800246a <LL_RCC_IsActiveFlag_PPRE2> + 8002cf0: 4603 mov r3, r0 + 8002cf2: 2b00 cmp r3, #0 + 8002cf4: d0f1 beq.n 8002cda <HAL_RCC_ClockConfig+0x162> + } + } + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8002cf6: 687b ldr r3, [r7, #4] + 8002cf8: 681b ldr r3, [r3, #0] + 8002cfa: f003 0301 and.w r3, r3, #1 + 8002cfe: 2b00 cmp r3, #0 + 8002d00: d043 beq.n 8002d8a <HAL_RCC_ClockConfig+0x212> + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8002d02: 687b ldr r3, [r7, #4] + 8002d04: 685b ldr r3, [r3, #4] + 8002d06: 2b02 cmp r3, #2 + 8002d08: d106 bne.n 8002d18 <HAL_RCC_ClockConfig+0x1a0> + { + /* Check the HSE ready flag */ + if (LL_RCC_HSE_IsReady() == 0U) + 8002d0a: f7ff f893 bl 8001e34 <LL_RCC_HSE_IsReady> + 8002d0e: 4603 mov r3, r0 + 8002d10: 2b00 cmp r3, #0 + 8002d12: d11e bne.n 8002d52 <HAL_RCC_ClockConfig+0x1da> + { + return HAL_ERROR; + 8002d14: 2301 movs r3, #1 + 8002d16: e067 b.n 8002de8 <HAL_RCC_ClockConfig+0x270> + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8002d18: 687b ldr r3, [r7, #4] + 8002d1a: 685b ldr r3, [r3, #4] + 8002d1c: 2b03 cmp r3, #3 + 8002d1e: d106 bne.n 8002d2e <HAL_RCC_ClockConfig+0x1b6> + { + /* Check the PLL ready flag */ + if (LL_RCC_PLL_IsReady() == 0U) + 8002d20: f7ff fb16 bl 8002350 <LL_RCC_PLL_IsReady> + 8002d24: 4603 mov r3, r0 + 8002d26: 2b00 cmp r3, #0 + 8002d28: d113 bne.n 8002d52 <HAL_RCC_ClockConfig+0x1da> + { + return HAL_ERROR; + 8002d2a: 2301 movs r3, #1 + 8002d2c: e05c b.n 8002de8 <HAL_RCC_ClockConfig+0x270> + } + } + /* MSI is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) + 8002d2e: 687b ldr r3, [r7, #4] + 8002d30: 685b ldr r3, [r3, #4] + 8002d32: 2b00 cmp r3, #0 + 8002d34: d106 bne.n 8002d44 <HAL_RCC_ClockConfig+0x1cc> + { + /* Check the MSI ready flag */ + if (LL_RCC_MSI_IsReady() == 0U) + 8002d36: f7ff f9fb bl 8002130 <LL_RCC_MSI_IsReady> + 8002d3a: 4603 mov r3, r0 + 8002d3c: 2b00 cmp r3, #0 + 8002d3e: d108 bne.n 8002d52 <HAL_RCC_ClockConfig+0x1da> + { + return HAL_ERROR; + 8002d40: 2301 movs r3, #1 + 8002d42: e051 b.n 8002de8 <HAL_RCC_ClockConfig+0x270> + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (LL_RCC_HSI_IsReady() == 0U) + 8002d44: f7ff f8a6 bl 8001e94 <LL_RCC_HSI_IsReady> + 8002d48: 4603 mov r3, r0 + 8002d4a: 2b00 cmp r3, #0 + 8002d4c: d101 bne.n 8002d52 <HAL_RCC_ClockConfig+0x1da> + { + return HAL_ERROR; + 8002d4e: 2301 movs r3, #1 + 8002d50: e04a b.n 8002de8 <HAL_RCC_ClockConfig+0x270> + } + + } + + /* apply system clock switch */ + LL_RCC_SetSysClkSource(RCC_ClkInitStruct->SYSCLKSource); + 8002d52: 687b ldr r3, [r7, #4] + 8002d54: 685b ldr r3, [r3, #4] + 8002d56: 4618 mov r0, r3 + 8002d58: f7ff fa39 bl 80021ce <LL_RCC_SetSysClkSource> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002d5c: f7fe fa86 bl 800126c <HAL_GetTick> + 8002d60: 60f8 str r0, [r7, #12] + + /* check system clock source switch status */ + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8002d62: e00a b.n 8002d7a <HAL_RCC_ClockConfig+0x202> + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 8002d64: f7fe fa82 bl 800126c <HAL_GetTick> + 8002d68: 4602 mov r2, r0 + 8002d6a: 68fb ldr r3, [r7, #12] + 8002d6c: 1ad3 subs r3, r2, r3 + 8002d6e: f241 3288 movw r2, #5000 @ 0x1388 + 8002d72: 4293 cmp r3, r2 + 8002d74: d901 bls.n 8002d7a <HAL_RCC_ClockConfig+0x202> + { + return HAL_TIMEOUT; + 8002d76: 2303 movs r3, #3 + 8002d78: e036 b.n 8002de8 <HAL_RCC_ClockConfig+0x270> + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8002d7a: f7ff fa3c bl 80021f6 <LL_RCC_GetSysClkSource> + 8002d7e: 4602 mov r2, r0 + 8002d80: 687b ldr r3, [r7, #4] + 8002d82: 685b ldr r3, [r3, #4] + 8002d84: 009b lsls r3, r3, #2 + 8002d86: 429a cmp r2, r3 + 8002d88: d1ec bne.n 8002d64 <HAL_RCC_ClockConfig+0x1ec> + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + 8002d8a: 4b19 ldr r3, [pc, #100] @ (8002df0 <HAL_RCC_ClockConfig+0x278>) + 8002d8c: 681b ldr r3, [r3, #0] + 8002d8e: f003 0307 and.w r3, r3, #7 + 8002d92: 683a ldr r2, [r7, #0] + 8002d94: 429a cmp r2, r3 + 8002d96: d21b bcs.n 8002dd0 <HAL_RCC_ClockConfig+0x258> + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8002d98: 4b15 ldr r3, [pc, #84] @ (8002df0 <HAL_RCC_ClockConfig+0x278>) + 8002d9a: 681b ldr r3, [r3, #0] + 8002d9c: f023 0207 bic.w r2, r3, #7 + 8002da0: 4913 ldr r1, [pc, #76] @ (8002df0 <HAL_RCC_ClockConfig+0x278>) + 8002da2: 683b ldr r3, [r7, #0] + 8002da4: 4313 orrs r3, r2 + 8002da6: 600b str r3, [r1, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002da8: f7fe fa60 bl 800126c <HAL_GetTick> + 8002dac: 60f8 str r0, [r7, #12] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 8002dae: e008 b.n 8002dc2 <HAL_RCC_ClockConfig+0x24a> + { + if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) + 8002db0: f7fe fa5c bl 800126c <HAL_GetTick> + 8002db4: 4602 mov r2, r0 + 8002db6: 68fb ldr r3, [r7, #12] + 8002db8: 1ad3 subs r3, r2, r3 + 8002dba: 2b02 cmp r3, #2 + 8002dbc: d901 bls.n 8002dc2 <HAL_RCC_ClockConfig+0x24a> + { + return HAL_TIMEOUT; + 8002dbe: 2303 movs r3, #3 + 8002dc0: e012 b.n 8002de8 <HAL_RCC_ClockConfig+0x270> + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 8002dc2: 4b0b ldr r3, [pc, #44] @ (8002df0 <HAL_RCC_ClockConfig+0x278>) + 8002dc4: 681b ldr r3, [r3, #0] + 8002dc6: f003 0307 and.w r3, r3, #7 + 8002dca: 683a ldr r2, [r7, #0] + 8002dcc: 429a cmp r2, r3 + 8002dce: d1ef bne.n 8002db0 <HAL_RCC_ClockConfig+0x238> + } + + /*---------------------------------------------------------------------------*/ + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetHCLKFreq(); + 8002dd0: f000 f87e bl 8002ed0 <HAL_RCC_GetHCLKFreq> + 8002dd4: 4603 mov r3, r0 + 8002dd6: 4a07 ldr r2, [pc, #28] @ (8002df4 <HAL_RCC_ClockConfig+0x27c>) + 8002dd8: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + return HAL_InitTick(HAL_GetTickPrio()); + 8002dda: f7fe fa53 bl 8001284 <HAL_GetTickPrio> + 8002dde: 4603 mov r3, r0 + 8002de0: 4618 mov r0, r3 + 8002de2: f7fe f9f5 bl 80011d0 <HAL_InitTick> + 8002de6: 4603 mov r3, r0 +} + 8002de8: 4618 mov r0, r3 + 8002dea: 3710 adds r7, #16 + 8002dec: 46bd mov sp, r7 + 8002dee: bd80 pop {r7, pc} + 8002df0: 58004000 .word 0x58004000 + 8002df4: 200006c8 .word 0x200006c8 + +08002df8 <HAL_RCC_GetSysClockFreq>: + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 8002df8: b590 push {r4, r7, lr} + 8002dfa: b085 sub sp, #20 + 8002dfc: af00 add r7, sp, #0 + uint32_t pllsource; + uint32_t sysclockfreq; + uint32_t pllinputfreq; + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8002dfe: f7ff f9fa bl 80021f6 <LL_RCC_GetSysClkSource> + 8002e02: 6078 str r0, [r7, #4] + + if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_MSI) + 8002e04: 687b ldr r3, [r7, #4] + 8002e06: 2b00 cmp r3, #0 + 8002e08: d10a bne.n 8002e20 <HAL_RCC_GetSysClockFreq+0x28> + { + /* Retrieve MSI frequency range in HZ*/ + /* MSI used as system clock source */ + sysclockfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); + 8002e0a: f7ff f9b6 bl 800217a <LL_RCC_MSI_GetRange> + 8002e0e: 4603 mov r3, r0 + 8002e10: 091b lsrs r3, r3, #4 + 8002e12: f003 030f and.w r3, r3, #15 + 8002e16: 4a2b ldr r2, [pc, #172] @ (8002ec4 <HAL_RCC_GetSysClockFreq+0xcc>) + 8002e18: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8002e1c: 60fb str r3, [r7, #12] + 8002e1e: e04b b.n 8002eb8 <HAL_RCC_GetSysClockFreq+0xc0> + } + else if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) + 8002e20: 687b ldr r3, [r7, #4] + 8002e22: 2b04 cmp r3, #4 + 8002e24: d102 bne.n 8002e2c <HAL_RCC_GetSysClockFreq+0x34> + { + /* HSI used as system clock source */ + sysclockfreq = HSI_VALUE; + 8002e26: 4b28 ldr r3, [pc, #160] @ (8002ec8 <HAL_RCC_GetSysClockFreq+0xd0>) + 8002e28: 60fb str r3, [r7, #12] + 8002e2a: e045 b.n 8002eb8 <HAL_RCC_GetSysClockFreq+0xc0> + } + else if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE) + 8002e2c: 687b ldr r3, [r7, #4] + 8002e2e: 2b08 cmp r3, #8 + 8002e30: d10a bne.n 8002e48 <HAL_RCC_GetSysClockFreq+0x50> + { + /* HSE used as system clock source */ + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + 8002e32: f7fe ffcf bl 8001dd4 <LL_RCC_HSE_IsEnabledDiv2> + 8002e36: 4603 mov r3, r0 + 8002e38: 2b01 cmp r3, #1 + 8002e3a: d102 bne.n 8002e42 <HAL_RCC_GetSysClockFreq+0x4a> + { + sysclockfreq = HSE_VALUE / 2U; + 8002e3c: 4b22 ldr r3, [pc, #136] @ (8002ec8 <HAL_RCC_GetSysClockFreq+0xd0>) + 8002e3e: 60fb str r3, [r7, #12] + 8002e40: e03a b.n 8002eb8 <HAL_RCC_GetSysClockFreq+0xc0> + } + else + { + sysclockfreq = HSE_VALUE; + 8002e42: 4b22 ldr r3, [pc, #136] @ (8002ecc <HAL_RCC_GetSysClockFreq+0xd4>) + 8002e44: 60fb str r3, [r7, #12] + 8002e46: e037 b.n 8002eb8 <HAL_RCC_GetSysClockFreq+0xc0> + } + } + else + { + /* PLL used as system clock source */ + pllsource = LL_RCC_PLL_GetMainSource(); + 8002e48: f7ff fab9 bl 80023be <LL_RCC_PLL_GetMainSource> + 8002e4c: 6038 str r0, [r7, #0] + switch (pllsource) + 8002e4e: 683b ldr r3, [r7, #0] + 8002e50: 2b02 cmp r3, #2 + 8002e52: d003 beq.n 8002e5c <HAL_RCC_GetSysClockFreq+0x64> + 8002e54: 683b ldr r3, [r7, #0] + 8002e56: 2b03 cmp r3, #3 + 8002e58: d003 beq.n 8002e62 <HAL_RCC_GetSysClockFreq+0x6a> + 8002e5a: e00d b.n 8002e78 <HAL_RCC_GetSysClockFreq+0x80> + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pllinputfreq = HSI_VALUE; + 8002e5c: 4b1a ldr r3, [pc, #104] @ (8002ec8 <HAL_RCC_GetSysClockFreq+0xd0>) + 8002e5e: 60bb str r3, [r7, #8] + break; + 8002e60: e015 b.n 8002e8e <HAL_RCC_GetSysClockFreq+0x96> + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + 8002e62: f7fe ffb7 bl 8001dd4 <LL_RCC_HSE_IsEnabledDiv2> + 8002e66: 4603 mov r3, r0 + 8002e68: 2b01 cmp r3, #1 + 8002e6a: d102 bne.n 8002e72 <HAL_RCC_GetSysClockFreq+0x7a> + { + pllinputfreq = HSE_VALUE / 2U; + 8002e6c: 4b16 ldr r3, [pc, #88] @ (8002ec8 <HAL_RCC_GetSysClockFreq+0xd0>) + 8002e6e: 60bb str r3, [r7, #8] + } + else + { + pllinputfreq = HSE_VALUE; + } + break; + 8002e70: e00d b.n 8002e8e <HAL_RCC_GetSysClockFreq+0x96> + pllinputfreq = HSE_VALUE; + 8002e72: 4b16 ldr r3, [pc, #88] @ (8002ecc <HAL_RCC_GetSysClockFreq+0xd4>) + 8002e74: 60bb str r3, [r7, #8] + break; + 8002e76: e00a b.n 8002e8e <HAL_RCC_GetSysClockFreq+0x96> + case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ + default: + pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); + 8002e78: f7ff f97f bl 800217a <LL_RCC_MSI_GetRange> + 8002e7c: 4603 mov r3, r0 + 8002e7e: 091b lsrs r3, r3, #4 + 8002e80: f003 030f and.w r3, r3, #15 + 8002e84: 4a0f ldr r2, [pc, #60] @ (8002ec4 <HAL_RCC_GetSysClockFreq+0xcc>) + 8002e86: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8002e8a: 60bb str r3, [r7, #8] + break; + 8002e8c: bf00 nop + } + sysclockfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetN(), + 8002e8e: f7ff fa71 bl 8002374 <LL_RCC_PLL_GetN> + 8002e92: 4602 mov r2, r0 + 8002e94: 68bb ldr r3, [r7, #8] + 8002e96: fb03 f402 mul.w r4, r3, r2 + 8002e9a: f7ff fa84 bl 80023a6 <LL_RCC_PLL_GetDivider> + 8002e9e: 4603 mov r3, r0 + 8002ea0: 091b lsrs r3, r3, #4 + 8002ea2: 3301 adds r3, #1 + 8002ea4: fbb4 f4f3 udiv r4, r4, r3 + 8002ea8: f7ff fa71 bl 800238e <LL_RCC_PLL_GetR> + 8002eac: 4603 mov r3, r0 + 8002eae: 0f5b lsrs r3, r3, #29 + 8002eb0: 3301 adds r3, #1 + 8002eb2: fbb4 f3f3 udiv r3, r4, r3 + 8002eb6: 60fb str r3, [r7, #12] + LL_RCC_PLL_GetR()); + } + + return sysclockfreq; + 8002eb8: 68fb ldr r3, [r7, #12] +} + 8002eba: 4618 mov r0, r3 + 8002ebc: 3714 adds r7, #20 + 8002ebe: 46bd mov sp, r7 + 8002ec0: bd90 pop {r4, r7, pc} + 8002ec2: bf00 nop + 8002ec4: 08005278 .word 0x08005278 + 8002ec8: 00f42400 .word 0x00f42400 + 8002ecc: 01e84800 .word 0x01e84800 + +08002ed0 <HAL_RCC_GetHCLKFreq>: +/** + * @brief Return the HCLK frequency. + * @retval HCLK frequency in Hz + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + 8002ed0: b598 push {r3, r4, r7, lr} + 8002ed2: af00 add r7, sp, #0 + /* Get SysClock and Compute HCLK1 frequency ---------------------------*/ + return ((uint32_t)(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()))); + 8002ed4: f7ff ff90 bl 8002df8 <HAL_RCC_GetSysClockFreq> + 8002ed8: 4604 mov r4, r0 + 8002eda: f7ff fa01 bl 80022e0 <LL_RCC_GetAHBPrescaler> + 8002ede: 4603 mov r3, r0 + 8002ee0: 091b lsrs r3, r3, #4 + 8002ee2: f003 030f and.w r3, r3, #15 + 8002ee6: 4a03 ldr r2, [pc, #12] @ (8002ef4 <HAL_RCC_GetHCLKFreq+0x24>) + 8002ee8: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8002eec: fbb4 f3f3 udiv r3, r4, r3 +} + 8002ef0: 4618 mov r0, r3 + 8002ef2: bd98 pop {r3, r4, r7, pc} + 8002ef4: 08005238 .word 0x08005238 + +08002ef8 <RCC_SetFlashLatencyFromMSIRange>: + voltage range. + * @param MSI_Range MSI range value from @ref RCC_MSIRANGE_0 to @ref RCC_MSIRANGE_11 + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSI_Range) +{ + 8002ef8: b590 push {r4, r7, lr} + 8002efa: b085 sub sp, #20 + 8002efc: af00 add r7, sp, #0 + 8002efe: 6078 str r0, [r7, #4] + + /* Check the parameters */ + assert_param(IS_RCC_MSI_CLOCK_RANGE(MSI_Range)); + + /* MSI frequency range in Hz */ + if (MSI_Range > RCC_MSIRANGE_11) + 8002f00: 687b ldr r3, [r7, #4] + 8002f02: 2bb0 cmp r3, #176 @ 0xb0 + 8002f04: d903 bls.n 8002f0e <RCC_SetFlashLatencyFromMSIRange+0x16> + { + msifreq = __LL_RCC_CALC_MSI_FREQ(RCC_MSIRANGE_11); + 8002f06: 4b15 ldr r3, [pc, #84] @ (8002f5c <RCC_SetFlashLatencyFromMSIRange+0x64>) + 8002f08: 6adb ldr r3, [r3, #44] @ 0x2c + 8002f0a: 60fb str r3, [r7, #12] + 8002f0c: e007 b.n 8002f1e <RCC_SetFlashLatencyFromMSIRange+0x26> + } + else + { + msifreq = __LL_RCC_CALC_MSI_FREQ(MSI_Range); + 8002f0e: 687b ldr r3, [r7, #4] + 8002f10: 091b lsrs r3, r3, #4 + 8002f12: f003 030f and.w r3, r3, #15 + 8002f16: 4a11 ldr r2, [pc, #68] @ (8002f5c <RCC_SetFlashLatencyFromMSIRange+0x64>) + 8002f18: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8002f1c: 60fb str r3, [r7, #12] + } + + flash_clksrcfreq = __LL_RCC_CALC_HCLK4_FREQ(msifreq, LL_RCC_GetAHB4Prescaler()); + 8002f1e: f7ff f9eb bl 80022f8 <LL_RCC_GetAHB4Prescaler> + 8002f22: 4603 mov r3, r0 + 8002f24: 091b lsrs r3, r3, #4 + 8002f26: f003 030f and.w r3, r3, #15 + 8002f2a: 4a0d ldr r2, [pc, #52] @ (8002f60 <RCC_SetFlashLatencyFromMSIRange+0x68>) + 8002f2c: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8002f30: 68fa ldr r2, [r7, #12] + 8002f32: fbb2 f3f3 udiv r3, r2, r3 + 8002f36: 60bb str r3, [r7, #8] + +#if defined(PWR_CR1_VOS) + return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), HAL_PWREx_GetVoltageRange()); + 8002f38: 68bb ldr r3, [r7, #8] + 8002f3a: 4a0a ldr r2, [pc, #40] @ (8002f64 <RCC_SetFlashLatencyFromMSIRange+0x6c>) + 8002f3c: fba2 2303 umull r2, r3, r2, r3 + 8002f40: 0c9c lsrs r4, r3, #18 + 8002f42: f7fe ff0d bl 8001d60 <HAL_PWREx_GetVoltageRange> + 8002f46: 4603 mov r3, r0 + 8002f48: 4619 mov r1, r3 + 8002f4a: 4620 mov r0, r4 + 8002f4c: f000 f80c bl 8002f68 <RCC_SetFlashLatency> + 8002f50: 4603 mov r3, r0 +#else + return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), PWR_REGULATOR_VOLTAGE_SCALE1); +#endif /* PWR_CR1_VOS */ +} + 8002f52: 4618 mov r0, r3 + 8002f54: 3714 adds r7, #20 + 8002f56: 46bd mov sp, r7 + 8002f58: bd90 pop {r4, r7, pc} + 8002f5a: bf00 nop + 8002f5c: 08005278 .word 0x08005278 + 8002f60: 08005238 .word 0x08005238 + 8002f64: 431bde83 .word 0x431bde83 + +08002f68 <RCC_SetFlashLatency>: + * @param Flash_ClkSrcFreq Flash Clock Source (in MHz) + * @param VCORE_Voltage Current Vcore voltage (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2) + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t VCORE_Voltage) +{ + 8002f68: b590 push {r4, r7, lr} + 8002f6a: b093 sub sp, #76 @ 0x4c + 8002f6c: af00 add r7, sp, #0 + 8002f6e: 6078 str r0, [r7, #4] + 8002f70: 6039 str r1, [r7, #0] + /* Flash Clock source (HCLK4) range in MHz with a VCORE is range1 */ + const uint32_t FLASH_CLK_SRC_RANGE_VOS1[] = {18UL, 36UL, 54UL, 64UL}; + 8002f72: 4b37 ldr r3, [pc, #220] @ (8003050 <RCC_SetFlashLatency+0xe8>) + 8002f74: f107 0428 add.w r4, r7, #40 @ 0x28 + 8002f78: cb0f ldmia r3, {r0, r1, r2, r3} + 8002f7a: e884 000f stmia.w r4, {r0, r1, r2, r3} +#if defined(PWR_CR1_VOS) + /* Flash Clock source (HCLK4) range in MHz with a VCORE is range2 */ + const uint32_t FLASH_CLK_SRC_RANGE_VOS2[] = {6UL, 12UL, 16UL}; + 8002f7e: 4a35 ldr r2, [pc, #212] @ (8003054 <RCC_SetFlashLatency+0xec>) + 8002f80: f107 031c add.w r3, r7, #28 + 8002f84: ca07 ldmia r2, {r0, r1, r2} + 8002f86: e883 0007 stmia.w r3, {r0, r1, r2} +#endif /* PWR_CR1_VOS */ + /* Flash Latency range */ + const uint32_t FLASH_LATENCY_RANGE[] = {FLASH_LATENCY_0, FLASH_LATENCY_1, FLASH_LATENCY_2, FLASH_LATENCY_3}; + 8002f8a: 4b33 ldr r3, [pc, #204] @ (8003058 <RCC_SetFlashLatency+0xf0>) + 8002f8c: f107 040c add.w r4, r7, #12 + 8002f90: cb0f ldmia r3, {r0, r1, r2, r3} + 8002f92: e884 000f stmia.w r4, {r0, r1, r2, r3} + uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ + 8002f96: 2300 movs r3, #0 + 8002f98: 647b str r3, [r7, #68] @ 0x44 + uint32_t tickstart; + +#if defined(PWR_CR1_VOS) + if (VCORE_Voltage == PWR_REGULATOR_VOLTAGE_SCALE1) + 8002f9a: 683b ldr r3, [r7, #0] + 8002f9c: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 8002fa0: d11a bne.n 8002fd8 <RCC_SetFlashLatency+0x70> + { + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) + 8002fa2: 2300 movs r3, #0 + 8002fa4: 643b str r3, [r7, #64] @ 0x40 + 8002fa6: e013 b.n 8002fd0 <RCC_SetFlashLatency+0x68> + { + if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS1[index]) + 8002fa8: 6c3b ldr r3, [r7, #64] @ 0x40 + 8002faa: 009b lsls r3, r3, #2 + 8002fac: 3348 adds r3, #72 @ 0x48 + 8002fae: 443b add r3, r7 + 8002fb0: f853 3c20 ldr.w r3, [r3, #-32] + 8002fb4: 687a ldr r2, [r7, #4] + 8002fb6: 429a cmp r2, r3 + 8002fb8: d807 bhi.n 8002fca <RCC_SetFlashLatency+0x62> + { + latency = FLASH_LATENCY_RANGE[index]; + 8002fba: 6c3b ldr r3, [r7, #64] @ 0x40 + 8002fbc: 009b lsls r3, r3, #2 + 8002fbe: 3348 adds r3, #72 @ 0x48 + 8002fc0: 443b add r3, r7 + 8002fc2: f853 3c3c ldr.w r3, [r3, #-60] + 8002fc6: 647b str r3, [r7, #68] @ 0x44 + break; + 8002fc8: e020 b.n 800300c <RCC_SetFlashLatency+0xa4> + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) + 8002fca: 6c3b ldr r3, [r7, #64] @ 0x40 + 8002fcc: 3301 adds r3, #1 + 8002fce: 643b str r3, [r7, #64] @ 0x40 + 8002fd0: 6c3b ldr r3, [r7, #64] @ 0x40 + 8002fd2: 2b03 cmp r3, #3 + 8002fd4: d9e8 bls.n 8002fa8 <RCC_SetFlashLatency+0x40> + 8002fd6: e019 b.n 800300c <RCC_SetFlashLatency+0xa4> + } + } + } + else /* PWR_REGULATOR_VOLTAGE_SCALE2 */ + { + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++) + 8002fd8: 2300 movs r3, #0 + 8002fda: 63fb str r3, [r7, #60] @ 0x3c + 8002fdc: e013 b.n 8003006 <RCC_SetFlashLatency+0x9e> + { + if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS2[index]) + 8002fde: 6bfb ldr r3, [r7, #60] @ 0x3c + 8002fe0: 009b lsls r3, r3, #2 + 8002fe2: 3348 adds r3, #72 @ 0x48 + 8002fe4: 443b add r3, r7 + 8002fe6: f853 3c2c ldr.w r3, [r3, #-44] + 8002fea: 687a ldr r2, [r7, #4] + 8002fec: 429a cmp r2, r3 + 8002fee: d807 bhi.n 8003000 <RCC_SetFlashLatency+0x98> + { + latency = FLASH_LATENCY_RANGE[index]; + 8002ff0: 6bfb ldr r3, [r7, #60] @ 0x3c + 8002ff2: 009b lsls r3, r3, #2 + 8002ff4: 3348 adds r3, #72 @ 0x48 + 8002ff6: 443b add r3, r7 + 8002ff8: f853 3c3c ldr.w r3, [r3, #-60] + 8002ffc: 647b str r3, [r7, #68] @ 0x44 + break; + 8002ffe: e005 b.n 800300c <RCC_SetFlashLatency+0xa4> + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++) + 8003000: 6bfb ldr r3, [r7, #60] @ 0x3c + 8003002: 3301 adds r3, #1 + 8003004: 63fb str r3, [r7, #60] @ 0x3c + 8003006: 6bfb ldr r3, [r7, #60] @ 0x3c + 8003008: 2b02 cmp r3, #2 + 800300a: d9e8 bls.n 8002fde <RCC_SetFlashLatency+0x76> + break; + } + } +#endif /* PWR_CR1_VOS */ + + __HAL_FLASH_SET_LATENCY(latency); + 800300c: 4b13 ldr r3, [pc, #76] @ (800305c <RCC_SetFlashLatency+0xf4>) + 800300e: 681b ldr r3, [r3, #0] + 8003010: f023 0207 bic.w r2, r3, #7 + 8003014: 4911 ldr r1, [pc, #68] @ (800305c <RCC_SetFlashLatency+0xf4>) + 8003016: 6c7b ldr r3, [r7, #68] @ 0x44 + 8003018: 4313 orrs r3, r2 + 800301a: 600b str r3, [r1, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800301c: f7fe f926 bl 800126c <HAL_GetTick> + 8003020: 63b8 str r0, [r7, #56] @ 0x38 + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + while (__HAL_FLASH_GET_LATENCY() != latency) + 8003022: e008 b.n 8003036 <RCC_SetFlashLatency+0xce> + { + if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) + 8003024: f7fe f922 bl 800126c <HAL_GetTick> + 8003028: 4602 mov r2, r0 + 800302a: 6bbb ldr r3, [r7, #56] @ 0x38 + 800302c: 1ad3 subs r3, r2, r3 + 800302e: 2b02 cmp r3, #2 + 8003030: d901 bls.n 8003036 <RCC_SetFlashLatency+0xce> + { + return HAL_TIMEOUT; + 8003032: 2303 movs r3, #3 + 8003034: e007 b.n 8003046 <RCC_SetFlashLatency+0xde> + while (__HAL_FLASH_GET_LATENCY() != latency) + 8003036: 4b09 ldr r3, [pc, #36] @ (800305c <RCC_SetFlashLatency+0xf4>) + 8003038: 681b ldr r3, [r3, #0] + 800303a: f003 0307 and.w r3, r3, #7 + 800303e: 6c7a ldr r2, [r7, #68] @ 0x44 + 8003040: 429a cmp r2, r3 + 8003042: d1ef bne.n 8003024 <RCC_SetFlashLatency+0xbc> + } + } + return HAL_OK; + 8003044: 2300 movs r3, #0 +} + 8003046: 4618 mov r0, r3 + 8003048: 374c adds r7, #76 @ 0x4c + 800304a: 46bd mov sp, r7 + 800304c: bd90 pop {r4, r7, pc} + 800304e: bf00 nop + 8003050: 0800520c .word 0x0800520c + 8003054: 0800521c .word 0x0800521c + 8003058: 08005228 .word 0x08005228 + 800305c: 58004000 .word 0x58004000 + +08003060 <LL_RCC_LSE_IsEnabled>: +{ + 8003060: b480 push {r7} + 8003062: af00 add r7, sp, #0 + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == (RCC_BDCR_LSEON)) ? 1UL : 0UL); + 8003064: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003068: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 800306c: f003 0301 and.w r3, r3, #1 + 8003070: 2b01 cmp r3, #1 + 8003072: d101 bne.n 8003078 <LL_RCC_LSE_IsEnabled+0x18> + 8003074: 2301 movs r3, #1 + 8003076: e000 b.n 800307a <LL_RCC_LSE_IsEnabled+0x1a> + 8003078: 2300 movs r3, #0 +} + 800307a: 4618 mov r0, r3 + 800307c: 46bd mov sp, r7 + 800307e: f85d 7b04 ldr.w r7, [sp], #4 + 8003082: 4770 bx lr + +08003084 <LL_RCC_LSE_IsReady>: +{ + 8003084: b480 push {r7} + 8003086: af00 add r7, sp, #0 + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); + 8003088: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800308c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003090: f003 0302 and.w r3, r3, #2 + 8003094: 2b02 cmp r3, #2 + 8003096: d101 bne.n 800309c <LL_RCC_LSE_IsReady+0x18> + 8003098: 2301 movs r3, #1 + 800309a: e000 b.n 800309e <LL_RCC_LSE_IsReady+0x1a> + 800309c: 2300 movs r3, #0 +} + 800309e: 4618 mov r0, r3 + 80030a0: 46bd mov sp, r7 + 80030a2: f85d 7b04 ldr.w r7, [sp], #4 + 80030a6: 4770 bx lr + +080030a8 <LL_RCC_SetRFWKPClockSource>: +{ + 80030a8: b480 push {r7} + 80030aa: b083 sub sp, #12 + 80030ac: af00 add r7, sp, #0 + 80030ae: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CSR, RCC_CSR_RFWKPSEL, Source); + 80030b0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80030b4: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 80030b8: f423 4240 bic.w r2, r3, #49152 @ 0xc000 + 80030bc: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80030c0: 687b ldr r3, [r7, #4] + 80030c2: 4313 orrs r3, r2 + 80030c4: f8c1 3094 str.w r3, [r1, #148] @ 0x94 +} + 80030c8: bf00 nop + 80030ca: 370c adds r7, #12 + 80030cc: 46bd mov sp, r7 + 80030ce: f85d 7b04 ldr.w r7, [sp], #4 + 80030d2: 4770 bx lr + +080030d4 <LL_RCC_SetSMPSClockSource>: +{ + 80030d4: b480 push {r7} + 80030d6: b083 sub sp, #12 + 80030d8: af00 add r7, sp, #0 + 80030da: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->SMPSCR, RCC_SMPSCR_SMPSSEL, SMPSSource); + 80030dc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80030e0: 6a5b ldr r3, [r3, #36] @ 0x24 + 80030e2: f023 0203 bic.w r2, r3, #3 + 80030e6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80030ea: 687b ldr r3, [r7, #4] + 80030ec: 4313 orrs r3, r2 + 80030ee: 624b str r3, [r1, #36] @ 0x24 +} + 80030f0: bf00 nop + 80030f2: 370c adds r7, #12 + 80030f4: 46bd mov sp, r7 + 80030f6: f85d 7b04 ldr.w r7, [sp], #4 + 80030fa: 4770 bx lr + +080030fc <LL_RCC_SetSMPSPrescaler>: +{ + 80030fc: b480 push {r7} + 80030fe: b083 sub sp, #12 + 8003100: af00 add r7, sp, #0 + 8003102: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->SMPSCR, RCC_SMPSCR_SMPSDIV, Prescaler); + 8003104: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003108: 6a5b ldr r3, [r3, #36] @ 0x24 + 800310a: f023 0230 bic.w r2, r3, #48 @ 0x30 + 800310e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003112: 687b ldr r3, [r7, #4] + 8003114: 4313 orrs r3, r2 + 8003116: 624b str r3, [r1, #36] @ 0x24 +} + 8003118: bf00 nop + 800311a: 370c adds r7, #12 + 800311c: 46bd mov sp, r7 + 800311e: f85d 7b04 ldr.w r7, [sp], #4 + 8003122: 4770 bx lr + +08003124 <LL_RCC_SetUSARTClockSource>: +{ + 8003124: b480 push {r7} + 8003126: b083 sub sp, #12 + 8003128: af00 add r7, sp, #0 + 800312a: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, USARTxSource); + 800312c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003130: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8003134: f023 0203 bic.w r2, r3, #3 + 8003138: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800313c: 687b ldr r3, [r7, #4] + 800313e: 4313 orrs r3, r2 + 8003140: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003144: bf00 nop + 8003146: 370c adds r7, #12 + 8003148: 46bd mov sp, r7 + 800314a: f85d 7b04 ldr.w r7, [sp], #4 + 800314e: 4770 bx lr + +08003150 <LL_RCC_SetLPUARTClockSource>: +{ + 8003150: b480 push {r7} + 8003152: b083 sub sp, #12 + 8003154: af00 add r7, sp, #0 + 8003156: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource); + 8003158: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800315c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8003160: f423 6240 bic.w r2, r3, #3072 @ 0xc00 + 8003164: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003168: 687b ldr r3, [r7, #4] + 800316a: 4313 orrs r3, r2 + 800316c: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003170: bf00 nop + 8003172: 370c adds r7, #12 + 8003174: 46bd mov sp, r7 + 8003176: f85d 7b04 ldr.w r7, [sp], #4 + 800317a: 4770 bx lr + +0800317c <LL_RCC_SetI2CClockSource>: +{ + 800317c: b480 push {r7} + 800317e: b083 sub sp, #12 + 8003180: af00 add r7, sp, #0 + 8003182: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000U), ((I2CxSource << 4) & 0x000FF000U)); + 8003184: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003188: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 + 800318c: 687b ldr r3, [r7, #4] + 800318e: 091b lsrs r3, r3, #4 + 8003190: f403 237f and.w r3, r3, #1044480 @ 0xff000 + 8003194: 43db mvns r3, r3 + 8003196: 401a ands r2, r3 + 8003198: 687b ldr r3, [r7, #4] + 800319a: 011b lsls r3, r3, #4 + 800319c: f403 237f and.w r3, r3, #1044480 @ 0xff000 + 80031a0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80031a4: 4313 orrs r3, r2 + 80031a6: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 80031aa: bf00 nop + 80031ac: 370c adds r7, #12 + 80031ae: 46bd mov sp, r7 + 80031b0: f85d 7b04 ldr.w r7, [sp], #4 + 80031b4: 4770 bx lr + +080031b6 <LL_RCC_SetLPTIMClockSource>: +{ + 80031b6: b480 push {r7} + 80031b8: b083 sub sp, #12 + 80031ba: af00 add r7, sp, #0 + 80031bc: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16)); + 80031be: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80031c2: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 + 80031c6: 687b ldr r3, [r7, #4] + 80031c8: 0c1b lsrs r3, r3, #16 + 80031ca: 041b lsls r3, r3, #16 + 80031cc: 43db mvns r3, r3 + 80031ce: 401a ands r2, r3 + 80031d0: 687b ldr r3, [r7, #4] + 80031d2: 041b lsls r3, r3, #16 + 80031d4: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80031d8: 4313 orrs r3, r2 + 80031da: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 80031de: bf00 nop + 80031e0: 370c adds r7, #12 + 80031e2: 46bd mov sp, r7 + 80031e4: f85d 7b04 ldr.w r7, [sp], #4 + 80031e8: 4770 bx lr + +080031ea <LL_RCC_SetSAIClockSource>: +{ + 80031ea: b480 push {r7} + 80031ec: b083 sub sp, #12 + 80031ee: af00 add r7, sp, #0 + 80031f0: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource); + 80031f2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80031f6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 80031fa: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 + 80031fe: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003202: 687b ldr r3, [r7, #4] + 8003204: 4313 orrs r3, r2 + 8003206: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 800320a: bf00 nop + 800320c: 370c adds r7, #12 + 800320e: 46bd mov sp, r7 + 8003210: f85d 7b04 ldr.w r7, [sp], #4 + 8003214: 4770 bx lr + +08003216 <LL_RCC_SetRNGClockSource>: +{ + 8003216: b480 push {r7} + 8003218: b083 sub sp, #12 + 800321a: af00 add r7, sp, #0 + 800321c: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource); + 800321e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003222: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8003226: f023 4240 bic.w r2, r3, #3221225472 @ 0xc0000000 + 800322a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800322e: 687b ldr r3, [r7, #4] + 8003230: 4313 orrs r3, r2 + 8003232: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003236: bf00 nop + 8003238: 370c adds r7, #12 + 800323a: 46bd mov sp, r7 + 800323c: f85d 7b04 ldr.w r7, [sp], #4 + 8003240: 4770 bx lr + +08003242 <LL_RCC_SetCLK48ClockSource>: +{ + 8003242: b480 push {r7} + 8003244: b083 sub sp, #12 + 8003246: af00 add r7, sp, #0 + 8003248: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, CLK48xSource); + 800324a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800324e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8003252: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000 + 8003256: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800325a: 687b ldr r3, [r7, #4] + 800325c: 4313 orrs r3, r2 + 800325e: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 8003262: bf00 nop + 8003264: 370c adds r7, #12 + 8003266: 46bd mov sp, r7 + 8003268: f85d 7b04 ldr.w r7, [sp], #4 + 800326c: 4770 bx lr + +0800326e <LL_RCC_SetUSBClockSource>: +{ + 800326e: b580 push {r7, lr} + 8003270: b082 sub sp, #8 + 8003272: af00 add r7, sp, #0 + 8003274: 6078 str r0, [r7, #4] + LL_RCC_SetCLK48ClockSource(USBxSource); + 8003276: 6878 ldr r0, [r7, #4] + 8003278: f7ff ffe3 bl 8003242 <LL_RCC_SetCLK48ClockSource> +} + 800327c: bf00 nop + 800327e: 3708 adds r7, #8 + 8003280: 46bd mov sp, r7 + 8003282: bd80 pop {r7, pc} + +08003284 <LL_RCC_SetADCClockSource>: +{ + 8003284: b480 push {r7} + 8003286: b083 sub sp, #12 + 8003288: af00 add r7, sp, #0 + 800328a: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); + 800328c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003290: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8003294: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000 + 8003298: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800329c: 687b ldr r3, [r7, #4] + 800329e: 4313 orrs r3, r2 + 80032a0: f8c1 3088 str.w r3, [r1, #136] @ 0x88 +} + 80032a4: bf00 nop + 80032a6: 370c adds r7, #12 + 80032a8: 46bd mov sp, r7 + 80032aa: f85d 7b04 ldr.w r7, [sp], #4 + 80032ae: 4770 bx lr + +080032b0 <LL_RCC_SetRTCClockSource>: +{ + 80032b0: b480 push {r7} + 80032b2: b083 sub sp, #12 + 80032b4: af00 add r7, sp, #0 + 80032b6: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); + 80032b8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80032bc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80032c0: f423 7240 bic.w r2, r3, #768 @ 0x300 + 80032c4: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80032c8: 687b ldr r3, [r7, #4] + 80032ca: 4313 orrs r3, r2 + 80032cc: f8c1 3090 str.w r3, [r1, #144] @ 0x90 +} + 80032d0: bf00 nop + 80032d2: 370c adds r7, #12 + 80032d4: 46bd mov sp, r7 + 80032d6: f85d 7b04 ldr.w r7, [sp], #4 + 80032da: 4770 bx lr + +080032dc <LL_RCC_GetRTCClockSource>: +{ + 80032dc: b480 push {r7} + 80032de: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); + 80032e0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80032e4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80032e8: f403 7340 and.w r3, r3, #768 @ 0x300 +} + 80032ec: 4618 mov r0, r3 + 80032ee: 46bd mov sp, r7 + 80032f0: f85d 7b04 ldr.w r7, [sp], #4 + 80032f4: 4770 bx lr + +080032f6 <LL_RCC_ForceBackupDomainReset>: +{ + 80032f6: b480 push {r7} + 80032f8: af00 add r7, sp, #0 + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); + 80032fa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80032fe: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003302: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003306: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 800330a: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 800330e: bf00 nop + 8003310: 46bd mov sp, r7 + 8003312: f85d 7b04 ldr.w r7, [sp], #4 + 8003316: 4770 bx lr + +08003318 <LL_RCC_ReleaseBackupDomainReset>: +{ + 8003318: b480 push {r7} + 800331a: af00 add r7, sp, #0 + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); + 800331c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003320: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8003324: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003328: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 800332c: f8c2 3090 str.w r3, [r2, #144] @ 0x90 +} + 8003330: bf00 nop + 8003332: 46bd mov sp, r7 + 8003334: f85d 7b04 ldr.w r7, [sp], #4 + 8003338: 4770 bx lr + +0800333a <LL_RCC_PLLSAI1_Enable>: +{ + 800333a: b480 push {r7} + 800333c: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON); + 800333e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003342: 681b ldr r3, [r3, #0] + 8003344: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003348: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 + 800334c: 6013 str r3, [r2, #0] +} + 800334e: bf00 nop + 8003350: 46bd mov sp, r7 + 8003352: f85d 7b04 ldr.w r7, [sp], #4 + 8003356: 4770 bx lr + +08003358 <LL_RCC_PLLSAI1_Disable>: +{ + 8003358: b480 push {r7} + 800335a: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON); + 800335c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003360: 681b ldr r3, [r3, #0] + 8003362: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003366: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 + 800336a: 6013 str r3, [r2, #0] +} + 800336c: bf00 nop + 800336e: 46bd mov sp, r7 + 8003370: f85d 7b04 ldr.w r7, [sp], #4 + 8003374: 4770 bx lr + +08003376 <LL_RCC_PLLSAI1_IsReady>: +{ + 8003376: b480 push {r7} + 8003378: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) ? 1UL : 0UL); + 800337a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800337e: 681b ldr r3, [r3, #0] + 8003380: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 + 8003384: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 + 8003388: d101 bne.n 800338e <LL_RCC_PLLSAI1_IsReady+0x18> + 800338a: 2301 movs r3, #1 + 800338c: e000 b.n 8003390 <LL_RCC_PLLSAI1_IsReady+0x1a> + 800338e: 2300 movs r3, #0 +} + 8003390: 4618 mov r0, r3 + 8003392: 46bd mov sp, r7 + 8003394: f85d 7b04 ldr.w r7, [sp], #4 + 8003398: 4770 bx lr + +0800339a <HAL_RCCEx_PeriphCLKConfig>: + * the RTC clock source: in this case the access to Backup domain is enabled. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + 800339a: b580 push {r7, lr} + 800339c: b088 sub sp, #32 + 800339e: af00 add r7, sp, #0 + 80033a0: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + 80033a2: 2300 movs r3, #0 + 80033a4: 77fb strb r3, [r7, #31] + HAL_StatusTypeDef status = HAL_OK; /* Final status */ + 80033a6: 2300 movs r3, #0 + 80033a8: 77bb strb r3, [r7, #30] + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + +#if defined(SAI1) + /*-------------------------- SAI1 clock source configuration ---------------------*/ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)) + 80033aa: 687b ldr r3, [r7, #4] + 80033ac: 681b ldr r3, [r3, #0] + 80033ae: f003 0340 and.w r3, r3, #64 @ 0x40 + 80033b2: 2b00 cmp r3, #0 + 80033b4: d034 beq.n 8003420 <HAL_RCCEx_PeriphCLKConfig+0x86> + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection)); + + switch (PeriphClkInit->Sai1ClockSelection) + 80033b6: 687b ldr r3, [r7, #4] + 80033b8: 6b1b ldr r3, [r3, #48] @ 0x30 + 80033ba: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000 + 80033be: d021 beq.n 8003404 <HAL_RCCEx_PeriphCLKConfig+0x6a> + 80033c0: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000 + 80033c4: d81b bhi.n 80033fe <HAL_RCCEx_PeriphCLKConfig+0x64> + 80033c6: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 + 80033ca: d01d beq.n 8003408 <HAL_RCCEx_PeriphCLKConfig+0x6e> + 80033cc: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 + 80033d0: d815 bhi.n 80033fe <HAL_RCCEx_PeriphCLKConfig+0x64> + 80033d2: 2b00 cmp r3, #0 + 80033d4: d00b beq.n 80033ee <HAL_RCCEx_PeriphCLKConfig+0x54> + 80033d6: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 + 80033da: d110 bne.n 80033fe <HAL_RCCEx_PeriphCLKConfig+0x64> + { + case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1 */ + /* Enable SAI1 Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI1CLK); + 80033dc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80033e0: 68db ldr r3, [r3, #12] + 80033e2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80033e6: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 80033ea: 60d3 str r3, [r2, #12] + + /* SAI1 clock source config set later after clock selection check */ + break; + 80033ec: e00d b.n 800340a <HAL_RCCEx_PeriphCLKConfig+0x70> + + case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1 */ + /* PLLSAI1 parameters N & P configuration and clock output (PLLSAI1ClockOut) */ + ret = RCCEx_PLLSAI1_ConfigNP(&(PeriphClkInit->PLLSAI1)); + 80033ee: 687b ldr r3, [r7, #4] + 80033f0: 3304 adds r3, #4 + 80033f2: 4618 mov r0, r3 + 80033f4: f000 f947 bl 8003686 <RCCEx_PLLSAI1_ConfigNP> + 80033f8: 4603 mov r3, r0 + 80033fa: 77fb strb r3, [r7, #31] + /* SAI1 clock source config set later after clock selection check */ + break; + 80033fc: e005 b.n 800340a <HAL_RCCEx_PeriphCLKConfig+0x70> + case RCC_SAI1CLKSOURCE_HSI: + + break; + + default: + ret = HAL_ERROR; + 80033fe: 2301 movs r3, #1 + 8003400: 77fb strb r3, [r7, #31] + break; + 8003402: e002 b.n 800340a <HAL_RCCEx_PeriphCLKConfig+0x70> + break; + 8003404: bf00 nop + 8003406: e000 b.n 800340a <HAL_RCCEx_PeriphCLKConfig+0x70> + break; + 8003408: bf00 nop + } + + if (ret == HAL_OK) + 800340a: 7ffb ldrb r3, [r7, #31] + 800340c: 2b00 cmp r3, #0 + 800340e: d105 bne.n 800341c <HAL_RCCEx_PeriphCLKConfig+0x82> + { + /* Set the source of SAI1 clock*/ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + 8003410: 687b ldr r3, [r7, #4] + 8003412: 6b1b ldr r3, [r3, #48] @ 0x30 + 8003414: 4618 mov r0, r3 + 8003416: f7ff fee8 bl 80031ea <LL_RCC_SetSAIClockSource> + 800341a: e001 b.n 8003420 <HAL_RCCEx_PeriphCLKConfig+0x86> + } + else + { + /* set overall return value */ + status = ret; + 800341c: 7ffb ldrb r3, [r7, #31] + 800341e: 77bb strb r3, [r7, #30] + } + } +#endif /* SAI1 */ + + /*-------------------------- RTC clock source configuration ----------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + 8003420: 687b ldr r3, [r7, #4] + 8003422: 681b ldr r3, [r3, #0] + 8003424: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8003428: 2b00 cmp r3, #0 + 800342a: d046 beq.n 80034ba <HAL_RCCEx_PeriphCLKConfig+0x120> + { + uint32_t rtcclocksource = LL_RCC_GetRTCClockSource(); + 800342c: f7ff ff56 bl 80032dc <LL_RCC_GetRTCClockSource> + 8003430: 61b8 str r0, [r7, #24] + + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Configure the clock source only if a different source is expected */ + if (rtcclocksource != PeriphClkInit->RTCClockSelection) + 8003432: 687b ldr r3, [r7, #4] + 8003434: 6c1b ldr r3, [r3, #64] @ 0x40 + 8003436: 69ba ldr r2, [r7, #24] + 8003438: 429a cmp r2, r3 + 800343a: d03c beq.n 80034b6 <HAL_RCCEx_PeriphCLKConfig+0x11c> + { + /* Enable write access to Backup domain */ + HAL_PWR_EnableBkUpAccess(); + 800343c: f7fe fc80 bl 8001d40 <HAL_PWR_EnableBkUpAccess> + + /* If a clock source is not yet selected */ + if (rtcclocksource == RCC_RTCCLKSOURCE_NONE) + 8003440: 69bb ldr r3, [r7, #24] + 8003442: 2b00 cmp r3, #0 + 8003444: d105 bne.n 8003452 <HAL_RCCEx_PeriphCLKConfig+0xb8> + { + /* Directly set the configuration of the clock source selection */ + LL_RCC_SetRTCClockSource(PeriphClkInit->RTCClockSelection); + 8003446: 687b ldr r3, [r7, #4] + 8003448: 6c1b ldr r3, [r3, #64] @ 0x40 + 800344a: 4618 mov r0, r3 + 800344c: f7ff ff30 bl 80032b0 <LL_RCC_SetRTCClockSource> + 8003450: e02e b.n 80034b0 <HAL_RCCEx_PeriphCLKConfig+0x116> + } + else /* A clock source is already selected */ + { + /* Store the content of BDCR register before the reset of Backup Domain */ + uint32_t bdcr = LL_RCC_ReadReg(BDCR); + 8003452: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003456: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 800345a: 617b str r3, [r7, #20] + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + LL_RCC_ForceBackupDomainReset(); + 800345c: f7ff ff4b bl 80032f6 <LL_RCC_ForceBackupDomainReset> + LL_RCC_ReleaseBackupDomainReset(); + 8003460: f7ff ff5a bl 8003318 <LL_RCC_ReleaseBackupDomainReset> + + /* Set the value of the clock source selection */ + MODIFY_REG(bdcr, RCC_BDCR_RTCSEL, PeriphClkInit->RTCClockSelection); + 8003464: 697b ldr r3, [r7, #20] + 8003466: f423 7240 bic.w r2, r3, #768 @ 0x300 + 800346a: 687b ldr r3, [r7, #4] + 800346c: 6c1b ldr r3, [r3, #64] @ 0x40 + 800346e: 4313 orrs r3, r2 + 8003470: 617b str r3, [r7, #20] + + /* Restore the content of BDCR register */ + LL_RCC_WriteReg(BDCR, bdcr); + 8003472: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003476: 697b ldr r3, [r7, #20] + 8003478: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (LL_RCC_LSE_IsEnabled() == 1U) + 800347c: f7ff fdf0 bl 8003060 <LL_RCC_LSE_IsEnabled> + 8003480: 4603 mov r3, r0 + 8003482: 2b01 cmp r3, #1 + 8003484: d114 bne.n 80034b0 <HAL_RCCEx_PeriphCLKConfig+0x116> + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003486: f7fd fef1 bl 800126c <HAL_GetTick> + 800348a: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while (LL_RCC_LSE_IsReady() != 1U) + 800348c: e00b b.n 80034a6 <HAL_RCCEx_PeriphCLKConfig+0x10c> + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 800348e: f7fd feed bl 800126c <HAL_GetTick> + 8003492: 4602 mov r2, r0 + 8003494: 693b ldr r3, [r7, #16] + 8003496: 1ad3 subs r3, r2, r3 + 8003498: f241 3288 movw r2, #5000 @ 0x1388 + 800349c: 4293 cmp r3, r2 + 800349e: d902 bls.n 80034a6 <HAL_RCCEx_PeriphCLKConfig+0x10c> + { + ret = HAL_TIMEOUT; + 80034a0: 2303 movs r3, #3 + 80034a2: 77fb strb r3, [r7, #31] + break; + 80034a4: e004 b.n 80034b0 <HAL_RCCEx_PeriphCLKConfig+0x116> + while (LL_RCC_LSE_IsReady() != 1U) + 80034a6: f7ff fded bl 8003084 <LL_RCC_LSE_IsReady> + 80034aa: 4603 mov r3, r0 + 80034ac: 2b01 cmp r3, #1 + 80034ae: d1ee bne.n 800348e <HAL_RCCEx_PeriphCLKConfig+0xf4> + } + } + } + + /* set overall return value */ + status = ret; + 80034b0: 7ffb ldrb r3, [r7, #31] + 80034b2: 77bb strb r3, [r7, #30] + 80034b4: e001 b.n 80034ba <HAL_RCCEx_PeriphCLKConfig+0x120> + } + else + { + /* set overall return value */ + status = ret; + 80034b6: 7ffb ldrb r3, [r7, #31] + 80034b8: 77bb strb r3, [r7, #30] + } + + } + + /*-------------------------- USART1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + 80034ba: 687b ldr r3, [r7, #4] + 80034bc: 681b ldr r3, [r3, #0] + 80034be: f003 0301 and.w r3, r3, #1 + 80034c2: 2b00 cmp r3, #0 + 80034c4: d004 beq.n 80034d0 <HAL_RCCEx_PeriphCLKConfig+0x136> + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + 80034c6: 687b ldr r3, [r7, #4] + 80034c8: 699b ldr r3, [r3, #24] + 80034ca: 4618 mov r0, r3 + 80034cc: f7ff fe2a bl 8003124 <LL_RCC_SetUSARTClockSource> + } + +#if defined(LPUART1) + /*-------------------------- LPUART1 clock source configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + 80034d0: 687b ldr r3, [r7, #4] + 80034d2: 681b ldr r3, [r3, #0] + 80034d4: f003 0302 and.w r3, r3, #2 + 80034d8: 2b00 cmp r3, #0 + 80034da: d004 beq.n 80034e6 <HAL_RCCEx_PeriphCLKConfig+0x14c> + { + /* Check the parameters */ + assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); + + /* Configure the LPUAR1 clock source */ + __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + 80034dc: 687b ldr r3, [r7, #4] + 80034de: 69db ldr r3, [r3, #28] + 80034e0: 4618 mov r0, r3 + 80034e2: f7ff fe35 bl 8003150 <LL_RCC_SetLPUARTClockSource> + } +#endif /* LPUART1 */ + + /*-------------------------- LPTIM1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) + 80034e6: 687b ldr r3, [r7, #4] + 80034e8: 681b ldr r3, [r3, #0] + 80034ea: f003 0310 and.w r3, r3, #16 + 80034ee: 2b00 cmp r3, #0 + 80034f0: d004 beq.n 80034fc <HAL_RCCEx_PeriphCLKConfig+0x162> + { + assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + 80034f2: 687b ldr r3, [r7, #4] + 80034f4: 6a9b ldr r3, [r3, #40] @ 0x28 + 80034f6: 4618 mov r0, r3 + 80034f8: f7ff fe5d bl 80031b6 <LL_RCC_SetLPTIMClockSource> + } + + /*-------------------------- LPTIM2 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) + 80034fc: 687b ldr r3, [r7, #4] + 80034fe: 681b ldr r3, [r3, #0] + 8003500: f003 0320 and.w r3, r3, #32 + 8003504: 2b00 cmp r3, #0 + 8003506: d004 beq.n 8003512 <HAL_RCCEx_PeriphCLKConfig+0x178> + { + assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection)); + __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); + 8003508: 687b ldr r3, [r7, #4] + 800350a: 6adb ldr r3, [r3, #44] @ 0x2c + 800350c: 4618 mov r0, r3 + 800350e: f7ff fe52 bl 80031b6 <LL_RCC_SetLPTIMClockSource> + } + + /*-------------------------- I2C1 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 8003512: 687b ldr r3, [r7, #4] + 8003514: 681b ldr r3, [r3, #0] + 8003516: f003 0304 and.w r3, r3, #4 + 800351a: 2b00 cmp r3, #0 + 800351c: d004 beq.n 8003528 <HAL_RCCEx_PeriphCLKConfig+0x18e> + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 800351e: 687b ldr r3, [r7, #4] + 8003520: 6a1b ldr r3, [r3, #32] + 8003522: 4618 mov r0, r3 + 8003524: f7ff fe2a bl 800317c <LL_RCC_SetI2CClockSource> + } + +#if defined(I2C3) + /*-------------------------- I2C3 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + 8003528: 687b ldr r3, [r7, #4] + 800352a: 681b ldr r3, [r3, #0] + 800352c: f003 0308 and.w r3, r3, #8 + 8003530: 2b00 cmp r3, #0 + 8003532: d004 beq.n 800353e <HAL_RCCEx_PeriphCLKConfig+0x1a4> + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + 8003534: 687b ldr r3, [r7, #4] + 8003536: 6a5b ldr r3, [r3, #36] @ 0x24 + 8003538: 4618 mov r0, r3 + 800353a: f7ff fe1f bl 800317c <LL_RCC_SetI2CClockSource> + } +#endif /* I2C3 */ + +#if defined(USB) + /*-------------------------- USB clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) + 800353e: 687b ldr r3, [r7, #4] + 8003540: 681b ldr r3, [r3, #0] + 8003542: f403 7380 and.w r3, r3, #256 @ 0x100 + 8003546: 2b00 cmp r3, #0 + 8003548: d022 beq.n 8003590 <HAL_RCCEx_PeriphCLKConfig+0x1f6> + { + assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + 800354a: 687b ldr r3, [r7, #4] + 800354c: 6b5b ldr r3, [r3, #52] @ 0x34 + 800354e: 4618 mov r0, r3 + 8003550: f7ff fe8d bl 800326e <LL_RCC_SetUSBClockSource> + + if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) + 8003554: 687b ldr r3, [r7, #4] + 8003556: 6b5b ldr r3, [r3, #52] @ 0x34 + 8003558: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 + 800355c: d107 bne.n 800356e <HAL_RCCEx_PeriphCLKConfig+0x1d4> + { + /* Enable PLLQ output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_USBCLK); + 800355e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003562: 68db ldr r3, [r3, #12] + 8003564: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 8003568: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 + 800356c: 60d3 str r3, [r2, #12] + } +#if defined(SAI1) + if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1) + 800356e: 687b ldr r3, [r7, #4] + 8003570: 6b5b ldr r3, [r3, #52] @ 0x34 + 8003572: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 + 8003576: d10b bne.n 8003590 <HAL_RCCEx_PeriphCLKConfig+0x1f6> + { + /* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */ + ret = RCCEx_PLLSAI1_ConfigNQ(&(PeriphClkInit->PLLSAI1)); + 8003578: 687b ldr r3, [r7, #4] + 800357a: 3304 adds r3, #4 + 800357c: 4618 mov r0, r3 + 800357e: f000 f8dd bl 800373c <RCCEx_PLLSAI1_ConfigNQ> + 8003582: 4603 mov r3, r0 + 8003584: 77fb strb r3, [r7, #31] + + if (ret != HAL_OK) + 8003586: 7ffb ldrb r3, [r7, #31] + 8003588: 2b00 cmp r3, #0 + 800358a: d001 beq.n 8003590 <HAL_RCCEx_PeriphCLKConfig+0x1f6> + { + /* set overall return value */ + status = ret; + 800358c: 7ffb ldrb r3, [r7, #31] + 800358e: 77bb strb r3, [r7, #30] +#endif /* SAI1 */ + } +#endif /* USB */ + + /*-------------------------- RNG clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) + 8003590: 687b ldr r3, [r7, #4] + 8003592: 681b ldr r3, [r3, #0] + 8003594: f403 7300 and.w r3, r3, #512 @ 0x200 + 8003598: 2b00 cmp r3, #0 + 800359a: d02b beq.n 80035f4 <HAL_RCCEx_PeriphCLKConfig+0x25a> + { + /* Check the parameters */ + assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); + + /* Configure the RNG clock source */ + __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); + 800359c: 687b ldr r3, [r7, #4] + 800359e: 6b9b ldr r3, [r3, #56] @ 0x38 + 80035a0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 80035a4: d008 beq.n 80035b8 <HAL_RCCEx_PeriphCLKConfig+0x21e> + 80035a6: 687b ldr r3, [r7, #4] + 80035a8: 6b9b ldr r3, [r3, #56] @ 0x38 + 80035aa: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 + 80035ae: d003 beq.n 80035b8 <HAL_RCCEx_PeriphCLKConfig+0x21e> + 80035b0: 687b ldr r3, [r7, #4] + 80035b2: 6b9b ldr r3, [r3, #56] @ 0x38 + 80035b4: 2b00 cmp r3, #0 + 80035b6: d105 bne.n 80035c4 <HAL_RCCEx_PeriphCLKConfig+0x22a> + 80035b8: 687b ldr r3, [r7, #4] + 80035ba: 6b9b ldr r3, [r3, #56] @ 0x38 + 80035bc: 4618 mov r0, r3 + 80035be: f7ff fe2a bl 8003216 <LL_RCC_SetRNGClockSource> + 80035c2: e00a b.n 80035da <HAL_RCCEx_PeriphCLKConfig+0x240> + 80035c4: 687b ldr r3, [r7, #4] + 80035c6: 6b9b ldr r3, [r3, #56] @ 0x38 + 80035c8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 80035cc: 60fb str r3, [r7, #12] + 80035ce: 2000 movs r0, #0 + 80035d0: f7ff fe21 bl 8003216 <LL_RCC_SetRNGClockSource> + 80035d4: 68f8 ldr r0, [r7, #12] + 80035d6: f7ff fe34 bl 8003242 <LL_RCC_SetCLK48ClockSource> + + if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) + 80035da: 687b ldr r3, [r7, #4] + 80035dc: 6b9b ldr r3, [r3, #56] @ 0x38 + 80035de: f1b3 5fc0 cmp.w r3, #402653184 @ 0x18000000 + 80035e2: d107 bne.n 80035f4 <HAL_RCCEx_PeriphCLKConfig+0x25a> + { + /* Enable PLLQ output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_RNGCLK); + 80035e4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80035e8: 68db ldr r3, [r3, #12] + 80035ea: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 80035ee: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 + 80035f2: 60d3 str r3, [r2, #12] + } + } + + /*-------------------------- ADC clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + 80035f4: 687b ldr r3, [r7, #4] + 80035f6: 681b ldr r3, [r3, #0] + 80035f8: f403 6380 and.w r3, r3, #1024 @ 0x400 + 80035fc: 2b00 cmp r3, #0 + 80035fe: d022 beq.n 8003646 <HAL_RCCEx_PeriphCLKConfig+0x2ac> + { + /* Check the parameters */ + assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); + + /* Configure the ADC interface clock source */ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + 8003600: 687b ldr r3, [r7, #4] + 8003602: 6bdb ldr r3, [r3, #60] @ 0x3c + 8003604: 4618 mov r0, r3 + 8003606: f7ff fe3d bl 8003284 <LL_RCC_SetADCClockSource> + + if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLL) + 800360a: 687b ldr r3, [r7, #4] + 800360c: 6bdb ldr r3, [r3, #60] @ 0x3c + 800360e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 + 8003612: d107 bne.n 8003624 <HAL_RCCEx_PeriphCLKConfig+0x28a> + { + /* Enable RCC_PLL_RNGCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); + 8003614: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003618: 68db ldr r3, [r3, #12] + 800361a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 + 800361e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8003622: 60d3 str r3, [r2, #12] + } + +#if defined(SAI1) + if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) + 8003624: 687b ldr r3, [r7, #4] + 8003626: 6bdb ldr r3, [r3, #60] @ 0x3c + 8003628: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 + 800362c: d10b bne.n 8003646 <HAL_RCCEx_PeriphCLKConfig+0x2ac> + { + /* PLLSAI1 parameters N & R configuration and clock output (PLLSAI1ClockOut) */ + ret = RCCEx_PLLSAI1_ConfigNR(&(PeriphClkInit->PLLSAI1)); + 800362e: 687b ldr r3, [r7, #4] + 8003630: 3304 adds r3, #4 + 8003632: 4618 mov r0, r3 + 8003634: f000 f8dd bl 80037f2 <RCCEx_PLLSAI1_ConfigNR> + 8003638: 4603 mov r3, r0 + 800363a: 77fb strb r3, [r7, #31] + + if (ret != HAL_OK) + 800363c: 7ffb ldrb r3, [r7, #31] + 800363e: 2b00 cmp r3, #0 + 8003640: d001 beq.n 8003646 <HAL_RCCEx_PeriphCLKConfig+0x2ac> + { + /* set overall return value */ + status = ret; + 8003642: 7ffb ldrb r3, [r7, #31] + 8003644: 77bb strb r3, [r7, #30] + } +#endif /* SAI1 */ + } + + /*-------------------------- RFWKP clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP) + 8003646: 687b ldr r3, [r7, #4] + 8003648: 681b ldr r3, [r3, #0] + 800364a: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 800364e: 2b00 cmp r3, #0 + 8003650: d004 beq.n 800365c <HAL_RCCEx_PeriphCLKConfig+0x2c2> + { + /* Check the parameters */ + assert_param(IS_RCC_RFWKPCLKSOURCE(PeriphClkInit->RFWakeUpClockSelection)); + + /* Configure the RFWKP interface clock source */ + __HAL_RCC_RFWAKEUP_CONFIG(PeriphClkInit->RFWakeUpClockSelection); + 8003652: 687b ldr r3, [r7, #4] + 8003654: 6c5b ldr r3, [r3, #68] @ 0x44 + 8003656: 4618 mov r0, r3 + 8003658: f7ff fd26 bl 80030a8 <LL_RCC_SetRFWKPClockSource> + + } + +#if defined(RCC_SMPS_SUPPORT) + /*-------------------------- SMPS clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS) + 800365c: 687b ldr r3, [r7, #4] + 800365e: 681b ldr r3, [r3, #0] + 8003660: f403 5300 and.w r3, r3, #8192 @ 0x2000 + 8003664: 2b00 cmp r3, #0 + 8003666: d009 beq.n 800367c <HAL_RCCEx_PeriphCLKConfig+0x2e2> + /* Check the parameters */ + assert_param(IS_RCC_SMPSCLKDIV(PeriphClkInit->SmpsDivSelection)); + assert_param(IS_RCC_SMPSCLKSOURCE(PeriphClkInit->SmpsClockSelection)); + + /* Configure the SMPS interface clock division factor */ + __HAL_RCC_SMPS_DIV_CONFIG(PeriphClkInit->SmpsDivSelection); + 8003668: 687b ldr r3, [r7, #4] + 800366a: 6cdb ldr r3, [r3, #76] @ 0x4c + 800366c: 4618 mov r0, r3 + 800366e: f7ff fd45 bl 80030fc <LL_RCC_SetSMPSPrescaler> + + /* Configure the SMPS interface clock source */ + __HAL_RCC_SMPS_CONFIG(PeriphClkInit->SmpsClockSelection); + 8003672: 687b ldr r3, [r7, #4] + 8003674: 6c9b ldr r3, [r3, #72] @ 0x48 + 8003676: 4618 mov r0, r3 + 8003678: f7ff fd2c bl 80030d4 <LL_RCC_SetSMPSClockSource> + } +#endif /* RCC_SMPS_SUPPORT */ + + return status; + 800367c: 7fbb ldrb r3, [r7, #30] +} + 800367e: 4618 mov r0, r3 + 8003680: 3720 adds r7, #32 + 8003682: 46bd mov sp, r7 + 8003684: bd80 pop {r7, pc} + +08003686 <RCCEx_PLLSAI1_ConfigNP>: + * @note PLLSAI1 is temporary disable to apply new parameters + * + * @retval HAL status + */ +static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNP(RCC_PLLSAI1InitTypeDef *PLLSAI1) +{ + 8003686: b580 push {r7, lr} + 8003688: b084 sub sp, #16 + 800368a: af00 add r7, sp, #0 + 800368c: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + 800368e: 2300 movs r3, #0 + 8003690: 73fb strb r3, [r7, #15] + assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN)); + assert_param(IS_RCC_PLLP_VALUE(PLLSAI1->PLLP)); + assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut)); + + /* Disable the PLLSAI1 */ + __HAL_RCC_PLLSAI1_DISABLE(); + 8003692: f7ff fe61 bl 8003358 <LL_RCC_PLLSAI1_Disable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003696: f7fd fde9 bl 800126c <HAL_GetTick> + 800369a: 60b8 str r0, [r7, #8] + + /* Wait till PLLSAI1 is ready to be updated */ + while (LL_RCC_PLLSAI1_IsReady() != 0U) + 800369c: e009 b.n 80036b2 <RCCEx_PLLSAI1_ConfigNP+0x2c> + { + if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) + 800369e: f7fd fde5 bl 800126c <HAL_GetTick> + 80036a2: 4602 mov r2, r0 + 80036a4: 68bb ldr r3, [r7, #8] + 80036a6: 1ad3 subs r3, r2, r3 + 80036a8: 2b02 cmp r3, #2 + 80036aa: d902 bls.n 80036b2 <RCCEx_PLLSAI1_ConfigNP+0x2c> + { + status = HAL_TIMEOUT; + 80036ac: 2303 movs r3, #3 + 80036ae: 73fb strb r3, [r7, #15] + break; + 80036b0: e004 b.n 80036bc <RCCEx_PLLSAI1_ConfigNP+0x36> + while (LL_RCC_PLLSAI1_IsReady() != 0U) + 80036b2: f7ff fe60 bl 8003376 <LL_RCC_PLLSAI1_IsReady> + 80036b6: 4603 mov r3, r0 + 80036b8: 2b00 cmp r3, #0 + 80036ba: d1f0 bne.n 800369e <RCCEx_PLLSAI1_ConfigNP+0x18> + } + } + + if (status == HAL_OK) + 80036bc: 7bfb ldrb r3, [r7, #15] + 80036be: 2b00 cmp r3, #0 + 80036c0: d137 bne.n 8003732 <RCCEx_PLLSAI1_ConfigNP+0xac> + { + /* Configure the PLLSAI1 Multiplication factor N */ + __HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN); + 80036c2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80036c6: 691b ldr r3, [r3, #16] + 80036c8: f423 42fe bic.w r2, r3, #32512 @ 0x7f00 + 80036cc: 687b ldr r3, [r7, #4] + 80036ce: 681b ldr r3, [r3, #0] + 80036d0: 021b lsls r3, r3, #8 + 80036d2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80036d6: 4313 orrs r3, r2 + 80036d8: 610b str r3, [r1, #16] + + /* Configure the PLLSAI1 Division factor P */ + __HAL_RCC_PLLSAI1_DIVP_CONFIG(PLLSAI1->PLLP); + 80036da: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80036de: 691b ldr r3, [r3, #16] + 80036e0: f423 1278 bic.w r2, r3, #4063232 @ 0x3e0000 + 80036e4: 687b ldr r3, [r7, #4] + 80036e6: 685b ldr r3, [r3, #4] + 80036e8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80036ec: 4313 orrs r3, r2 + 80036ee: 610b str r3, [r1, #16] + + /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ + __HAL_RCC_PLLSAI1_ENABLE(); + 80036f0: f7ff fe23 bl 800333a <LL_RCC_PLLSAI1_Enable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80036f4: f7fd fdba bl 800126c <HAL_GetTick> + 80036f8: 60b8 str r0, [r7, #8] + + /* Wait till PLLSAI1 is ready */ + while (LL_RCC_PLLSAI1_IsReady() != 1U) + 80036fa: e009 b.n 8003710 <RCCEx_PLLSAI1_ConfigNP+0x8a> + { + if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) + 80036fc: f7fd fdb6 bl 800126c <HAL_GetTick> + 8003700: 4602 mov r2, r0 + 8003702: 68bb ldr r3, [r7, #8] + 8003704: 1ad3 subs r3, r2, r3 + 8003706: 2b02 cmp r3, #2 + 8003708: d902 bls.n 8003710 <RCCEx_PLLSAI1_ConfigNP+0x8a> + { + status = HAL_TIMEOUT; + 800370a: 2303 movs r3, #3 + 800370c: 73fb strb r3, [r7, #15] + break; + 800370e: e004 b.n 800371a <RCCEx_PLLSAI1_ConfigNP+0x94> + while (LL_RCC_PLLSAI1_IsReady() != 1U) + 8003710: f7ff fe31 bl 8003376 <LL_RCC_PLLSAI1_IsReady> + 8003714: 4603 mov r3, r0 + 8003716: 2b01 cmp r3, #1 + 8003718: d1f0 bne.n 80036fc <RCCEx_PLLSAI1_ConfigNP+0x76> + } + } + + if (status == HAL_OK) + 800371a: 7bfb ldrb r3, [r7, #15] + 800371c: 2b00 cmp r3, #0 + 800371e: d108 bne.n 8003732 <RCCEx_PLLSAI1_ConfigNP+0xac> + { + /* Configure the PLLSAI1 Clock output(s) */ + __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut); + 8003720: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003724: 691a ldr r2, [r3, #16] + 8003726: 687b ldr r3, [r7, #4] + 8003728: 691b ldr r3, [r3, #16] + 800372a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800372e: 4313 orrs r3, r2 + 8003730: 610b str r3, [r1, #16] + } + } + + return status; + 8003732: 7bfb ldrb r3, [r7, #15] +} + 8003734: 4618 mov r0, r3 + 8003736: 3710 adds r7, #16 + 8003738: 46bd mov sp, r7 + 800373a: bd80 pop {r7, pc} + +0800373c <RCCEx_PLLSAI1_ConfigNQ>: + * @note PLLSAI1 is temporary disable to apply new parameters + * + * @retval HAL status + */ +static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNQ(RCC_PLLSAI1InitTypeDef *PLLSAI1) +{ + 800373c: b580 push {r7, lr} + 800373e: b084 sub sp, #16 + 8003740: af00 add r7, sp, #0 + 8003742: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + 8003744: 2300 movs r3, #0 + 8003746: 73fb strb r3, [r7, #15] + assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN)); + assert_param(IS_RCC_PLLQ_VALUE(PLLSAI1->PLLQ)); + assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut)); + + /* Disable the PLLSAI1 */ + __HAL_RCC_PLLSAI1_DISABLE(); + 8003748: f7ff fe06 bl 8003358 <LL_RCC_PLLSAI1_Disable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800374c: f7fd fd8e bl 800126c <HAL_GetTick> + 8003750: 60b8 str r0, [r7, #8] + + /* Wait till PLLSAI1 is ready to be updated */ + while (LL_RCC_PLLSAI1_IsReady() != 0U) + 8003752: e009 b.n 8003768 <RCCEx_PLLSAI1_ConfigNQ+0x2c> + { + if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) + 8003754: f7fd fd8a bl 800126c <HAL_GetTick> + 8003758: 4602 mov r2, r0 + 800375a: 68bb ldr r3, [r7, #8] + 800375c: 1ad3 subs r3, r2, r3 + 800375e: 2b02 cmp r3, #2 + 8003760: d902 bls.n 8003768 <RCCEx_PLLSAI1_ConfigNQ+0x2c> + { + status = HAL_TIMEOUT; + 8003762: 2303 movs r3, #3 + 8003764: 73fb strb r3, [r7, #15] + break; + 8003766: e004 b.n 8003772 <RCCEx_PLLSAI1_ConfigNQ+0x36> + while (LL_RCC_PLLSAI1_IsReady() != 0U) + 8003768: f7ff fe05 bl 8003376 <LL_RCC_PLLSAI1_IsReady> + 800376c: 4603 mov r3, r0 + 800376e: 2b00 cmp r3, #0 + 8003770: d1f0 bne.n 8003754 <RCCEx_PLLSAI1_ConfigNQ+0x18> + } + } + + if (status == HAL_OK) + 8003772: 7bfb ldrb r3, [r7, #15] + 8003774: 2b00 cmp r3, #0 + 8003776: d137 bne.n 80037e8 <RCCEx_PLLSAI1_ConfigNQ+0xac> + { + /* Configure the PLLSAI1 Multiplication factor N */ + __HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN); + 8003778: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800377c: 691b ldr r3, [r3, #16] + 800377e: f423 42fe bic.w r2, r3, #32512 @ 0x7f00 + 8003782: 687b ldr r3, [r7, #4] + 8003784: 681b ldr r3, [r3, #0] + 8003786: 021b lsls r3, r3, #8 + 8003788: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800378c: 4313 orrs r3, r2 + 800378e: 610b str r3, [r1, #16] + /* Configure the PLLSAI1 Division factor Q */ + __HAL_RCC_PLLSAI1_DIVQ_CONFIG(PLLSAI1->PLLQ); + 8003790: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003794: 691b ldr r3, [r3, #16] + 8003796: f023 6260 bic.w r2, r3, #234881024 @ 0xe000000 + 800379a: 687b ldr r3, [r7, #4] + 800379c: 689b ldr r3, [r3, #8] + 800379e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80037a2: 4313 orrs r3, r2 + 80037a4: 610b str r3, [r1, #16] + + /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ + __HAL_RCC_PLLSAI1_ENABLE(); + 80037a6: f7ff fdc8 bl 800333a <LL_RCC_PLLSAI1_Enable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80037aa: f7fd fd5f bl 800126c <HAL_GetTick> + 80037ae: 60b8 str r0, [r7, #8] + + /* Wait till PLLSAI1 is ready */ + while (LL_RCC_PLLSAI1_IsReady() != 1U) + 80037b0: e009 b.n 80037c6 <RCCEx_PLLSAI1_ConfigNQ+0x8a> + { + if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) + 80037b2: f7fd fd5b bl 800126c <HAL_GetTick> + 80037b6: 4602 mov r2, r0 + 80037b8: 68bb ldr r3, [r7, #8] + 80037ba: 1ad3 subs r3, r2, r3 + 80037bc: 2b02 cmp r3, #2 + 80037be: d902 bls.n 80037c6 <RCCEx_PLLSAI1_ConfigNQ+0x8a> + { + status = HAL_TIMEOUT; + 80037c0: 2303 movs r3, #3 + 80037c2: 73fb strb r3, [r7, #15] + break; + 80037c4: e004 b.n 80037d0 <RCCEx_PLLSAI1_ConfigNQ+0x94> + while (LL_RCC_PLLSAI1_IsReady() != 1U) + 80037c6: f7ff fdd6 bl 8003376 <LL_RCC_PLLSAI1_IsReady> + 80037ca: 4603 mov r3, r0 + 80037cc: 2b01 cmp r3, #1 + 80037ce: d1f0 bne.n 80037b2 <RCCEx_PLLSAI1_ConfigNQ+0x76> + } + } + + if (status == HAL_OK) + 80037d0: 7bfb ldrb r3, [r7, #15] + 80037d2: 2b00 cmp r3, #0 + 80037d4: d108 bne.n 80037e8 <RCCEx_PLLSAI1_ConfigNQ+0xac> + { + /* Configure the PLLSAI1 Clock output(s) */ + __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut); + 80037d6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 80037da: 691a ldr r2, [r3, #16] + 80037dc: 687b ldr r3, [r7, #4] + 80037de: 691b ldr r3, [r3, #16] + 80037e0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 80037e4: 4313 orrs r3, r2 + 80037e6: 610b str r3, [r1, #16] + } + } + + return status; + 80037e8: 7bfb ldrb r3, [r7, #15] +} + 80037ea: 4618 mov r0, r3 + 80037ec: 3710 adds r7, #16 + 80037ee: 46bd mov sp, r7 + 80037f0: bd80 pop {r7, pc} + +080037f2 <RCCEx_PLLSAI1_ConfigNR>: + * @note PLLSAI1 is temporary disable to apply new parameters + * + * @retval HAL status + */ +static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNR(RCC_PLLSAI1InitTypeDef *PLLSAI1) +{ + 80037f2: b580 push {r7, lr} + 80037f4: b084 sub sp, #16 + 80037f6: af00 add r7, sp, #0 + 80037f8: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + 80037fa: 2300 movs r3, #0 + 80037fc: 73fb strb r3, [r7, #15] + assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN)); + assert_param(IS_RCC_PLLR_VALUE(PLLSAI1->PLLR)); + assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut)); + + /* Disable the PLLSAI1 */ + __HAL_RCC_PLLSAI1_DISABLE(); + 80037fe: f7ff fdab bl 8003358 <LL_RCC_PLLSAI1_Disable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003802: f7fd fd33 bl 800126c <HAL_GetTick> + 8003806: 60b8 str r0, [r7, #8] + + /* Wait till PLLSAI1 is ready to be updated */ + while (LL_RCC_PLLSAI1_IsReady() != 0U) + 8003808: e009 b.n 800381e <RCCEx_PLLSAI1_ConfigNR+0x2c> + { + if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) + 800380a: f7fd fd2f bl 800126c <HAL_GetTick> + 800380e: 4602 mov r2, r0 + 8003810: 68bb ldr r3, [r7, #8] + 8003812: 1ad3 subs r3, r2, r3 + 8003814: 2b02 cmp r3, #2 + 8003816: d902 bls.n 800381e <RCCEx_PLLSAI1_ConfigNR+0x2c> + { + status = HAL_TIMEOUT; + 8003818: 2303 movs r3, #3 + 800381a: 73fb strb r3, [r7, #15] + break; + 800381c: e004 b.n 8003828 <RCCEx_PLLSAI1_ConfigNR+0x36> + while (LL_RCC_PLLSAI1_IsReady() != 0U) + 800381e: f7ff fdaa bl 8003376 <LL_RCC_PLLSAI1_IsReady> + 8003822: 4603 mov r3, r0 + 8003824: 2b00 cmp r3, #0 + 8003826: d1f0 bne.n 800380a <RCCEx_PLLSAI1_ConfigNR+0x18> + } + } + + if (status == HAL_OK) + 8003828: 7bfb ldrb r3, [r7, #15] + 800382a: 2b00 cmp r3, #0 + 800382c: d137 bne.n 800389e <RCCEx_PLLSAI1_ConfigNR+0xac> + { + /* Configure the PLLSAI1 Multiplication factor N */ + __HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN); + 800382e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003832: 691b ldr r3, [r3, #16] + 8003834: f423 42fe bic.w r2, r3, #32512 @ 0x7f00 + 8003838: 687b ldr r3, [r7, #4] + 800383a: 681b ldr r3, [r3, #0] + 800383c: 021b lsls r3, r3, #8 + 800383e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003842: 4313 orrs r3, r2 + 8003844: 610b str r3, [r1, #16] + /* Configure the PLLSAI1 Division factor R */ + __HAL_RCC_PLLSAI1_DIVR_CONFIG(PLLSAI1->PLLR); + 8003846: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 800384a: 691b ldr r3, [r3, #16] + 800384c: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 + 8003850: 687b ldr r3, [r7, #4] + 8003852: 68db ldr r3, [r3, #12] + 8003854: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 8003858: 4313 orrs r3, r2 + 800385a: 610b str r3, [r1, #16] + + /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ + __HAL_RCC_PLLSAI1_ENABLE(); + 800385c: f7ff fd6d bl 800333a <LL_RCC_PLLSAI1_Enable> + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003860: f7fd fd04 bl 800126c <HAL_GetTick> + 8003864: 60b8 str r0, [r7, #8] + + /* Wait till PLLSAI1 is ready */ + while (LL_RCC_PLLSAI1_IsReady() != 1U) + 8003866: e009 b.n 800387c <RCCEx_PLLSAI1_ConfigNR+0x8a> + { + if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) + 8003868: f7fd fd00 bl 800126c <HAL_GetTick> + 800386c: 4602 mov r2, r0 + 800386e: 68bb ldr r3, [r7, #8] + 8003870: 1ad3 subs r3, r2, r3 + 8003872: 2b02 cmp r3, #2 + 8003874: d902 bls.n 800387c <RCCEx_PLLSAI1_ConfigNR+0x8a> + { + status = HAL_TIMEOUT; + 8003876: 2303 movs r3, #3 + 8003878: 73fb strb r3, [r7, #15] + break; + 800387a: e004 b.n 8003886 <RCCEx_PLLSAI1_ConfigNR+0x94> + while (LL_RCC_PLLSAI1_IsReady() != 1U) + 800387c: f7ff fd7b bl 8003376 <LL_RCC_PLLSAI1_IsReady> + 8003880: 4603 mov r3, r0 + 8003882: 2b01 cmp r3, #1 + 8003884: d1f0 bne.n 8003868 <RCCEx_PLLSAI1_ConfigNR+0x76> + } + } + + if (status == HAL_OK) + 8003886: 7bfb ldrb r3, [r7, #15] + 8003888: 2b00 cmp r3, #0 + 800388a: d108 bne.n 800389e <RCCEx_PLLSAI1_ConfigNR+0xac> + { + /* Configure the PLLSAI1 Clock output(s) */ + __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut); + 800388c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 + 8003890: 691a ldr r2, [r3, #16] + 8003892: 687b ldr r3, [r7, #4] + 8003894: 691b ldr r3, [r3, #16] + 8003896: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 + 800389a: 4313 orrs r3, r2 + 800389c: 610b str r3, [r1, #16] + } + } + + return status; + 800389e: 7bfb ldrb r3, [r7, #15] +} + 80038a0: 4618 mov r0, r3 + 80038a2: 3710 adds r7, #16 + 80038a4: 46bd mov sp, r7 + 80038a6: bd80 pop {r7, pc} + +080038a8 <HAL_RTC_Init>: + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) +{ + 80038a8: b580 push {r7, lr} + 80038aa: b084 sub sp, #16 + 80038ac: af00 add r7, sp, #0 + 80038ae: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status; + + /* Check RTC handler validity */ + if (hrtc == NULL) + 80038b0: 687b ldr r3, [r7, #4] + 80038b2: 2b00 cmp r3, #0 + 80038b4: d101 bne.n 80038ba <HAL_RTC_Init+0x12> + { + return HAL_ERROR; + 80038b6: 2301 movs r3, #1 + 80038b8: e07a b.n 80039b0 <HAL_RTC_Init+0x108> + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + } +#else /* USE_HAL_RTC_REGISTER_CALLBACKS */ + if (hrtc->State == HAL_RTC_STATE_RESET) + 80038ba: 687b ldr r3, [r7, #4] + 80038bc: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 + 80038c0: b2db uxtb r3, r3 + 80038c2: 2b00 cmp r3, #0 + 80038c4: d106 bne.n 80038d4 <HAL_RTC_Init+0x2c> + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + 80038c6: 687b ldr r3, [r7, #4] + 80038c8: 2200 movs r2, #0 + 80038ca: f883 2020 strb.w r2, [r3, #32] + + /* Initialize RTC MSP */ + HAL_RTC_MspInit(hrtc); + 80038ce: 6878 ldr r0, [r7, #4] + 80038d0: f7fd fae4 bl 8000e9c <HAL_RTC_MspInit> + } +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + 80038d4: 687b ldr r3, [r7, #4] + 80038d6: 2202 movs r2, #2 + 80038d8: f883 2021 strb.w r2, [r3, #33] @ 0x21 + + /* Check whether the calendar needs to be initialized */ + if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) + 80038dc: 687b ldr r3, [r7, #4] + 80038de: 681b ldr r3, [r3, #0] + 80038e0: 68db ldr r3, [r3, #12] + 80038e2: f003 0310 and.w r3, r3, #16 + 80038e6: 2b10 cmp r3, #16 + 80038e8: d058 beq.n 800399c <HAL_RTC_Init+0xf4> + { + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 80038ea: 687b ldr r3, [r7, #4] + 80038ec: 681b ldr r3, [r3, #0] + 80038ee: 22ca movs r2, #202 @ 0xca + 80038f0: 625a str r2, [r3, #36] @ 0x24 + 80038f2: 687b ldr r3, [r7, #4] + 80038f4: 681b ldr r3, [r3, #0] + 80038f6: 2253 movs r2, #83 @ 0x53 + 80038f8: 625a str r2, [r3, #36] @ 0x24 + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + 80038fa: 6878 ldr r0, [r7, #4] + 80038fc: f000 fa58 bl 8003db0 <RTC_EnterInitMode> + 8003900: 4603 mov r3, r0 + 8003902: 73fb strb r3, [r7, #15] + + if (status == HAL_OK) + 8003904: 7bfb ldrb r3, [r7, #15] + 8003906: 2b00 cmp r3, #0 + 8003908: d12c bne.n 8003964 <HAL_RTC_Init+0xbc> + { + /* Clear RTC_CR FMT, OSEL and POL Bits */ + hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); + 800390a: 687b ldr r3, [r7, #4] + 800390c: 681b ldr r3, [r3, #0] + 800390e: 689b ldr r3, [r3, #8] + 8003910: 687a ldr r2, [r7, #4] + 8003912: 6812 ldr r2, [r2, #0] + 8003914: f423 03e0 bic.w r3, r3, #7340032 @ 0x700000 + 8003918: f023 0340 bic.w r3, r3, #64 @ 0x40 + 800391c: 6093 str r3, [r2, #8] + /* Set RTC_CR register */ + hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); + 800391e: 687b ldr r3, [r7, #4] + 8003920: 681b ldr r3, [r3, #0] + 8003922: 6899 ldr r1, [r3, #8] + 8003924: 687b ldr r3, [r7, #4] + 8003926: 685a ldr r2, [r3, #4] + 8003928: 687b ldr r3, [r7, #4] + 800392a: 691b ldr r3, [r3, #16] + 800392c: 431a orrs r2, r3 + 800392e: 687b ldr r3, [r7, #4] + 8003930: 699b ldr r3, [r3, #24] + 8003932: 431a orrs r2, r3 + 8003934: 687b ldr r3, [r7, #4] + 8003936: 681b ldr r3, [r3, #0] + 8003938: 430a orrs r2, r1 + 800393a: 609a str r2, [r3, #8] + + /* Configure the RTC PRER */ + hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); + 800393c: 687b ldr r3, [r7, #4] + 800393e: 681b ldr r3, [r3, #0] + 8003940: 687a ldr r2, [r7, #4] + 8003942: 68d2 ldr r2, [r2, #12] + 8003944: 611a str r2, [r3, #16] + hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos); + 8003946: 687b ldr r3, [r7, #4] + 8003948: 681b ldr r3, [r3, #0] + 800394a: 6919 ldr r1, [r3, #16] + 800394c: 687b ldr r3, [r7, #4] + 800394e: 689b ldr r3, [r3, #8] + 8003950: 041a lsls r2, r3, #16 + 8003952: 687b ldr r3, [r7, #4] + 8003954: 681b ldr r3, [r3, #0] + 8003956: 430a orrs r2, r1 + 8003958: 611a str r2, [r3, #16] + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + 800395a: 6878 ldr r0, [r7, #4] + 800395c: f000 fa60 bl 8003e20 <RTC_ExitInitMode> + 8003960: 4603 mov r3, r0 + 8003962: 73fb strb r3, [r7, #15] + } + + if (status == HAL_OK) + 8003964: 7bfb ldrb r3, [r7, #15] + 8003966: 2b00 cmp r3, #0 + 8003968: d113 bne.n 8003992 <HAL_RTC_Init+0xea> + { +#if defined(RTC_OR_ALARMOUTTYPE) + hrtc->Instance->OR &= (uint32_t)~(RTC_OUTPUT_TYPE_PUSHPULL | RTC_OUTPUT_REMAP_POS1); + 800396a: 687b ldr r3, [r7, #4] + 800396c: 681b ldr r3, [r3, #0] + 800396e: 6cda ldr r2, [r3, #76] @ 0x4c + 8003970: 687b ldr r3, [r7, #4] + 8003972: 681b ldr r3, [r3, #0] + 8003974: f022 0203 bic.w r2, r2, #3 + 8003978: 64da str r2, [r3, #76] @ 0x4c + hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + 800397a: 687b ldr r3, [r7, #4] + 800397c: 681b ldr r3, [r3, #0] + 800397e: 6cd9 ldr r1, [r3, #76] @ 0x4c + 8003980: 687b ldr r3, [r7, #4] + 8003982: 69da ldr r2, [r3, #28] + 8003984: 687b ldr r3, [r7, #4] + 8003986: 695b ldr r3, [r3, #20] + 8003988: 431a orrs r2, r3 + 800398a: 687b ldr r3, [r7, #4] + 800398c: 681b ldr r3, [r3, #0] + 800398e: 430a orrs r2, r1 + 8003990: 64da str r2, [r3, #76] @ 0x4c + hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutRemap); +#endif /* RTC_OR_ALARMOUTTYPE */ + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8003992: 687b ldr r3, [r7, #4] + 8003994: 681b ldr r3, [r3, #0] + 8003996: 22ff movs r2, #255 @ 0xff + 8003998: 625a str r2, [r3, #36] @ 0x24 + 800399a: e001 b.n 80039a0 <HAL_RTC_Init+0xf8> + } + else + { + /* The calendar is already initialized */ + status = HAL_OK; + 800399c: 2300 movs r3, #0 + 800399e: 73fb strb r3, [r7, #15] + } + + if (status == HAL_OK) + 80039a0: 7bfb ldrb r3, [r7, #15] + 80039a2: 2b00 cmp r3, #0 + 80039a4: d103 bne.n 80039ae <HAL_RTC_Init+0x106> + { + hrtc->State = HAL_RTC_STATE_READY; + 80039a6: 687b ldr r3, [r7, #4] + 80039a8: 2201 movs r2, #1 + 80039aa: f883 2021 strb.w r2, [r3, #33] @ 0x21 + } + + return status; + 80039ae: 7bfb ldrb r3, [r7, #15] +} + 80039b0: 4618 mov r0, r3 + 80039b2: 3710 adds r7, #16 + 80039b4: 46bd mov sp, r7 + 80039b6: bd80 pop {r7, pc} + +080039b8 <HAL_RTC_SetTime>: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + 80039b8: b590 push {r4, r7, lr} + 80039ba: b087 sub sp, #28 + 80039bc: af00 add r7, sp, #0 + 80039be: 60f8 str r0, [r7, #12] + 80039c0: 60b9 str r1, [r7, #8] + 80039c2: 607a str r2, [r7, #4] + uint32_t tmpreg = 0U; + 80039c4: 2300 movs r3, #0 + 80039c6: 617b str r3, [r7, #20] + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); + assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + 80039c8: 68fb ldr r3, [r7, #12] + 80039ca: f893 3020 ldrb.w r3, [r3, #32] + 80039ce: 2b01 cmp r3, #1 + 80039d0: d101 bne.n 80039d6 <HAL_RTC_SetTime+0x1e> + 80039d2: 2302 movs r3, #2 + 80039d4: e08b b.n 8003aee <HAL_RTC_SetTime+0x136> + 80039d6: 68fb ldr r3, [r7, #12] + 80039d8: 2201 movs r2, #1 + 80039da: f883 2020 strb.w r2, [r3, #32] + + hrtc->State = HAL_RTC_STATE_BUSY; + 80039de: 68fb ldr r3, [r7, #12] + 80039e0: 2202 movs r2, #2 + 80039e2: f883 2021 strb.w r2, [r3, #33] @ 0x21 + + if (Format == RTC_FORMAT_BIN) + 80039e6: 687b ldr r3, [r7, #4] + 80039e8: 2b00 cmp r3, #0 + 80039ea: d126 bne.n 8003a3a <HAL_RTC_SetTime+0x82> + { + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) + 80039ec: 68fb ldr r3, [r7, #12] + 80039ee: 681b ldr r3, [r3, #0] + 80039f0: 689b ldr r3, [r3, #8] + 80039f2: f003 0340 and.w r3, r3, #64 @ 0x40 + 80039f6: 2b00 cmp r3, #0 + 80039f8: d102 bne.n 8003a00 <HAL_RTC_SetTime+0x48> + assert_param(IS_RTC_HOUR12(sTime->Hours)); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00U; + 80039fa: 68bb ldr r3, [r7, #8] + 80039fc: 2200 movs r2, #0 + 80039fe: 70da strb r2, [r3, #3] + assert_param(IS_RTC_HOUR24(sTime->Hours)); + } + assert_param(IS_RTC_MINUTES(sTime->Minutes)); + assert_param(IS_RTC_SECONDS(sTime->Seconds)); + + tmpreg = (uint32_t)(( (uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ + 8003a00: 68bb ldr r3, [r7, #8] + 8003a02: 781b ldrb r3, [r3, #0] + 8003a04: 4618 mov r0, r3 + 8003a06: f000 fa31 bl 8003e6c <RTC_ByteToBcd2> + 8003a0a: 4603 mov r3, r0 + 8003a0c: 041c lsls r4, r3, #16 + ( (uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + 8003a0e: 68bb ldr r3, [r7, #8] + 8003a10: 785b ldrb r3, [r3, #1] + 8003a12: 4618 mov r0, r3 + 8003a14: f000 fa2a bl 8003e6c <RTC_ByteToBcd2> + 8003a18: 4603 mov r3, r0 + 8003a1a: 021b lsls r3, r3, #8 + tmpreg = (uint32_t)(( (uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ + 8003a1c: 431c orrs r4, r3 + ( (uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ + 8003a1e: 68bb ldr r3, [r7, #8] + 8003a20: 789b ldrb r3, [r3, #2] + 8003a22: 4618 mov r0, r3 + 8003a24: f000 fa22 bl 8003e6c <RTC_ByteToBcd2> + 8003a28: 4603 mov r3, r0 + ( (uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + 8003a2a: ea44 0203 orr.w r2, r4, r3 + (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos)); + 8003a2e: 68bb ldr r3, [r7, #8] + 8003a30: 78db ldrb r3, [r3, #3] + 8003a32: 059b lsls r3, r3, #22 + tmpreg = (uint32_t)(( (uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ + 8003a34: 4313 orrs r3, r2 + 8003a36: 617b str r3, [r7, #20] + 8003a38: e018 b.n 8003a6c <HAL_RTC_SetTime+0xb4> + } + else + { + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) + 8003a3a: 68fb ldr r3, [r7, #12] + 8003a3c: 681b ldr r3, [r3, #0] + 8003a3e: 689b ldr r3, [r3, #8] + 8003a40: f003 0340 and.w r3, r3, #64 @ 0x40 + 8003a44: 2b00 cmp r3, #0 + 8003a46: d102 bne.n 8003a4e <HAL_RTC_SetTime+0x96> + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours))); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00U; + 8003a48: 68bb ldr r3, [r7, #8] + 8003a4a: 2200 movs r2, #0 + 8003a4c: 70da strb r2, [r3, #3] + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); + tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ + 8003a4e: 68bb ldr r3, [r7, #8] + 8003a50: 781b ldrb r3, [r3, #0] + 8003a52: 041a lsls r2, r3, #16 + ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + 8003a54: 68bb ldr r3, [r7, #8] + 8003a56: 785b ldrb r3, [r3, #1] + 8003a58: 021b lsls r3, r3, #8 + tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ + 8003a5a: 4313 orrs r3, r2 + ((uint32_t) sTime->Seconds) | \ + 8003a5c: 68ba ldr r2, [r7, #8] + 8003a5e: 7892 ldrb r2, [r2, #2] + ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + 8003a60: 431a orrs r2, r3 + ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos)); + 8003a62: 68bb ldr r3, [r7, #8] + 8003a64: 78db ldrb r3, [r3, #3] + 8003a66: 059b lsls r3, r3, #22 + tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ + 8003a68: 4313 orrs r3, r2 + 8003a6a: 617b str r3, [r7, #20] + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8003a6c: 68fb ldr r3, [r7, #12] + 8003a6e: 681b ldr r3, [r3, #0] + 8003a70: 22ca movs r2, #202 @ 0xca + 8003a72: 625a str r2, [r3, #36] @ 0x24 + 8003a74: 68fb ldr r3, [r7, #12] + 8003a76: 681b ldr r3, [r3, #0] + 8003a78: 2253 movs r2, #83 @ 0x53 + 8003a7a: 625a str r2, [r3, #36] @ 0x24 + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + 8003a7c: 68f8 ldr r0, [r7, #12] + 8003a7e: f000 f997 bl 8003db0 <RTC_EnterInitMode> + 8003a82: 4603 mov r3, r0 + 8003a84: 74fb strb r3, [r7, #19] + + if (status == HAL_OK) + 8003a86: 7cfb ldrb r3, [r7, #19] + 8003a88: 2b00 cmp r3, #0 + 8003a8a: d120 bne.n 8003ace <HAL_RTC_SetTime+0x116> + { + /* Set the RTC_TR register */ + hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); + 8003a8c: 68fb ldr r3, [r7, #12] + 8003a8e: 681a ldr r2, [r3, #0] + 8003a90: 697b ldr r3, [r7, #20] + 8003a92: f003 337f and.w r3, r3, #2139062143 @ 0x7f7f7f7f + 8003a96: f023 43fe bic.w r3, r3, #2130706432 @ 0x7f000000 + 8003a9a: 6013 str r3, [r2, #0] + + /* Clear the bits to be configured (Deprecated. Use HAL_RTC_DST_xxx functions instead) */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP; + 8003a9c: 68fb ldr r3, [r7, #12] + 8003a9e: 681b ldr r3, [r3, #0] + 8003aa0: 689a ldr r2, [r3, #8] + 8003aa2: 68fb ldr r3, [r7, #12] + 8003aa4: 681b ldr r3, [r3, #0] + 8003aa6: f422 2280 bic.w r2, r2, #262144 @ 0x40000 + 8003aaa: 609a str r2, [r3, #8] + + /* Configure the RTC_CR register (Deprecated. Use HAL_RTC_DST_xxx functions instead) */ + hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); + 8003aac: 68fb ldr r3, [r7, #12] + 8003aae: 681b ldr r3, [r3, #0] + 8003ab0: 6899 ldr r1, [r3, #8] + 8003ab2: 68bb ldr r3, [r7, #8] + 8003ab4: 68da ldr r2, [r3, #12] + 8003ab6: 68bb ldr r3, [r7, #8] + 8003ab8: 691b ldr r3, [r3, #16] + 8003aba: 431a orrs r2, r3 + 8003abc: 68fb ldr r3, [r7, #12] + 8003abe: 681b ldr r3, [r3, #0] + 8003ac0: 430a orrs r2, r1 + 8003ac2: 609a str r2, [r3, #8] + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + 8003ac4: 68f8 ldr r0, [r7, #12] + 8003ac6: f000 f9ab bl 8003e20 <RTC_ExitInitMode> + 8003aca: 4603 mov r3, r0 + 8003acc: 74fb strb r3, [r7, #19] + } + + if (status == HAL_OK) + 8003ace: 7cfb ldrb r3, [r7, #19] + 8003ad0: 2b00 cmp r3, #0 + 8003ad2: d103 bne.n 8003adc <HAL_RTC_SetTime+0x124> + { + hrtc->State = HAL_RTC_STATE_READY; + 8003ad4: 68fb ldr r3, [r7, #12] + 8003ad6: 2201 movs r2, #1 + 8003ad8: f883 2021 strb.w r2, [r3, #33] @ 0x21 + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8003adc: 68fb ldr r3, [r7, #12] + 8003ade: 681b ldr r3, [r3, #0] + 8003ae0: 22ff movs r2, #255 @ 0xff + 8003ae2: 625a str r2, [r3, #36] @ 0x24 + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8003ae4: 68fb ldr r3, [r7, #12] + 8003ae6: 2200 movs r2, #0 + 8003ae8: f883 2020 strb.w r2, [r3, #32] + + return status; + 8003aec: 7cfb ldrb r3, [r7, #19] +} + 8003aee: 4618 mov r0, r3 + 8003af0: 371c adds r7, #28 + 8003af2: 46bd mov sp, r7 + 8003af4: bd90 pop {r4, r7, pc} + +08003af6 <HAL_RTC_GetTime>: + * until current date is read to ensure consistency between the time and + * date values. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + 8003af6: b580 push {r7, lr} + 8003af8: b086 sub sp, #24 + 8003afa: af00 add r7, sp, #0 + 8003afc: 60f8 str r0, [r7, #12] + 8003afe: 60b9 str r1, [r7, #8] + 8003b00: 607a str r2, [r7, #4] + uint32_t tmpreg = 0U; + 8003b02: 2300 movs r3, #0 + 8003b04: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get subseconds value from the corresponding register */ + sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR); + 8003b06: 68fb ldr r3, [r7, #12] + 8003b08: 681b ldr r3, [r3, #0] + 8003b0a: 6a9a ldr r2, [r3, #40] @ 0x28 + 8003b0c: 68bb ldr r3, [r7, #8] + 8003b0e: 605a str r2, [r3, #4] + + /* Get SecondFraction structure field from the corresponding register field*/ + sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S); + 8003b10: 68fb ldr r3, [r7, #12] + 8003b12: 681b ldr r3, [r3, #0] + 8003b14: 691b ldr r3, [r3, #16] + 8003b16: f3c3 020e ubfx r2, r3, #0, #15 + 8003b1a: 68bb ldr r3, [r7, #8] + 8003b1c: 609a str r2, [r3, #8] + + /* Get the TR register */ + tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); + 8003b1e: 68fb ldr r3, [r7, #12] + 8003b20: 681b ldr r3, [r3, #0] + 8003b22: 681b ldr r3, [r3, #0] + 8003b24: f003 337f and.w r3, r3, #2139062143 @ 0x7f7f7f7f + 8003b28: f023 43fe bic.w r3, r3, #2130706432 @ 0x7f000000 + 8003b2c: 617b str r3, [r7, #20] + + /* Fill the structure fields with the read parameters */ + sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos); + 8003b2e: 697b ldr r3, [r7, #20] + 8003b30: 0c1b lsrs r3, r3, #16 + 8003b32: b2db uxtb r3, r3 + 8003b34: f003 033f and.w r3, r3, #63 @ 0x3f + 8003b38: b2da uxtb r2, r3 + 8003b3a: 68bb ldr r3, [r7, #8] + 8003b3c: 701a strb r2, [r3, #0] + sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); + 8003b3e: 697b ldr r3, [r7, #20] + 8003b40: 0a1b lsrs r3, r3, #8 + 8003b42: b2db uxtb r3, r3 + 8003b44: f003 037f and.w r3, r3, #127 @ 0x7f + 8003b48: b2da uxtb r2, r3 + 8003b4a: 68bb ldr r3, [r7, #8] + 8003b4c: 705a strb r2, [r3, #1] + sTime->Seconds = (uint8_t)( tmpreg & (RTC_TR_ST | RTC_TR_SU)); + 8003b4e: 697b ldr r3, [r7, #20] + 8003b50: b2db uxtb r3, r3 + 8003b52: f003 037f and.w r3, r3, #127 @ 0x7f + 8003b56: b2da uxtb r2, r3 + 8003b58: 68bb ldr r3, [r7, #8] + 8003b5a: 709a strb r2, [r3, #2] + sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> RTC_TR_PM_Pos); + 8003b5c: 697b ldr r3, [r7, #20] + 8003b5e: 0d9b lsrs r3, r3, #22 + 8003b60: b2db uxtb r3, r3 + 8003b62: f003 0301 and.w r3, r3, #1 + 8003b66: b2da uxtb r2, r3 + 8003b68: 68bb ldr r3, [r7, #8] + 8003b6a: 70da strb r2, [r3, #3] + + /* Check the input parameters format */ + if (Format == RTC_FORMAT_BIN) + 8003b6c: 687b ldr r3, [r7, #4] + 8003b6e: 2b00 cmp r3, #0 + 8003b70: d11a bne.n 8003ba8 <HAL_RTC_GetTime+0xb2> + { + /* Convert the time structure parameters to Binary format */ + sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); + 8003b72: 68bb ldr r3, [r7, #8] + 8003b74: 781b ldrb r3, [r3, #0] + 8003b76: 4618 mov r0, r3 + 8003b78: f000 f996 bl 8003ea8 <RTC_Bcd2ToByte> + 8003b7c: 4603 mov r3, r0 + 8003b7e: 461a mov r2, r3 + 8003b80: 68bb ldr r3, [r7, #8] + 8003b82: 701a strb r2, [r3, #0] + sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes); + 8003b84: 68bb ldr r3, [r7, #8] + 8003b86: 785b ldrb r3, [r3, #1] + 8003b88: 4618 mov r0, r3 + 8003b8a: f000 f98d bl 8003ea8 <RTC_Bcd2ToByte> + 8003b8e: 4603 mov r3, r0 + 8003b90: 461a mov r2, r3 + 8003b92: 68bb ldr r3, [r7, #8] + 8003b94: 705a strb r2, [r3, #1] + sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); + 8003b96: 68bb ldr r3, [r7, #8] + 8003b98: 789b ldrb r3, [r3, #2] + 8003b9a: 4618 mov r0, r3 + 8003b9c: f000 f984 bl 8003ea8 <RTC_Bcd2ToByte> + 8003ba0: 4603 mov r3, r0 + 8003ba2: 461a mov r2, r3 + 8003ba4: 68bb ldr r3, [r7, #8] + 8003ba6: 709a strb r2, [r3, #2] + } + + return HAL_OK; + 8003ba8: 2300 movs r3, #0 +} + 8003baa: 4618 mov r0, r3 + 8003bac: 3718 adds r7, #24 + 8003bae: 46bd mov sp, r7 + 8003bb0: bd80 pop {r7, pc} + +08003bb2 <HAL_RTC_SetDate>: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + 8003bb2: b590 push {r4, r7, lr} + 8003bb4: b087 sub sp, #28 + 8003bb6: af00 add r7, sp, #0 + 8003bb8: 60f8 str r0, [r7, #12] + 8003bba: 60b9 str r1, [r7, #8] + 8003bbc: 607a str r2, [r7, #4] + uint32_t datetmpreg = 0U; + 8003bbe: 2300 movs r3, #0 + 8003bc0: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + 8003bc2: 68fb ldr r3, [r7, #12] + 8003bc4: f893 3020 ldrb.w r3, [r3, #32] + 8003bc8: 2b01 cmp r3, #1 + 8003bca: d101 bne.n 8003bd0 <HAL_RTC_SetDate+0x1e> + 8003bcc: 2302 movs r3, #2 + 8003bce: e075 b.n 8003cbc <HAL_RTC_SetDate+0x10a> + 8003bd0: 68fb ldr r3, [r7, #12] + 8003bd2: 2201 movs r2, #1 + 8003bd4: f883 2020 strb.w r2, [r3, #32] + + hrtc->State = HAL_RTC_STATE_BUSY; + 8003bd8: 68fb ldr r3, [r7, #12] + 8003bda: 2202 movs r2, #2 + 8003bdc: f883 2021 strb.w r2, [r3, #33] @ 0x21 + + if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) + 8003be0: 687b ldr r3, [r7, #4] + 8003be2: 2b00 cmp r3, #0 + 8003be4: d10e bne.n 8003c04 <HAL_RTC_SetDate+0x52> + 8003be6: 68bb ldr r3, [r7, #8] + 8003be8: 785b ldrb r3, [r3, #1] + 8003bea: f003 0310 and.w r3, r3, #16 + 8003bee: 2b00 cmp r3, #0 + 8003bf0: d008 beq.n 8003c04 <HAL_RTC_SetDate+0x52> + { + sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); + 8003bf2: 68bb ldr r3, [r7, #8] + 8003bf4: 785b ldrb r3, [r3, #1] + 8003bf6: f023 0310 bic.w r3, r3, #16 + 8003bfa: b2db uxtb r3, r3 + 8003bfc: 330a adds r3, #10 + 8003bfe: b2da uxtb r2, r3 + 8003c00: 68bb ldr r3, [r7, #8] + 8003c02: 705a strb r2, [r3, #1] + } + + assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); + + if (Format == RTC_FORMAT_BIN) + 8003c04: 687b ldr r3, [r7, #4] + 8003c06: 2b00 cmp r3, #0 + 8003c08: d11c bne.n 8003c44 <HAL_RTC_SetDate+0x92> + { + assert_param(IS_RTC_YEAR(sDate->Year)); + assert_param(IS_RTC_MONTH(sDate->Month)); + assert_param(IS_RTC_DATE(sDate->Date)); + + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ + 8003c0a: 68bb ldr r3, [r7, #8] + 8003c0c: 78db ldrb r3, [r3, #3] + 8003c0e: 4618 mov r0, r3 + 8003c10: f000 f92c bl 8003e6c <RTC_ByteToBcd2> + 8003c14: 4603 mov r3, r0 + 8003c16: 041c lsls r4, r3, #16 + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \ + 8003c18: 68bb ldr r3, [r7, #8] + 8003c1a: 785b ldrb r3, [r3, #1] + 8003c1c: 4618 mov r0, r3 + 8003c1e: f000 f925 bl 8003e6c <RTC_ByteToBcd2> + 8003c22: 4603 mov r3, r0 + 8003c24: 021b lsls r3, r3, #8 + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ + 8003c26: 431c orrs r4, r3 + ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ + 8003c28: 68bb ldr r3, [r7, #8] + 8003c2a: 789b ldrb r3, [r3, #2] + 8003c2c: 4618 mov r0, r3 + 8003c2e: f000 f91d bl 8003e6c <RTC_ByteToBcd2> + 8003c32: 4603 mov r3, r0 + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \ + 8003c34: ea44 0203 orr.w r2, r4, r3 + ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos)); + 8003c38: 68bb ldr r3, [r7, #8] + 8003c3a: 781b ldrb r3, [r3, #0] + 8003c3c: 035b lsls r3, r3, #13 + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ + 8003c3e: 4313 orrs r3, r2 + 8003c40: 617b str r3, [r7, #20] + 8003c42: e00e b.n 8003c62 <HAL_RTC_SetDate+0xb0> + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); + assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); + assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); + + datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ + 8003c44: 68bb ldr r3, [r7, #8] + 8003c46: 78db ldrb r3, [r3, #3] + 8003c48: 041a lsls r2, r3, #16 + (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \ + 8003c4a: 68bb ldr r3, [r7, #8] + 8003c4c: 785b ldrb r3, [r3, #1] + 8003c4e: 021b lsls r3, r3, #8 + datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ + 8003c50: 4313 orrs r3, r2 + ((uint32_t) sDate->Date) | \ + 8003c52: 68ba ldr r2, [r7, #8] + 8003c54: 7892 ldrb r2, [r2, #2] + (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \ + 8003c56: 431a orrs r2, r3 + (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos)); + 8003c58: 68bb ldr r3, [r7, #8] + 8003c5a: 781b ldrb r3, [r3, #0] + 8003c5c: 035b lsls r3, r3, #13 + datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ + 8003c5e: 4313 orrs r3, r2 + 8003c60: 617b str r3, [r7, #20] + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8003c62: 68fb ldr r3, [r7, #12] + 8003c64: 681b ldr r3, [r3, #0] + 8003c66: 22ca movs r2, #202 @ 0xca + 8003c68: 625a str r2, [r3, #36] @ 0x24 + 8003c6a: 68fb ldr r3, [r7, #12] + 8003c6c: 681b ldr r3, [r3, #0] + 8003c6e: 2253 movs r2, #83 @ 0x53 + 8003c70: 625a str r2, [r3, #36] @ 0x24 + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + 8003c72: 68f8 ldr r0, [r7, #12] + 8003c74: f000 f89c bl 8003db0 <RTC_EnterInitMode> + 8003c78: 4603 mov r3, r0 + 8003c7a: 74fb strb r3, [r7, #19] + + if (status == HAL_OK) + 8003c7c: 7cfb ldrb r3, [r7, #19] + 8003c7e: 2b00 cmp r3, #0 + 8003c80: d10c bne.n 8003c9c <HAL_RTC_SetDate+0xea> + { + /* Set the RTC_DR register */ + hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); + 8003c82: 68fb ldr r3, [r7, #12] + 8003c84: 681a ldr r2, [r3, #0] + 8003c86: 697b ldr r3, [r7, #20] + 8003c88: f023 437f bic.w r3, r3, #4278190080 @ 0xff000000 + 8003c8c: f023 03c0 bic.w r3, r3, #192 @ 0xc0 + 8003c90: 6053 str r3, [r2, #4] + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + 8003c92: 68f8 ldr r0, [r7, #12] + 8003c94: f000 f8c4 bl 8003e20 <RTC_ExitInitMode> + 8003c98: 4603 mov r3, r0 + 8003c9a: 74fb strb r3, [r7, #19] + } + + if (status == HAL_OK) + 8003c9c: 7cfb ldrb r3, [r7, #19] + 8003c9e: 2b00 cmp r3, #0 + 8003ca0: d103 bne.n 8003caa <HAL_RTC_SetDate+0xf8> + { + hrtc->State = HAL_RTC_STATE_READY; + 8003ca2: 68fb ldr r3, [r7, #12] + 8003ca4: 2201 movs r2, #1 + 8003ca6: f883 2021 strb.w r2, [r3, #33] @ 0x21 + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8003caa: 68fb ldr r3, [r7, #12] + 8003cac: 681b ldr r3, [r3, #0] + 8003cae: 22ff movs r2, #255 @ 0xff + 8003cb0: 625a str r2, [r3, #36] @ 0x24 + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8003cb2: 68fb ldr r3, [r7, #12] + 8003cb4: 2200 movs r2, #0 + 8003cb6: f883 2020 strb.w r2, [r3, #32] + + return status; + 8003cba: 7cfb ldrb r3, [r7, #19] +} + 8003cbc: 4618 mov r0, r3 + 8003cbe: 371c adds r7, #28 + 8003cc0: 46bd mov sp, r7 + 8003cc2: bd90 pop {r4, r7, pc} + +08003cc4 <HAL_RTC_GetDate>: + * until current date is read to ensure consistency between the time and + * date values. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + 8003cc4: b580 push {r7, lr} + 8003cc6: b086 sub sp, #24 + 8003cc8: af00 add r7, sp, #0 + 8003cca: 60f8 str r0, [r7, #12] + 8003ccc: 60b9 str r1, [r7, #8] + 8003cce: 607a str r2, [r7, #4] + uint32_t datetmpreg = 0U; + 8003cd0: 2300 movs r3, #0 + 8003cd2: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get the DR register */ + datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); + 8003cd4: 68fb ldr r3, [r7, #12] + 8003cd6: 681b ldr r3, [r3, #0] + 8003cd8: 685b ldr r3, [r3, #4] + 8003cda: f023 437f bic.w r3, r3, #4278190080 @ 0xff000000 + 8003cde: f023 03c0 bic.w r3, r3, #192 @ 0xc0 + 8003ce2: 617b str r3, [r7, #20] + + /* Fill the structure fields with the read parameters */ + sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos); + 8003ce4: 697b ldr r3, [r7, #20] + 8003ce6: 0c1b lsrs r3, r3, #16 + 8003ce8: b2da uxtb r2, r3 + 8003cea: 68bb ldr r3, [r7, #8] + 8003cec: 70da strb r2, [r3, #3] + sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos); + 8003cee: 697b ldr r3, [r7, #20] + 8003cf0: 0a1b lsrs r3, r3, #8 + 8003cf2: b2db uxtb r3, r3 + 8003cf4: f003 031f and.w r3, r3, #31 + 8003cf8: b2da uxtb r2, r3 + 8003cfa: 68bb ldr r3, [r7, #8] + 8003cfc: 705a strb r2, [r3, #1] + sDate->Date = (uint8_t) (datetmpreg & (RTC_DR_DT | RTC_DR_DU)); + 8003cfe: 697b ldr r3, [r7, #20] + 8003d00: b2db uxtb r3, r3 + 8003d02: f003 033f and.w r3, r3, #63 @ 0x3f + 8003d06: b2da uxtb r2, r3 + 8003d08: 68bb ldr r3, [r7, #8] + 8003d0a: 709a strb r2, [r3, #2] + sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> RTC_DR_WDU_Pos); + 8003d0c: 697b ldr r3, [r7, #20] + 8003d0e: 0b5b lsrs r3, r3, #13 + 8003d10: b2db uxtb r3, r3 + 8003d12: f003 0307 and.w r3, r3, #7 + 8003d16: b2da uxtb r2, r3 + 8003d18: 68bb ldr r3, [r7, #8] + 8003d1a: 701a strb r2, [r3, #0] + + /* Check the input parameters format */ + if (Format == RTC_FORMAT_BIN) + 8003d1c: 687b ldr r3, [r7, #4] + 8003d1e: 2b00 cmp r3, #0 + 8003d20: d11a bne.n 8003d58 <HAL_RTC_GetDate+0x94> + { + /* Convert the date structure parameters to Binary format */ + sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); + 8003d22: 68bb ldr r3, [r7, #8] + 8003d24: 78db ldrb r3, [r3, #3] + 8003d26: 4618 mov r0, r3 + 8003d28: f000 f8be bl 8003ea8 <RTC_Bcd2ToByte> + 8003d2c: 4603 mov r3, r0 + 8003d2e: 461a mov r2, r3 + 8003d30: 68bb ldr r3, [r7, #8] + 8003d32: 70da strb r2, [r3, #3] + sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); + 8003d34: 68bb ldr r3, [r7, #8] + 8003d36: 785b ldrb r3, [r3, #1] + 8003d38: 4618 mov r0, r3 + 8003d3a: f000 f8b5 bl 8003ea8 <RTC_Bcd2ToByte> + 8003d3e: 4603 mov r3, r0 + 8003d40: 461a mov r2, r3 + 8003d42: 68bb ldr r3, [r7, #8] + 8003d44: 705a strb r2, [r3, #1] + sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); + 8003d46: 68bb ldr r3, [r7, #8] + 8003d48: 789b ldrb r3, [r3, #2] + 8003d4a: 4618 mov r0, r3 + 8003d4c: f000 f8ac bl 8003ea8 <RTC_Bcd2ToByte> + 8003d50: 4603 mov r3, r0 + 8003d52: 461a mov r2, r3 + 8003d54: 68bb ldr r3, [r7, #8] + 8003d56: 709a strb r2, [r3, #2] + } + return HAL_OK; + 8003d58: 2300 movs r3, #0 +} + 8003d5a: 4618 mov r0, r3 + 8003d5c: 3718 adds r7, #24 + 8003d5e: 46bd mov sp, r7 + 8003d60: bd80 pop {r7, pc} + ... + +08003d64 <HAL_RTC_WaitForSynchro>: + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) +{ + 8003d64: b580 push {r7, lr} + 8003d66: b084 sub sp, #16 + 8003d68: af00 add r7, sp, #0 + 8003d6a: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 8003d6c: 2300 movs r3, #0 + 8003d6e: 60fb str r3, [r7, #12] + + /* Clear RSF flag, keep reserved bits at reset values (setting other flags has no effect) */ + hrtc->Instance->ISR = ((uint32_t)(RTC_RSF_MASK & RTC_ISR_RESERVED_MASK)); + 8003d70: 687b ldr r3, [r7, #4] + 8003d72: 681b ldr r3, [r3, #0] + 8003d74: 4a0d ldr r2, [pc, #52] @ (8003dac <HAL_RTC_WaitForSynchro+0x48>) + 8003d76: 60da str r2, [r3, #12] + + /* Get tick */ + tickstart = HAL_GetTick(); + 8003d78: f7fd fa78 bl 800126c <HAL_GetTick> + 8003d7c: 60f8 str r0, [r7, #12] + + /* Wait the registers to be synchronised */ + while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U) + 8003d7e: e009 b.n 8003d94 <HAL_RTC_WaitForSynchro+0x30> + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 8003d80: f7fd fa74 bl 800126c <HAL_GetTick> + 8003d84: 4602 mov r2, r0 + 8003d86: 68fb ldr r3, [r7, #12] + 8003d88: 1ad3 subs r3, r2, r3 + 8003d8a: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 8003d8e: d901 bls.n 8003d94 <HAL_RTC_WaitForSynchro+0x30> + { + return HAL_TIMEOUT; + 8003d90: 2303 movs r3, #3 + 8003d92: e007 b.n 8003da4 <HAL_RTC_WaitForSynchro+0x40> + while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U) + 8003d94: 687b ldr r3, [r7, #4] + 8003d96: 681b ldr r3, [r3, #0] + 8003d98: 68db ldr r3, [r3, #12] + 8003d9a: f003 0320 and.w r3, r3, #32 + 8003d9e: 2b00 cmp r3, #0 + 8003da0: d0ee beq.n 8003d80 <HAL_RTC_WaitForSynchro+0x1c> + } + } + + return HAL_OK; + 8003da2: 2300 movs r3, #0 +} + 8003da4: 4618 mov r0, r3 + 8003da6: 3710 adds r7, #16 + 8003da8: 46bd mov sp, r7 + 8003daa: bd80 pop {r7, pc} + 8003dac: 0001ff5f .word 0x0001ff5f + +08003db0 <RTC_EnterInitMode>: + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) +{ + 8003db0: b580 push {r7, lr} + 8003db2: b084 sub sp, #16 + 8003db4: af00 add r7, sp, #0 + 8003db6: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 8003db8: 2300 movs r3, #0 + 8003dba: 60bb str r3, [r7, #8] + HAL_StatusTypeDef status = HAL_OK; + 8003dbc: 2300 movs r3, #0 + 8003dbe: 73fb strb r3, [r7, #15] + + /* Check that Initialization mode is not already set */ + if (READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) + 8003dc0: 687b ldr r3, [r7, #4] + 8003dc2: 681b ldr r3, [r3, #0] + 8003dc4: 68db ldr r3, [r3, #12] + 8003dc6: f003 0340 and.w r3, r3, #64 @ 0x40 + 8003dca: 2b00 cmp r3, #0 + 8003dcc: d123 bne.n 8003e16 <RTC_EnterInitMode+0x66> + { + /* Set INIT bit to enter Initialization mode */ + SET_BIT(hrtc->Instance->ISR, RTC_ISR_INIT); + 8003dce: 687b ldr r3, [r7, #4] + 8003dd0: 681b ldr r3, [r3, #0] + 8003dd2: 68da ldr r2, [r3, #12] + 8003dd4: 687b ldr r3, [r7, #4] + 8003dd6: 681b ldr r3, [r3, #0] + 8003dd8: f042 0280 orr.w r2, r2, #128 @ 0x80 + 8003ddc: 60da str r2, [r3, #12] + + /* Get tick */ + tickstart = HAL_GetTick(); + 8003dde: f7fd fa45 bl 800126c <HAL_GetTick> + 8003de2: 60b8 str r0, [r7, #8] + + /* Wait till RTC is in INIT state and if timeout is reached exit */ + while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_ERROR)) + 8003de4: e00d b.n 8003e02 <RTC_EnterInitMode+0x52> + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 8003de6: f7fd fa41 bl 800126c <HAL_GetTick> + 8003dea: 4602 mov r2, r0 + 8003dec: 68bb ldr r3, [r7, #8] + 8003dee: 1ad3 subs r3, r2, r3 + 8003df0: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 8003df4: d905 bls.n 8003e02 <RTC_EnterInitMode+0x52> + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + 8003df6: 687b ldr r3, [r7, #4] + 8003df8: 2204 movs r2, #4 + 8003dfa: f883 2021 strb.w r2, [r3, #33] @ 0x21 + status = HAL_ERROR; + 8003dfe: 2301 movs r3, #1 + 8003e00: 73fb strb r3, [r7, #15] + while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_ERROR)) + 8003e02: 687b ldr r3, [r7, #4] + 8003e04: 681b ldr r3, [r3, #0] + 8003e06: 68db ldr r3, [r3, #12] + 8003e08: f003 0340 and.w r3, r3, #64 @ 0x40 + 8003e0c: 2b00 cmp r3, #0 + 8003e0e: d102 bne.n 8003e16 <RTC_EnterInitMode+0x66> + 8003e10: 7bfb ldrb r3, [r7, #15] + 8003e12: 2b01 cmp r3, #1 + 8003e14: d1e7 bne.n 8003de6 <RTC_EnterInitMode+0x36> + } + } + } + + return status; + 8003e16: 7bfb ldrb r3, [r7, #15] +} + 8003e18: 4618 mov r0, r3 + 8003e1a: 3710 adds r7, #16 + 8003e1c: 46bd mov sp, r7 + 8003e1e: bd80 pop {r7, pc} + +08003e20 <RTC_ExitInitMode>: + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) +{ + 8003e20: b580 push {r7, lr} + 8003e22: b084 sub sp, #16 + 8003e24: af00 add r7, sp, #0 + 8003e26: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8003e28: 2300 movs r3, #0 + 8003e2a: 73fb strb r3, [r7, #15] + + /* Clear INIT bit to exit Initialization mode */ + CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT); + 8003e2c: 687b ldr r3, [r7, #4] + 8003e2e: 681b ldr r3, [r3, #0] + 8003e30: 68da ldr r2, [r3, #12] + 8003e32: 687b ldr r3, [r7, #4] + 8003e34: 681b ldr r3, [r3, #0] + 8003e36: f022 0280 bic.w r2, r2, #128 @ 0x80 + 8003e3a: 60da str r2, [r3, #12] + + /* If CR_BYPSHAD bit = 0, wait for synchro */ + if (READ_BIT(hrtc->Instance->CR, RTC_CR_BYPSHAD) == 0U) + 8003e3c: 687b ldr r3, [r7, #4] + 8003e3e: 681b ldr r3, [r3, #0] + 8003e40: 689b ldr r3, [r3, #8] + 8003e42: f003 0320 and.w r3, r3, #32 + 8003e46: 2b00 cmp r3, #0 + 8003e48: d10b bne.n 8003e62 <RTC_ExitInitMode+0x42> + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + 8003e4a: 6878 ldr r0, [r7, #4] + 8003e4c: f7ff ff8a bl 8003d64 <HAL_RTC_WaitForSynchro> + 8003e50: 4603 mov r3, r0 + 8003e52: 2b00 cmp r3, #0 + 8003e54: d005 beq.n 8003e62 <RTC_ExitInitMode+0x42> + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + 8003e56: 687b ldr r3, [r7, #4] + 8003e58: 2204 movs r2, #4 + 8003e5a: f883 2021 strb.w r2, [r3, #33] @ 0x21 + status = HAL_ERROR; + 8003e5e: 2301 movs r3, #1 + 8003e60: 73fb strb r3, [r7, #15] + } + } + + return status; + 8003e62: 7bfb ldrb r3, [r7, #15] +} + 8003e64: 4618 mov r0, r3 + 8003e66: 3710 adds r7, #16 + 8003e68: 46bd mov sp, r7 + 8003e6a: bd80 pop {r7, pc} + +08003e6c <RTC_ByteToBcd2>: + * @brief Converts a 2-digit number from decimal to BCD format. + * @param number decimal-formatted number (from 0 to 99) to be converted + * @retval Converted byte + */ +uint8_t RTC_ByteToBcd2(uint8_t number) +{ + 8003e6c: b480 push {r7} + 8003e6e: b085 sub sp, #20 + 8003e70: af00 add r7, sp, #0 + 8003e72: 4603 mov r3, r0 + 8003e74: 71fb strb r3, [r7, #7] + uint32_t bcdhigh = 0U; + 8003e76: 2300 movs r3, #0 + 8003e78: 60fb str r3, [r7, #12] + + while (number >= 10U) + 8003e7a: e005 b.n 8003e88 <RTC_ByteToBcd2+0x1c> + { + bcdhigh++; + 8003e7c: 68fb ldr r3, [r7, #12] + 8003e7e: 3301 adds r3, #1 + 8003e80: 60fb str r3, [r7, #12] + number -= 10U; + 8003e82: 79fb ldrb r3, [r7, #7] + 8003e84: 3b0a subs r3, #10 + 8003e86: 71fb strb r3, [r7, #7] + while (number >= 10U) + 8003e88: 79fb ldrb r3, [r7, #7] + 8003e8a: 2b09 cmp r3, #9 + 8003e8c: d8f6 bhi.n 8003e7c <RTC_ByteToBcd2+0x10> + } + + return ((uint8_t)(bcdhigh << 4U) | number); + 8003e8e: 68fb ldr r3, [r7, #12] + 8003e90: b2db uxtb r3, r3 + 8003e92: 011b lsls r3, r3, #4 + 8003e94: b2da uxtb r2, r3 + 8003e96: 79fb ldrb r3, [r7, #7] + 8003e98: 4313 orrs r3, r2 + 8003e9a: b2db uxtb r3, r3 +} + 8003e9c: 4618 mov r0, r3 + 8003e9e: 3714 adds r7, #20 + 8003ea0: 46bd mov sp, r7 + 8003ea2: f85d 7b04 ldr.w r7, [sp], #4 + 8003ea6: 4770 bx lr + +08003ea8 <RTC_Bcd2ToByte>: + * @brief Converts a 2-digit number from BCD to decimal format. + * @param number BCD-formatted number (from 00 to 99) to be converted + * @retval Converted word + */ +uint8_t RTC_Bcd2ToByte(uint8_t number) +{ + 8003ea8: b480 push {r7} + 8003eaa: b085 sub sp, #20 + 8003eac: af00 add r7, sp, #0 + 8003eae: 4603 mov r3, r0 + 8003eb0: 71fb strb r3, [r7, #7] + uint32_t tens = 0U; + 8003eb2: 2300 movs r3, #0 + 8003eb4: 60fb str r3, [r7, #12] + tens = (((uint32_t)number & 0xF0U) >> 4U) * 10U; + 8003eb6: 79fb ldrb r3, [r7, #7] + 8003eb8: 091b lsrs r3, r3, #4 + 8003eba: b2db uxtb r3, r3 + 8003ebc: 461a mov r2, r3 + 8003ebe: 4613 mov r3, r2 + 8003ec0: 009b lsls r3, r3, #2 + 8003ec2: 4413 add r3, r2 + 8003ec4: 005b lsls r3, r3, #1 + 8003ec6: 60fb str r3, [r7, #12] + return (uint8_t)(tens + ((uint32_t)number & 0x0FU)); + 8003ec8: 68fb ldr r3, [r7, #12] + 8003eca: b2da uxtb r2, r3 + 8003ecc: 79fb ldrb r3, [r7, #7] + 8003ece: f003 030f and.w r3, r3, #15 + 8003ed2: b2db uxtb r3, r3 + 8003ed4: 4413 add r3, r2 + 8003ed6: b2db uxtb r3, r3 +} + 8003ed8: 4618 mov r0, r3 + 8003eda: 3714 adds r7, #20 + 8003edc: 46bd mov sp, r7 + 8003ede: f85d 7b04 ldr.w r7, [sp], #4 + 8003ee2: 4770 bx lr + +08003ee4 <HAL_RTCEx_SetWakeUpTimer_IT>: + * @param WakeUpCounter Wakeup counter + * @param WakeUpClock Wakeup clock + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) +{ + 8003ee4: b480 push {r7} + 8003ee6: b087 sub sp, #28 + 8003ee8: af00 add r7, sp, #0 + 8003eea: 60f8 str r0, [r7, #12] + 8003eec: 60b9 str r1, [r7, #8] + 8003eee: 607a str r2, [r7, #4] + __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); + 8003ef0: 4b5f ldr r3, [pc, #380] @ (8004070 <HAL_RTCEx_SetWakeUpTimer_IT+0x18c>) + 8003ef2: 681b ldr r3, [r3, #0] + 8003ef4: 4a5f ldr r2, [pc, #380] @ (8004074 <HAL_RTCEx_SetWakeUpTimer_IT+0x190>) + 8003ef6: fba2 2303 umull r2, r3, r2, r3 + 8003efa: 0adb lsrs r3, r3, #11 + 8003efc: f44f 727a mov.w r2, #1000 @ 0x3e8 + 8003f00: fb02 f303 mul.w r3, r2, r3 + 8003f04: 617b str r3, [r7, #20] + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + 8003f06: 68fb ldr r3, [r7, #12] + 8003f08: f893 3020 ldrb.w r3, [r3, #32] + 8003f0c: 2b01 cmp r3, #1 + 8003f0e: d101 bne.n 8003f14 <HAL_RTCEx_SetWakeUpTimer_IT+0x30> + 8003f10: 2302 movs r3, #2 + 8003f12: e0a7 b.n 8004064 <HAL_RTCEx_SetWakeUpTimer_IT+0x180> + 8003f14: 68fb ldr r3, [r7, #12] + 8003f16: 2201 movs r2, #1 + 8003f18: f883 2020 strb.w r2, [r3, #32] + + hrtc->State = HAL_RTC_STATE_BUSY; + 8003f1c: 68fb ldr r3, [r7, #12] + 8003f1e: 2202 movs r2, #2 + 8003f20: f883 2021 strb.w r2, [r3, #33] @ 0x21 + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8003f24: 68fb ldr r3, [r7, #12] + 8003f26: 681b ldr r3, [r3, #0] + 8003f28: 22ca movs r2, #202 @ 0xca + 8003f2a: 625a str r2, [r3, #36] @ 0x24 + 8003f2c: 68fb ldr r3, [r7, #12] + 8003f2e: 681b ldr r3, [r3, #0] + 8003f30: 2253 movs r2, #83 @ 0x53 + 8003f32: 625a str r2, [r3, #36] @ 0x24 + + /* Check RTC WUTWF flag is reset only when wakeup timer enabled */ + if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U) + 8003f34: 68fb ldr r3, [r7, #12] + 8003f36: 681b ldr r3, [r3, #0] + 8003f38: 689b ldr r3, [r3, #8] + 8003f3a: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8003f3e: 2b00 cmp r3, #0 + 8003f40: d01a beq.n 8003f78 <HAL_RTCEx_SetWakeUpTimer_IT+0x94> + { + /* Wait till RTC WUTWF flag is reset and if timeout is reached exit */ + do + { + count = count - 1U; + 8003f42: 697b ldr r3, [r7, #20] + 8003f44: 3b01 subs r3, #1 + 8003f46: 617b str r3, [r7, #20] + if (count == 0U) + 8003f48: 697b ldr r3, [r7, #20] + 8003f4a: 2b00 cmp r3, #0 + 8003f4c: d10d bne.n 8003f6a <HAL_RTCEx_SetWakeUpTimer_IT+0x86> + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8003f4e: 68fb ldr r3, [r7, #12] + 8003f50: 681b ldr r3, [r3, #0] + 8003f52: 22ff movs r2, #255 @ 0xff + 8003f54: 625a str r2, [r3, #36] @ 0x24 + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + 8003f56: 68fb ldr r3, [r7, #12] + 8003f58: 2203 movs r2, #3 + 8003f5a: f883 2021 strb.w r2, [r3, #33] @ 0x21 + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8003f5e: 68fb ldr r3, [r7, #12] + 8003f60: 2200 movs r2, #0 + 8003f62: f883 2020 strb.w r2, [r3, #32] + + return HAL_TIMEOUT; + 8003f66: 2303 movs r3, #3 + 8003f68: e07c b.n 8004064 <HAL_RTCEx_SetWakeUpTimer_IT+0x180> + } + } while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) != 0U); + 8003f6a: 68fb ldr r3, [r7, #12] + 8003f6c: 681b ldr r3, [r3, #0] + 8003f6e: 68db ldr r3, [r3, #12] + 8003f70: f003 0304 and.w r3, r3, #4 + 8003f74: 2b00 cmp r3, #0 + 8003f76: d1e4 bne.n 8003f42 <HAL_RTCEx_SetWakeUpTimer_IT+0x5e> + } + + /* Disable the Wakeup timer */ + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + 8003f78: 68fb ldr r3, [r7, #12] + 8003f7a: 681b ldr r3, [r3, #0] + 8003f7c: 689a ldr r2, [r3, #8] + 8003f7e: 68fb ldr r3, [r7, #12] + 8003f80: 681b ldr r3, [r3, #0] + 8003f82: f422 6280 bic.w r2, r2, #1024 @ 0x400 + 8003f86: 609a str r2, [r3, #8] + + /* Clear the Wakeup flag */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + 8003f88: 68fb ldr r3, [r7, #12] + 8003f8a: 681b ldr r3, [r3, #0] + 8003f8c: 68db ldr r3, [r3, #12] + 8003f8e: b2da uxtb r2, r3 + 8003f90: 68fb ldr r3, [r7, #12] + 8003f92: 681b ldr r3, [r3, #0] + 8003f94: f462 6290 orn r2, r2, #1152 @ 0x480 + 8003f98: 60da str r2, [r3, #12] + + /* Reload the counter */ + count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); + 8003f9a: 4b35 ldr r3, [pc, #212] @ (8004070 <HAL_RTCEx_SetWakeUpTimer_IT+0x18c>) + 8003f9c: 681b ldr r3, [r3, #0] + 8003f9e: 4a35 ldr r2, [pc, #212] @ (8004074 <HAL_RTCEx_SetWakeUpTimer_IT+0x190>) + 8003fa0: fba2 2303 umull r2, r3, r2, r3 + 8003fa4: 0adb lsrs r3, r3, #11 + 8003fa6: f44f 727a mov.w r2, #1000 @ 0x3e8 + 8003faa: fb02 f303 mul.w r3, r2, r3 + 8003fae: 617b str r3, [r7, #20] + + /* Wait till RTC WUTWF flag is set and if timeout is reached exit */ + do + { + count = count - 1U; + 8003fb0: 697b ldr r3, [r7, #20] + 8003fb2: 3b01 subs r3, #1 + 8003fb4: 617b str r3, [r7, #20] + if (count == 0U) + 8003fb6: 697b ldr r3, [r7, #20] + 8003fb8: 2b00 cmp r3, #0 + 8003fba: d10d bne.n 8003fd8 <HAL_RTCEx_SetWakeUpTimer_IT+0xf4> + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8003fbc: 68fb ldr r3, [r7, #12] + 8003fbe: 681b ldr r3, [r3, #0] + 8003fc0: 22ff movs r2, #255 @ 0xff + 8003fc2: 625a str r2, [r3, #36] @ 0x24 + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + 8003fc4: 68fb ldr r3, [r7, #12] + 8003fc6: 2203 movs r2, #3 + 8003fc8: f883 2021 strb.w r2, [r3, #33] @ 0x21 + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8003fcc: 68fb ldr r3, [r7, #12] + 8003fce: 2200 movs r2, #0 + 8003fd0: f883 2020 strb.w r2, [r3, #32] + + return HAL_TIMEOUT; + 8003fd4: 2303 movs r3, #3 + 8003fd6: e045 b.n 8004064 <HAL_RTCEx_SetWakeUpTimer_IT+0x180> + } + } while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U); + 8003fd8: 68fb ldr r3, [r7, #12] + 8003fda: 681b ldr r3, [r3, #0] + 8003fdc: 68db ldr r3, [r3, #12] + 8003fde: f003 0304 and.w r3, r3, #4 + 8003fe2: 2b00 cmp r3, #0 + 8003fe4: d0e4 beq.n 8003fb0 <HAL_RTCEx_SetWakeUpTimer_IT+0xcc> + + /* Clear the Wakeup Timer clock source bits in CR register */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; + 8003fe6: 68fb ldr r3, [r7, #12] + 8003fe8: 681b ldr r3, [r3, #0] + 8003fea: 689a ldr r2, [r3, #8] + 8003fec: 68fb ldr r3, [r7, #12] + 8003fee: 681b ldr r3, [r3, #0] + 8003ff0: f022 0207 bic.w r2, r2, #7 + 8003ff4: 609a str r2, [r3, #8] + + /* Configure the clock source */ + hrtc->Instance->CR |= (uint32_t)WakeUpClock; + 8003ff6: 68fb ldr r3, [r7, #12] + 8003ff8: 681b ldr r3, [r3, #0] + 8003ffa: 6899 ldr r1, [r3, #8] + 8003ffc: 68fb ldr r3, [r7, #12] + 8003ffe: 681b ldr r3, [r3, #0] + 8004000: 687a ldr r2, [r7, #4] + 8004002: 430a orrs r2, r1 + 8004004: 609a str r2, [r3, #8] + + /* Configure the Wakeup Timer counter */ + hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; + 8004006: 68fb ldr r3, [r7, #12] + 8004008: 681b ldr r3, [r3, #0] + 800400a: 68ba ldr r2, [r7, #8] + 800400c: 615a str r2, [r3, #20] + + /* Enable and configure the EXTI line associated to the RTC Wakeup Timer interrupt */ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); + 800400e: 4b1a ldr r3, [pc, #104] @ (8004078 <HAL_RTCEx_SetWakeUpTimer_IT+0x194>) + 8004010: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 8004014: 4a18 ldr r2, [pc, #96] @ (8004078 <HAL_RTCEx_SetWakeUpTimer_IT+0x194>) + 8004016: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 800401a: f8c2 3080 str.w r3, [r2, #128] @ 0x80 + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); + 800401e: 4b16 ldr r3, [pc, #88] @ (8004078 <HAL_RTCEx_SetWakeUpTimer_IT+0x194>) + 8004020: 681b ldr r3, [r3, #0] + 8004022: 4a15 ldr r2, [pc, #84] @ (8004078 <HAL_RTCEx_SetWakeUpTimer_IT+0x194>) + 8004024: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 8004028: 6013 str r3, [r2, #0] + + /* Configure the interrupt in the RTC_CR register */ + __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc, RTC_IT_WUT); + 800402a: 68fb ldr r3, [r7, #12] + 800402c: 681b ldr r3, [r3, #0] + 800402e: 689a ldr r2, [r3, #8] + 8004030: 68fb ldr r3, [r7, #12] + 8004032: 681b ldr r3, [r3, #0] + 8004034: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 8004038: 609a str r2, [r3, #8] + + /* Enable the Wakeup Timer */ + __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); + 800403a: 68fb ldr r3, [r7, #12] + 800403c: 681b ldr r3, [r3, #0] + 800403e: 689a ldr r2, [r3, #8] + 8004040: 68fb ldr r3, [r7, #12] + 8004042: 681b ldr r3, [r3, #0] + 8004044: f442 6280 orr.w r2, r2, #1024 @ 0x400 + 8004048: 609a str r2, [r3, #8] + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 800404a: 68fb ldr r3, [r7, #12] + 800404c: 681b ldr r3, [r3, #0] + 800404e: 22ff movs r2, #255 @ 0xff + 8004050: 625a str r2, [r3, #36] @ 0x24 + + hrtc->State = HAL_RTC_STATE_READY; + 8004052: 68fb ldr r3, [r7, #12] + 8004054: 2201 movs r2, #1 + 8004056: f883 2021 strb.w r2, [r3, #33] @ 0x21 + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 800405a: 68fb ldr r3, [r7, #12] + 800405c: 2200 movs r2, #0 + 800405e: f883 2020 strb.w r2, [r3, #32] + + return HAL_OK; + 8004062: 2300 movs r3, #0 +} + 8004064: 4618 mov r0, r3 + 8004066: 371c adds r7, #28 + 8004068: 46bd mov sp, r7 + 800406a: f85d 7b04 ldr.w r7, [sp], #4 + 800406e: 4770 bx lr + 8004070: 200006c8 .word 0x200006c8 + 8004074: 10624dd3 .word 0x10624dd3 + 8004078: 58000800 .word 0x58000800 + +0800407c <HAL_RTCEx_DeactivateWakeUpTimer>: + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) +{ + 800407c: b580 push {r7, lr} + 800407e: b084 sub sp, #16 + 8004080: af00 add r7, sp, #0 + 8004082: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 8004084: 2300 movs r3, #0 + 8004086: 60fb str r3, [r7, #12] + + /* Process Locked */ + __HAL_LOCK(hrtc); + 8004088: 687b ldr r3, [r7, #4] + 800408a: f893 3020 ldrb.w r3, [r3, #32] + 800408e: 2b01 cmp r3, #1 + 8004090: d101 bne.n 8004096 <HAL_RTCEx_DeactivateWakeUpTimer+0x1a> + 8004092: 2302 movs r3, #2 + 8004094: e04d b.n 8004132 <HAL_RTCEx_DeactivateWakeUpTimer+0xb6> + 8004096: 687b ldr r3, [r7, #4] + 8004098: 2201 movs r2, #1 + 800409a: f883 2020 strb.w r2, [r3, #32] + + hrtc->State = HAL_RTC_STATE_BUSY; + 800409e: 687b ldr r3, [r7, #4] + 80040a0: 2202 movs r2, #2 + 80040a2: f883 2021 strb.w r2, [r3, #33] @ 0x21 + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 80040a6: 687b ldr r3, [r7, #4] + 80040a8: 681b ldr r3, [r3, #0] + 80040aa: 22ca movs r2, #202 @ 0xca + 80040ac: 625a str r2, [r3, #36] @ 0x24 + 80040ae: 687b ldr r3, [r7, #4] + 80040b0: 681b ldr r3, [r3, #0] + 80040b2: 2253 movs r2, #83 @ 0x53 + 80040b4: 625a str r2, [r3, #36] @ 0x24 + + /* Disable the Wakeup Timer */ + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + 80040b6: 687b ldr r3, [r7, #4] + 80040b8: 681b ldr r3, [r3, #0] + 80040ba: 689a ldr r2, [r3, #8] + 80040bc: 687b ldr r3, [r7, #4] + 80040be: 681b ldr r3, [r3, #0] + 80040c0: f422 6280 bic.w r2, r2, #1024 @ 0x400 + 80040c4: 609a str r2, [r3, #8] + + /* In case interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc, RTC_IT_WUT); + 80040c6: 687b ldr r3, [r7, #4] + 80040c8: 681b ldr r3, [r3, #0] + 80040ca: 689a ldr r2, [r3, #8] + 80040cc: 687b ldr r3, [r7, #4] + 80040ce: 681b ldr r3, [r3, #0] + 80040d0: f422 4280 bic.w r2, r2, #16384 @ 0x4000 + 80040d4: 609a str r2, [r3, #8] + + /* Get tick */ + tickstart = HAL_GetTick(); + 80040d6: f7fd f8c9 bl 800126c <HAL_GetTick> + 80040da: 60f8 str r0, [r7, #12] + + /* Wait till RTC WUTWF flag is set and if timeout is reached exit */ + while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) + 80040dc: e015 b.n 800410a <HAL_RTCEx_DeactivateWakeUpTimer+0x8e> + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 80040de: f7fd f8c5 bl 800126c <HAL_GetTick> + 80040e2: 4602 mov r2, r0 + 80040e4: 68fb ldr r3, [r7, #12] + 80040e6: 1ad3 subs r3, r2, r3 + 80040e8: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 80040ec: d90d bls.n 800410a <HAL_RTCEx_DeactivateWakeUpTimer+0x8e> + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 80040ee: 687b ldr r3, [r7, #4] + 80040f0: 681b ldr r3, [r3, #0] + 80040f2: 22ff movs r2, #255 @ 0xff + 80040f4: 625a str r2, [r3, #36] @ 0x24 + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + 80040f6: 687b ldr r3, [r7, #4] + 80040f8: 2203 movs r2, #3 + 80040fa: f883 2021 strb.w r2, [r3, #33] @ 0x21 + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 80040fe: 687b ldr r3, [r7, #4] + 8004100: 2200 movs r2, #0 + 8004102: f883 2020 strb.w r2, [r3, #32] + + return HAL_TIMEOUT; + 8004106: 2303 movs r3, #3 + 8004108: e013 b.n 8004132 <HAL_RTCEx_DeactivateWakeUpTimer+0xb6> + while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) + 800410a: 687b ldr r3, [r7, #4] + 800410c: 681b ldr r3, [r3, #0] + 800410e: 68db ldr r3, [r3, #12] + 8004110: f003 0304 and.w r3, r3, #4 + 8004114: 2b00 cmp r3, #0 + 8004116: d0e2 beq.n 80040de <HAL_RTCEx_DeactivateWakeUpTimer+0x62> + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8004118: 687b ldr r3, [r7, #4] + 800411a: 681b ldr r3, [r3, #0] + 800411c: 22ff movs r2, #255 @ 0xff + 800411e: 625a str r2, [r3, #36] @ 0x24 + + hrtc->State = HAL_RTC_STATE_READY; + 8004120: 687b ldr r3, [r7, #4] + 8004122: 2201 movs r2, #1 + 8004124: f883 2021 strb.w r2, [r3, #33] @ 0x21 + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8004128: 687b ldr r3, [r7, #4] + 800412a: 2200 movs r2, #0 + 800412c: f883 2020 strb.w r2, [r3, #32] + + return HAL_OK; + 8004130: 2300 movs r3, #0 +} + 8004132: 4618 mov r0, r3 + 8004134: 3710 adds r7, #16 + 8004136: 46bd mov sp, r7 + 8004138: bd80 pop {r7, pc} + ... + +0800413c <HAL_RTCEx_WakeUpTimerIRQHandler>: + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) +{ + 800413c: b580 push {r7, lr} + 800413e: b082 sub sp, #8 + 8004140: af00 add r7, sp, #0 + 8004142: 6078 str r0, [r7, #4] + /* Clear the EXTI flag associated to the RTC Wakeup Timer interrupt */ + __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); + 8004144: 4b0f ldr r3, [pc, #60] @ (8004184 <HAL_RTCEx_WakeUpTimerIRQHandler+0x48>) + 8004146: f44f 2200 mov.w r2, #524288 @ 0x80000 + 800414a: 60da str r2, [r3, #12] + + /* Get the pending status of the Wakeup timer Interrupt */ + if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U) + 800414c: 687b ldr r3, [r7, #4] + 800414e: 681b ldr r3, [r3, #0] + 8004150: 68db ldr r3, [r3, #12] + 8004152: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8004156: 2b00 cmp r3, #0 + 8004158: d00b beq.n 8004172 <HAL_RTCEx_WakeUpTimerIRQHandler+0x36> + { + /* Clear the Wakeup timer interrupt pending bit */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + 800415a: 687b ldr r3, [r7, #4] + 800415c: 681b ldr r3, [r3, #0] + 800415e: 68db ldr r3, [r3, #12] + 8004160: b2da uxtb r2, r3 + 8004162: 687b ldr r3, [r7, #4] + 8004164: 681b ldr r3, [r3, #0] + 8004166: f462 6290 orn r2, r2, #1152 @ 0x480 + 800416a: 60da str r2, [r3, #12] + + /* Wakeup timer callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->WakeUpTimerEventCallback(hrtc); +#else + HAL_RTCEx_WakeUpTimerEventCallback(hrtc); + 800416c: 6878 ldr r0, [r7, #4] + 800416e: f000 f80b bl 8004188 <HAL_RTCEx_WakeUpTimerEventCallback> +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + 8004172: 687b ldr r3, [r7, #4] + 8004174: 2201 movs r2, #1 + 8004176: f883 2021 strb.w r2, [r3, #33] @ 0x21 +} + 800417a: bf00 nop + 800417c: 3708 adds r7, #8 + 800417e: 46bd mov sp, r7 + 8004180: bd80 pop {r7, pc} + 8004182: bf00 nop + 8004184: 58000800 .word 0x58000800 + +08004188 <HAL_RTCEx_WakeUpTimerEventCallback>: + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) +{ + 8004188: b480 push {r7} + 800418a: b083 sub sp, #12 + 800418c: af00 add r7, sp, #0 + 800418e: 6078 str r0, [r7, #4] + UNUSED(hrtc); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file + */ +} + 8004190: bf00 nop + 8004192: 370c adds r7, #12 + 8004194: 46bd mov sp, r7 + 8004196: f85d 7b04 ldr.w r7, [sp], #4 + 800419a: 4770 bx lr + +0800419c <HAL_SPI_Init>: + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + 800419c: b580 push {r7, lr} + 800419e: b084 sub sp, #16 + 80041a0: af00 add r7, sp, #0 + 80041a2: 6078 str r0, [r7, #4] + uint32_t frxth; + + /* Check the SPI handle allocation */ + if (hspi == NULL) + 80041a4: 687b ldr r3, [r7, #4] + 80041a6: 2b00 cmp r3, #0 + 80041a8: d101 bne.n 80041ae <HAL_SPI_Init+0x12> + { + return HAL_ERROR; + 80041aa: 2301 movs r3, #1 + 80041ac: e095 b.n 80042da <HAL_SPI_Init+0x13e> + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + 80041ae: 687b ldr r3, [r7, #4] + 80041b0: 6a5b ldr r3, [r3, #36] @ 0x24 + 80041b2: 2b00 cmp r3, #0 + 80041b4: d108 bne.n 80041c8 <HAL_SPI_Init+0x2c> + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + 80041b6: 687b ldr r3, [r7, #4] + 80041b8: 685b ldr r3, [r3, #4] + 80041ba: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 80041be: d009 beq.n 80041d4 <HAL_SPI_Init+0x38> + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 80041c0: 687b ldr r3, [r7, #4] + 80041c2: 2200 movs r2, #0 + 80041c4: 61da str r2, [r3, #28] + 80041c6: e005 b.n 80041d4 <HAL_SPI_Init+0x38> + else + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + 80041c8: 687b ldr r3, [r7, #4] + 80041ca: 2200 movs r2, #0 + 80041cc: 611a str r2, [r3, #16] + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; + 80041ce: 687b ldr r3, [r7, #4] + 80041d0: 2200 movs r2, #0 + 80041d2: 615a str r2, [r3, #20] + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 80041d4: 687b ldr r3, [r7, #4] + 80041d6: 2200 movs r2, #0 + 80041d8: 629a str r2, [r3, #40] @ 0x28 +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + 80041da: 687b ldr r3, [r7, #4] + 80041dc: f893 305d ldrb.w r3, [r3, #93] @ 0x5d + 80041e0: b2db uxtb r3, r3 + 80041e2: 2b00 cmp r3, #0 + 80041e4: d106 bne.n 80041f4 <HAL_SPI_Init+0x58> + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + 80041e6: 687b ldr r3, [r7, #4] + 80041e8: 2200 movs r2, #0 + 80041ea: f883 205c strb.w r2, [r3, #92] @ 0x5c + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + 80041ee: 6878 ldr r0, [r7, #4] + 80041f0: f7fc fe88 bl 8000f04 <HAL_SPI_MspInit> +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + 80041f4: 687b ldr r3, [r7, #4] + 80041f6: 2202 movs r2, #2 + 80041f8: f883 205d strb.w r2, [r3, #93] @ 0x5d + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 80041fc: 687b ldr r3, [r7, #4] + 80041fe: 681b ldr r3, [r3, #0] + 8004200: 681a ldr r2, [r3, #0] + 8004202: 687b ldr r3, [r7, #4] + 8004204: 681b ldr r3, [r3, #0] + 8004206: f022 0240 bic.w r2, r2, #64 @ 0x40 + 800420a: 601a str r2, [r3, #0] + + /* Align by default the rs fifo threshold on the data size */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 800420c: 687b ldr r3, [r7, #4] + 800420e: 68db ldr r3, [r3, #12] + 8004210: f5b3 6fe0 cmp.w r3, #1792 @ 0x700 + 8004214: d902 bls.n 800421c <HAL_SPI_Init+0x80> + { + frxth = SPI_RXFIFO_THRESHOLD_HF; + 8004216: 2300 movs r3, #0 + 8004218: 60fb str r3, [r7, #12] + 800421a: e002 b.n 8004222 <HAL_SPI_Init+0x86> + } + else + { + frxth = SPI_RXFIFO_THRESHOLD_QF; + 800421c: f44f 5380 mov.w r3, #4096 @ 0x1000 + 8004220: 60fb str r3, [r7, #12] + } + + /* CRC calculation is valid only for 16Bit and 8 Bit */ + if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) + 8004222: 687b ldr r3, [r7, #4] + 8004224: 68db ldr r3, [r3, #12] + 8004226: f5b3 6f70 cmp.w r3, #3840 @ 0xf00 + 800422a: d007 beq.n 800423c <HAL_SPI_Init+0xa0> + 800422c: 687b ldr r3, [r7, #4] + 800422e: 68db ldr r3, [r3, #12] + 8004230: f5b3 6fe0 cmp.w r3, #1792 @ 0x700 + 8004234: d002 beq.n 800423c <HAL_SPI_Init+0xa0> + { + /* CRC must be disabled */ + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8004236: 687b ldr r3, [r7, #4] + 8004238: 2200 movs r2, #0 + 800423a: 629a str r2, [r3, #40] @ 0x28 + } + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + 800423c: 687b ldr r3, [r7, #4] + 800423e: 685b ldr r3, [r3, #4] + 8004240: f403 7282 and.w r2, r3, #260 @ 0x104 + 8004244: 687b ldr r3, [r7, #4] + 8004246: 689b ldr r3, [r3, #8] + 8004248: f403 4304 and.w r3, r3, #33792 @ 0x8400 + 800424c: 431a orrs r2, r3 + 800424e: 687b ldr r3, [r7, #4] + 8004250: 691b ldr r3, [r3, #16] + 8004252: f003 0302 and.w r3, r3, #2 + 8004256: 431a orrs r2, r3 + 8004258: 687b ldr r3, [r7, #4] + 800425a: 695b ldr r3, [r3, #20] + 800425c: f003 0301 and.w r3, r3, #1 + 8004260: 431a orrs r2, r3 + 8004262: 687b ldr r3, [r7, #4] + 8004264: 699b ldr r3, [r3, #24] + 8004266: f403 7300 and.w r3, r3, #512 @ 0x200 + 800426a: 431a orrs r2, r3 + 800426c: 687b ldr r3, [r7, #4] + 800426e: 69db ldr r3, [r3, #28] + 8004270: f003 0338 and.w r3, r3, #56 @ 0x38 + 8004274: 431a orrs r2, r3 + 8004276: 687b ldr r3, [r7, #4] + 8004278: 6a1b ldr r3, [r3, #32] + 800427a: f003 0380 and.w r3, r3, #128 @ 0x80 + 800427e: ea42 0103 orr.w r1, r2, r3 + 8004282: 687b ldr r3, [r7, #4] + 8004284: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004286: f403 5200 and.w r2, r3, #8192 @ 0x2000 + 800428a: 687b ldr r3, [r7, #4] + 800428c: 681b ldr r3, [r3, #0] + 800428e: 430a orrs r2, r1 + 8004290: 601a str r2, [r3, #0] + } + } +#endif /* USE_SPI_CRC */ + + /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | + 8004292: 687b ldr r3, [r7, #4] + 8004294: 699b ldr r3, [r3, #24] + 8004296: 0c1b lsrs r3, r3, #16 + 8004298: f003 0204 and.w r2, r3, #4 + 800429c: 687b ldr r3, [r7, #4] + 800429e: 6a5b ldr r3, [r3, #36] @ 0x24 + 80042a0: f003 0310 and.w r3, r3, #16 + 80042a4: 431a orrs r2, r3 + 80042a6: 687b ldr r3, [r7, #4] + 80042a8: 6b5b ldr r3, [r3, #52] @ 0x34 + 80042aa: f003 0308 and.w r3, r3, #8 + 80042ae: 431a orrs r2, r3 + 80042b0: 687b ldr r3, [r7, #4] + 80042b2: 68db ldr r3, [r3, #12] + 80042b4: f403 6370 and.w r3, r3, #3840 @ 0xf00 + 80042b8: ea42 0103 orr.w r1, r2, r3 + 80042bc: 68fb ldr r3, [r7, #12] + 80042be: f403 5280 and.w r2, r3, #4096 @ 0x1000 + 80042c2: 687b ldr r3, [r7, #4] + 80042c4: 681b ldr r3, [r3, #0] + 80042c6: 430a orrs r2, r1 + 80042c8: 605a str r2, [r3, #4] +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 80042ca: 687b ldr r3, [r7, #4] + 80042cc: 2200 movs r2, #0 + 80042ce: 661a str r2, [r3, #96] @ 0x60 + hspi->State = HAL_SPI_STATE_READY; + 80042d0: 687b ldr r3, [r7, #4] + 80042d2: 2201 movs r2, #1 + 80042d4: f883 205d strb.w r2, [r3, #93] @ 0x5d + + return HAL_OK; + 80042d8: 2300 movs r3, #0 +} + 80042da: 4618 mov r0, r3 + 80042dc: 3710 adds r7, #16 + 80042de: 46bd mov sp, r7 + 80042e0: bd80 pop {r7, pc} + +080042e2 <HAL_SPI_Transmit>: + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 80042e2: b580 push {r7, lr} + 80042e4: b088 sub sp, #32 + 80042e6: af00 add r7, sp, #0 + 80042e8: 60f8 str r0, [r7, #12] + 80042ea: 60b9 str r1, [r7, #8] + 80042ec: 603b str r3, [r7, #0] + 80042ee: 4613 mov r3, r2 + 80042f0: 80fb strh r3, [r7, #6] + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 80042f2: f7fc ffbb bl 800126c <HAL_GetTick> + 80042f6: 61f8 str r0, [r7, #28] + initial_TxXferCount = Size; + 80042f8: 88fb ldrh r3, [r7, #6] + 80042fa: 837b strh r3, [r7, #26] + + if (hspi->State != HAL_SPI_STATE_READY) + 80042fc: 68fb ldr r3, [r7, #12] + 80042fe: f893 305d ldrb.w r3, [r3, #93] @ 0x5d + 8004302: b2db uxtb r3, r3 + 8004304: 2b01 cmp r3, #1 + 8004306: d001 beq.n 800430c <HAL_SPI_Transmit+0x2a> + { + return HAL_BUSY; + 8004308: 2302 movs r3, #2 + 800430a: e15c b.n 80045c6 <HAL_SPI_Transmit+0x2e4> + } + + if ((pData == NULL) || (Size == 0U)) + 800430c: 68bb ldr r3, [r7, #8] + 800430e: 2b00 cmp r3, #0 + 8004310: d002 beq.n 8004318 <HAL_SPI_Transmit+0x36> + 8004312: 88fb ldrh r3, [r7, #6] + 8004314: 2b00 cmp r3, #0 + 8004316: d101 bne.n 800431c <HAL_SPI_Transmit+0x3a> + { + return HAL_ERROR; + 8004318: 2301 movs r3, #1 + 800431a: e154 b.n 80045c6 <HAL_SPI_Transmit+0x2e4> + } + + /* Process Locked */ + __HAL_LOCK(hspi); + 800431c: 68fb ldr r3, [r7, #12] + 800431e: f893 305c ldrb.w r3, [r3, #92] @ 0x5c + 8004322: 2b01 cmp r3, #1 + 8004324: d101 bne.n 800432a <HAL_SPI_Transmit+0x48> + 8004326: 2302 movs r3, #2 + 8004328: e14d b.n 80045c6 <HAL_SPI_Transmit+0x2e4> + 800432a: 68fb ldr r3, [r7, #12] + 800432c: 2201 movs r2, #1 + 800432e: f883 205c strb.w r2, [r3, #92] @ 0x5c + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + 8004332: 68fb ldr r3, [r7, #12] + 8004334: 2203 movs r2, #3 + 8004336: f883 205d strb.w r2, [r3, #93] @ 0x5d + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 800433a: 68fb ldr r3, [r7, #12] + 800433c: 2200 movs r2, #0 + 800433e: 661a str r2, [r3, #96] @ 0x60 + hspi->pTxBuffPtr = (const uint8_t *)pData; + 8004340: 68fb ldr r3, [r7, #12] + 8004342: 68ba ldr r2, [r7, #8] + 8004344: 639a str r2, [r3, #56] @ 0x38 + hspi->TxXferSize = Size; + 8004346: 68fb ldr r3, [r7, #12] + 8004348: 88fa ldrh r2, [r7, #6] + 800434a: 879a strh r2, [r3, #60] @ 0x3c + hspi->TxXferCount = Size; + 800434c: 68fb ldr r3, [r7, #12] + 800434e: 88fa ldrh r2, [r7, #6] + 8004350: 87da strh r2, [r3, #62] @ 0x3e + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + 8004352: 68fb ldr r3, [r7, #12] + 8004354: 2200 movs r2, #0 + 8004356: 641a str r2, [r3, #64] @ 0x40 + hspi->RxXferSize = 0U; + 8004358: 68fb ldr r3, [r7, #12] + 800435a: 2200 movs r2, #0 + 800435c: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 + hspi->RxXferCount = 0U; + 8004360: 68fb ldr r3, [r7, #12] + 8004362: 2200 movs r2, #0 + 8004364: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 + hspi->TxISR = NULL; + 8004368: 68fb ldr r3, [r7, #12] + 800436a: 2200 movs r2, #0 + 800436c: 651a str r2, [r3, #80] @ 0x50 + hspi->RxISR = NULL; + 800436e: 68fb ldr r3, [r7, #12] + 8004370: 2200 movs r2, #0 + 8004372: 64da str r2, [r3, #76] @ 0x4c + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + 8004374: 68fb ldr r3, [r7, #12] + 8004376: 689b ldr r3, [r3, #8] + 8004378: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 800437c: d10f bne.n 800439e <HAL_SPI_Transmit+0xbc> + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + 800437e: 68fb ldr r3, [r7, #12] + 8004380: 681b ldr r3, [r3, #0] + 8004382: 681a ldr r2, [r3, #0] + 8004384: 68fb ldr r3, [r7, #12] + 8004386: 681b ldr r3, [r3, #0] + 8004388: f022 0240 bic.w r2, r2, #64 @ 0x40 + 800438c: 601a str r2, [r3, #0] + SPI_1LINE_TX(hspi); + 800438e: 68fb ldr r3, [r7, #12] + 8004390: 681b ldr r3, [r3, #0] + 8004392: 681a ldr r2, [r3, #0] + 8004394: 68fb ldr r3, [r7, #12] + 8004396: 681b ldr r3, [r3, #0] + 8004398: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 800439c: 601a str r2, [r3, #0] + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 800439e: 68fb ldr r3, [r7, #12] + 80043a0: 681b ldr r3, [r3, #0] + 80043a2: 681b ldr r3, [r3, #0] + 80043a4: f003 0340 and.w r3, r3, #64 @ 0x40 + 80043a8: 2b40 cmp r3, #64 @ 0x40 + 80043aa: d007 beq.n 80043bc <HAL_SPI_Transmit+0xda> + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + 80043ac: 68fb ldr r3, [r7, #12] + 80043ae: 681b ldr r3, [r3, #0] + 80043b0: 681a ldr r2, [r3, #0] + 80043b2: 68fb ldr r3, [r7, #12] + 80043b4: 681b ldr r3, [r3, #0] + 80043b6: f042 0240 orr.w r2, r2, #64 @ 0x40 + 80043ba: 601a str r2, [r3, #0] + } + + /* Transmit data in 16 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 80043bc: 68fb ldr r3, [r7, #12] + 80043be: 68db ldr r3, [r3, #12] + 80043c0: f5b3 6fe0 cmp.w r3, #1792 @ 0x700 + 80043c4: d952 bls.n 800446c <HAL_SPI_Transmit+0x18a> + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 80043c6: 68fb ldr r3, [r7, #12] + 80043c8: 685b ldr r3, [r3, #4] + 80043ca: 2b00 cmp r3, #0 + 80043cc: d002 beq.n 80043d4 <HAL_SPI_Transmit+0xf2> + 80043ce: 8b7b ldrh r3, [r7, #26] + 80043d0: 2b01 cmp r3, #1 + 80043d2: d145 bne.n 8004460 <HAL_SPI_Transmit+0x17e> + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 80043d4: 68fb ldr r3, [r7, #12] + 80043d6: 6b9b ldr r3, [r3, #56] @ 0x38 + 80043d8: 881a ldrh r2, [r3, #0] + 80043da: 68fb ldr r3, [r7, #12] + 80043dc: 681b ldr r3, [r3, #0] + 80043de: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 80043e0: 68fb ldr r3, [r7, #12] + 80043e2: 6b9b ldr r3, [r3, #56] @ 0x38 + 80043e4: 1c9a adds r2, r3, #2 + 80043e6: 68fb ldr r3, [r7, #12] + 80043e8: 639a str r2, [r3, #56] @ 0x38 + hspi->TxXferCount--; + 80043ea: 68fb ldr r3, [r7, #12] + 80043ec: 8fdb ldrh r3, [r3, #62] @ 0x3e + 80043ee: b29b uxth r3, r3 + 80043f0: 3b01 subs r3, #1 + 80043f2: b29a uxth r2, r3 + 80043f4: 68fb ldr r3, [r7, #12] + 80043f6: 87da strh r2, [r3, #62] @ 0x3e + } + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0U) + 80043f8: e032 b.n 8004460 <HAL_SPI_Transmit+0x17e> + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 80043fa: 68fb ldr r3, [r7, #12] + 80043fc: 681b ldr r3, [r3, #0] + 80043fe: 689b ldr r3, [r3, #8] + 8004400: f003 0302 and.w r3, r3, #2 + 8004404: 2b02 cmp r3, #2 + 8004406: d112 bne.n 800442e <HAL_SPI_Transmit+0x14c> + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 8004408: 68fb ldr r3, [r7, #12] + 800440a: 6b9b ldr r3, [r3, #56] @ 0x38 + 800440c: 881a ldrh r2, [r3, #0] + 800440e: 68fb ldr r3, [r7, #12] + 8004410: 681b ldr r3, [r3, #0] + 8004412: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8004414: 68fb ldr r3, [r7, #12] + 8004416: 6b9b ldr r3, [r3, #56] @ 0x38 + 8004418: 1c9a adds r2, r3, #2 + 800441a: 68fb ldr r3, [r7, #12] + 800441c: 639a str r2, [r3, #56] @ 0x38 + hspi->TxXferCount--; + 800441e: 68fb ldr r3, [r7, #12] + 8004420: 8fdb ldrh r3, [r3, #62] @ 0x3e + 8004422: b29b uxth r3, r3 + 8004424: 3b01 subs r3, #1 + 8004426: b29a uxth r2, r3 + 8004428: 68fb ldr r3, [r7, #12] + 800442a: 87da strh r2, [r3, #62] @ 0x3e + 800442c: e018 b.n 8004460 <HAL_SPI_Transmit+0x17e> + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 800442e: f7fc ff1d bl 800126c <HAL_GetTick> + 8004432: 4602 mov r2, r0 + 8004434: 69fb ldr r3, [r7, #28] + 8004436: 1ad3 subs r3, r2, r3 + 8004438: 683a ldr r2, [r7, #0] + 800443a: 429a cmp r2, r3 + 800443c: d803 bhi.n 8004446 <HAL_SPI_Transmit+0x164> + 800443e: 683b ldr r3, [r7, #0] + 8004440: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8004444: d102 bne.n 800444c <HAL_SPI_Transmit+0x16a> + 8004446: 683b ldr r3, [r7, #0] + 8004448: 2b00 cmp r3, #0 + 800444a: d109 bne.n 8004460 <HAL_SPI_Transmit+0x17e> + { + hspi->State = HAL_SPI_STATE_READY; + 800444c: 68fb ldr r3, [r7, #12] + 800444e: 2201 movs r2, #1 + 8004450: f883 205d strb.w r2, [r3, #93] @ 0x5d + __HAL_UNLOCK(hspi); + 8004454: 68fb ldr r3, [r7, #12] + 8004456: 2200 movs r2, #0 + 8004458: f883 205c strb.w r2, [r3, #92] @ 0x5c + return HAL_TIMEOUT; + 800445c: 2303 movs r3, #3 + 800445e: e0b2 b.n 80045c6 <HAL_SPI_Transmit+0x2e4> + while (hspi->TxXferCount > 0U) + 8004460: 68fb ldr r3, [r7, #12] + 8004462: 8fdb ldrh r3, [r3, #62] @ 0x3e + 8004464: b29b uxth r3, r3 + 8004466: 2b00 cmp r3, #0 + 8004468: d1c7 bne.n 80043fa <HAL_SPI_Transmit+0x118> + 800446a: e083 b.n 8004574 <HAL_SPI_Transmit+0x292> + } + } + /* Transmit data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 800446c: 68fb ldr r3, [r7, #12] + 800446e: 685b ldr r3, [r3, #4] + 8004470: 2b00 cmp r3, #0 + 8004472: d002 beq.n 800447a <HAL_SPI_Transmit+0x198> + 8004474: 8b7b ldrh r3, [r7, #26] + 8004476: 2b01 cmp r3, #1 + 8004478: d177 bne.n 800456a <HAL_SPI_Transmit+0x288> + { + if (hspi->TxXferCount > 1U) + 800447a: 68fb ldr r3, [r7, #12] + 800447c: 8fdb ldrh r3, [r3, #62] @ 0x3e + 800447e: b29b uxth r3, r3 + 8004480: 2b01 cmp r3, #1 + 8004482: d912 bls.n 80044aa <HAL_SPI_Transmit+0x1c8> + { + /* write on the data register in packing mode */ + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 8004484: 68fb ldr r3, [r7, #12] + 8004486: 6b9b ldr r3, [r3, #56] @ 0x38 + 8004488: 881a ldrh r2, [r3, #0] + 800448a: 68fb ldr r3, [r7, #12] + 800448c: 681b ldr r3, [r3, #0] + 800448e: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8004490: 68fb ldr r3, [r7, #12] + 8004492: 6b9b ldr r3, [r3, #56] @ 0x38 + 8004494: 1c9a adds r2, r3, #2 + 8004496: 68fb ldr r3, [r7, #12] + 8004498: 639a str r2, [r3, #56] @ 0x38 + hspi->TxXferCount -= 2U; + 800449a: 68fb ldr r3, [r7, #12] + 800449c: 8fdb ldrh r3, [r3, #62] @ 0x3e + 800449e: b29b uxth r3, r3 + 80044a0: 3b02 subs r3, #2 + 80044a2: b29a uxth r2, r3 + 80044a4: 68fb ldr r3, [r7, #12] + 80044a6: 87da strh r2, [r3, #62] @ 0x3e + 80044a8: e05f b.n 800456a <HAL_SPI_Transmit+0x288> + } + else + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + 80044aa: 68fb ldr r3, [r7, #12] + 80044ac: 6b9a ldr r2, [r3, #56] @ 0x38 + 80044ae: 68fb ldr r3, [r7, #12] + 80044b0: 681b ldr r3, [r3, #0] + 80044b2: 330c adds r3, #12 + 80044b4: 7812 ldrb r2, [r2, #0] + 80044b6: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr ++; + 80044b8: 68fb ldr r3, [r7, #12] + 80044ba: 6b9b ldr r3, [r3, #56] @ 0x38 + 80044bc: 1c5a adds r2, r3, #1 + 80044be: 68fb ldr r3, [r7, #12] + 80044c0: 639a str r2, [r3, #56] @ 0x38 + hspi->TxXferCount--; + 80044c2: 68fb ldr r3, [r7, #12] + 80044c4: 8fdb ldrh r3, [r3, #62] @ 0x3e + 80044c6: b29b uxth r3, r3 + 80044c8: 3b01 subs r3, #1 + 80044ca: b29a uxth r2, r3 + 80044cc: 68fb ldr r3, [r7, #12] + 80044ce: 87da strh r2, [r3, #62] @ 0x3e + } + } + while (hspi->TxXferCount > 0U) + 80044d0: e04b b.n 800456a <HAL_SPI_Transmit+0x288> + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 80044d2: 68fb ldr r3, [r7, #12] + 80044d4: 681b ldr r3, [r3, #0] + 80044d6: 689b ldr r3, [r3, #8] + 80044d8: f003 0302 and.w r3, r3, #2 + 80044dc: 2b02 cmp r3, #2 + 80044de: d12b bne.n 8004538 <HAL_SPI_Transmit+0x256> + { + if (hspi->TxXferCount > 1U) + 80044e0: 68fb ldr r3, [r7, #12] + 80044e2: 8fdb ldrh r3, [r3, #62] @ 0x3e + 80044e4: b29b uxth r3, r3 + 80044e6: 2b01 cmp r3, #1 + 80044e8: d912 bls.n 8004510 <HAL_SPI_Transmit+0x22e> + { + /* write on the data register in packing mode */ + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 80044ea: 68fb ldr r3, [r7, #12] + 80044ec: 6b9b ldr r3, [r3, #56] @ 0x38 + 80044ee: 881a ldrh r2, [r3, #0] + 80044f0: 68fb ldr r3, [r7, #12] + 80044f2: 681b ldr r3, [r3, #0] + 80044f4: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 80044f6: 68fb ldr r3, [r7, #12] + 80044f8: 6b9b ldr r3, [r3, #56] @ 0x38 + 80044fa: 1c9a adds r2, r3, #2 + 80044fc: 68fb ldr r3, [r7, #12] + 80044fe: 639a str r2, [r3, #56] @ 0x38 + hspi->TxXferCount -= 2U; + 8004500: 68fb ldr r3, [r7, #12] + 8004502: 8fdb ldrh r3, [r3, #62] @ 0x3e + 8004504: b29b uxth r3, r3 + 8004506: 3b02 subs r3, #2 + 8004508: b29a uxth r2, r3 + 800450a: 68fb ldr r3, [r7, #12] + 800450c: 87da strh r2, [r3, #62] @ 0x3e + 800450e: e02c b.n 800456a <HAL_SPI_Transmit+0x288> + } + else + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + 8004510: 68fb ldr r3, [r7, #12] + 8004512: 6b9a ldr r2, [r3, #56] @ 0x38 + 8004514: 68fb ldr r3, [r7, #12] + 8004516: 681b ldr r3, [r3, #0] + 8004518: 330c adds r3, #12 + 800451a: 7812 ldrb r2, [r2, #0] + 800451c: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr++; + 800451e: 68fb ldr r3, [r7, #12] + 8004520: 6b9b ldr r3, [r3, #56] @ 0x38 + 8004522: 1c5a adds r2, r3, #1 + 8004524: 68fb ldr r3, [r7, #12] + 8004526: 639a str r2, [r3, #56] @ 0x38 + hspi->TxXferCount--; + 8004528: 68fb ldr r3, [r7, #12] + 800452a: 8fdb ldrh r3, [r3, #62] @ 0x3e + 800452c: b29b uxth r3, r3 + 800452e: 3b01 subs r3, #1 + 8004530: b29a uxth r2, r3 + 8004532: 68fb ldr r3, [r7, #12] + 8004534: 87da strh r2, [r3, #62] @ 0x3e + 8004536: e018 b.n 800456a <HAL_SPI_Transmit+0x288> + } + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 8004538: f7fc fe98 bl 800126c <HAL_GetTick> + 800453c: 4602 mov r2, r0 + 800453e: 69fb ldr r3, [r7, #28] + 8004540: 1ad3 subs r3, r2, r3 + 8004542: 683a ldr r2, [r7, #0] + 8004544: 429a cmp r2, r3 + 8004546: d803 bhi.n 8004550 <HAL_SPI_Transmit+0x26e> + 8004548: 683b ldr r3, [r7, #0] + 800454a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 800454e: d102 bne.n 8004556 <HAL_SPI_Transmit+0x274> + 8004550: 683b ldr r3, [r7, #0] + 8004552: 2b00 cmp r3, #0 + 8004554: d109 bne.n 800456a <HAL_SPI_Transmit+0x288> + { + hspi->State = HAL_SPI_STATE_READY; + 8004556: 68fb ldr r3, [r7, #12] + 8004558: 2201 movs r2, #1 + 800455a: f883 205d strb.w r2, [r3, #93] @ 0x5d + __HAL_UNLOCK(hspi); + 800455e: 68fb ldr r3, [r7, #12] + 8004560: 2200 movs r2, #0 + 8004562: f883 205c strb.w r2, [r3, #92] @ 0x5c + return HAL_TIMEOUT; + 8004566: 2303 movs r3, #3 + 8004568: e02d b.n 80045c6 <HAL_SPI_Transmit+0x2e4> + while (hspi->TxXferCount > 0U) + 800456a: 68fb ldr r3, [r7, #12] + 800456c: 8fdb ldrh r3, [r3, #62] @ 0x3e + 800456e: b29b uxth r3, r3 + 8004570: 2b00 cmp r3, #0 + 8004572: d1ae bne.n 80044d2 <HAL_SPI_Transmit+0x1f0> + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + 8004574: 69fa ldr r2, [r7, #28] + 8004576: 6839 ldr r1, [r7, #0] + 8004578: 68f8 ldr r0, [r7, #12] + 800457a: f000 f947 bl 800480c <SPI_EndRxTxTransaction> + 800457e: 4603 mov r3, r0 + 8004580: 2b00 cmp r3, #0 + 8004582: d002 beq.n 800458a <HAL_SPI_Transmit+0x2a8> + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 8004584: 68fb ldr r3, [r7, #12] + 8004586: 2220 movs r2, #32 + 8004588: 661a str r2, [r3, #96] @ 0x60 + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + 800458a: 68fb ldr r3, [r7, #12] + 800458c: 689b ldr r3, [r3, #8] + 800458e: 2b00 cmp r3, #0 + 8004590: d10a bne.n 80045a8 <HAL_SPI_Transmit+0x2c6> + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + 8004592: 2300 movs r3, #0 + 8004594: 617b str r3, [r7, #20] + 8004596: 68fb ldr r3, [r7, #12] + 8004598: 681b ldr r3, [r3, #0] + 800459a: 68db ldr r3, [r3, #12] + 800459c: 617b str r3, [r7, #20] + 800459e: 68fb ldr r3, [r7, #12] + 80045a0: 681b ldr r3, [r3, #0] + 80045a2: 689b ldr r3, [r3, #8] + 80045a4: 617b str r3, [r7, #20] + 80045a6: 697b ldr r3, [r7, #20] + } + + hspi->State = HAL_SPI_STATE_READY; + 80045a8: 68fb ldr r3, [r7, #12] + 80045aa: 2201 movs r2, #1 + 80045ac: f883 205d strb.w r2, [r3, #93] @ 0x5d + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 80045b0: 68fb ldr r3, [r7, #12] + 80045b2: 2200 movs r2, #0 + 80045b4: f883 205c strb.w r2, [r3, #92] @ 0x5c + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 80045b8: 68fb ldr r3, [r7, #12] + 80045ba: 6e1b ldr r3, [r3, #96] @ 0x60 + 80045bc: 2b00 cmp r3, #0 + 80045be: d001 beq.n 80045c4 <HAL_SPI_Transmit+0x2e2> + { + return HAL_ERROR; + 80045c0: 2301 movs r3, #1 + 80045c2: e000 b.n 80045c6 <HAL_SPI_Transmit+0x2e4> + } + else + { + return HAL_OK; + 80045c4: 2300 movs r3, #0 + } +} + 80045c6: 4618 mov r0, r3 + 80045c8: 3720 adds r7, #32 + 80045ca: 46bd mov sp, r7 + 80045cc: bd80 pop {r7, pc} + ... + +080045d0 <SPI_WaitFlagStateUntilTimeout>: + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart) +{ + 80045d0: b580 push {r7, lr} + 80045d2: b088 sub sp, #32 + 80045d4: af00 add r7, sp, #0 + 80045d6: 60f8 str r0, [r7, #12] + 80045d8: 60b9 str r1, [r7, #8] + 80045da: 603b str r3, [r7, #0] + 80045dc: 4613 mov r3, r2 + 80045de: 71fb strb r3, [r7, #7] + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + 80045e0: f7fc fe44 bl 800126c <HAL_GetTick> + 80045e4: 4602 mov r2, r0 + 80045e6: 6abb ldr r3, [r7, #40] @ 0x28 + 80045e8: 1a9b subs r3, r3, r2 + 80045ea: 683a ldr r2, [r7, #0] + 80045ec: 4413 add r3, r2 + 80045ee: 61fb str r3, [r7, #28] + tmp_tickstart = HAL_GetTick(); + 80045f0: f7fc fe3c bl 800126c <HAL_GetTick> + 80045f4: 61b8 str r0, [r7, #24] + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + 80045f6: 4b39 ldr r3, [pc, #228] @ (80046dc <SPI_WaitFlagStateUntilTimeout+0x10c>) + 80045f8: 681b ldr r3, [r3, #0] + 80045fa: 015b lsls r3, r3, #5 + 80045fc: 0d1b lsrs r3, r3, #20 + 80045fe: 69fa ldr r2, [r7, #28] + 8004600: fb02 f303 mul.w r3, r2, r3 + 8004604: 617b str r3, [r7, #20] + + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 8004606: e055 b.n 80046b4 <SPI_WaitFlagStateUntilTimeout+0xe4> + { + if (Timeout != HAL_MAX_DELAY) + 8004608: 683b ldr r3, [r7, #0] + 800460a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 800460e: d051 beq.n 80046b4 <SPI_WaitFlagStateUntilTimeout+0xe4> + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + 8004610: f7fc fe2c bl 800126c <HAL_GetTick> + 8004614: 4602 mov r2, r0 + 8004616: 69bb ldr r3, [r7, #24] + 8004618: 1ad3 subs r3, r2, r3 + 800461a: 69fa ldr r2, [r7, #28] + 800461c: 429a cmp r2, r3 + 800461e: d902 bls.n 8004626 <SPI_WaitFlagStateUntilTimeout+0x56> + 8004620: 69fb ldr r3, [r7, #28] + 8004622: 2b00 cmp r3, #0 + 8004624: d13d bne.n 80046a2 <SPI_WaitFlagStateUntilTimeout+0xd2> + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 8004626: 68fb ldr r3, [r7, #12] + 8004628: 681b ldr r3, [r3, #0] + 800462a: 685a ldr r2, [r3, #4] + 800462c: 68fb ldr r3, [r7, #12] + 800462e: 681b ldr r3, [r3, #0] + 8004630: f022 02e0 bic.w r2, r2, #224 @ 0xe0 + 8004634: 605a str r2, [r3, #4] + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 8004636: 68fb ldr r3, [r7, #12] + 8004638: 685b ldr r3, [r3, #4] + 800463a: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 800463e: d111 bne.n 8004664 <SPI_WaitFlagStateUntilTimeout+0x94> + 8004640: 68fb ldr r3, [r7, #12] + 8004642: 689b ldr r3, [r3, #8] + 8004644: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 8004648: d004 beq.n 8004654 <SPI_WaitFlagStateUntilTimeout+0x84> + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + 800464a: 68fb ldr r3, [r7, #12] + 800464c: 689b ldr r3, [r3, #8] + 800464e: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8004652: d107 bne.n 8004664 <SPI_WaitFlagStateUntilTimeout+0x94> + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 8004654: 68fb ldr r3, [r7, #12] + 8004656: 681b ldr r3, [r3, #0] + 8004658: 681a ldr r2, [r3, #0] + 800465a: 68fb ldr r3, [r7, #12] + 800465c: 681b ldr r3, [r3, #0] + 800465e: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8004662: 601a str r2, [r3, #0] + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 8004664: 68fb ldr r3, [r7, #12] + 8004666: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004668: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 800466c: d10f bne.n 800468e <SPI_WaitFlagStateUntilTimeout+0xbe> + { + SPI_RESET_CRC(hspi); + 800466e: 68fb ldr r3, [r7, #12] + 8004670: 681b ldr r3, [r3, #0] + 8004672: 681a ldr r2, [r3, #0] + 8004674: 68fb ldr r3, [r7, #12] + 8004676: 681b ldr r3, [r3, #0] + 8004678: f422 5200 bic.w r2, r2, #8192 @ 0x2000 + 800467c: 601a str r2, [r3, #0] + 800467e: 68fb ldr r3, [r7, #12] + 8004680: 681b ldr r3, [r3, #0] + 8004682: 681a ldr r2, [r3, #0] + 8004684: 68fb ldr r3, [r7, #12] + 8004686: 681b ldr r3, [r3, #0] + 8004688: f442 5200 orr.w r2, r2, #8192 @ 0x2000 + 800468c: 601a str r2, [r3, #0] + } + + hspi->State = HAL_SPI_STATE_READY; + 800468e: 68fb ldr r3, [r7, #12] + 8004690: 2201 movs r2, #1 + 8004692: f883 205d strb.w r2, [r3, #93] @ 0x5d + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 8004696: 68fb ldr r3, [r7, #12] + 8004698: 2200 movs r2, #0 + 800469a: f883 205c strb.w r2, [r3, #92] @ 0x5c + + return HAL_TIMEOUT; + 800469e: 2303 movs r3, #3 + 80046a0: e018 b.n 80046d4 <SPI_WaitFlagStateUntilTimeout+0x104> + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if (count == 0U) + 80046a2: 697b ldr r3, [r7, #20] + 80046a4: 2b00 cmp r3, #0 + 80046a6: d102 bne.n 80046ae <SPI_WaitFlagStateUntilTimeout+0xde> + { + tmp_timeout = 0U; + 80046a8: 2300 movs r3, #0 + 80046aa: 61fb str r3, [r7, #28] + 80046ac: e002 b.n 80046b4 <SPI_WaitFlagStateUntilTimeout+0xe4> + } + else + { + count--; + 80046ae: 697b ldr r3, [r7, #20] + 80046b0: 3b01 subs r3, #1 + 80046b2: 617b str r3, [r7, #20] + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 80046b4: 68fb ldr r3, [r7, #12] + 80046b6: 681b ldr r3, [r3, #0] + 80046b8: 689a ldr r2, [r3, #8] + 80046ba: 68bb ldr r3, [r7, #8] + 80046bc: 4013 ands r3, r2 + 80046be: 68ba ldr r2, [r7, #8] + 80046c0: 429a cmp r2, r3 + 80046c2: bf0c ite eq + 80046c4: 2301 moveq r3, #1 + 80046c6: 2300 movne r3, #0 + 80046c8: b2db uxtb r3, r3 + 80046ca: 461a mov r2, r3 + 80046cc: 79fb ldrb r3, [r7, #7] + 80046ce: 429a cmp r2, r3 + 80046d0: d19a bne.n 8004608 <SPI_WaitFlagStateUntilTimeout+0x38> + } + } + } + + return HAL_OK; + 80046d2: 2300 movs r3, #0 +} + 80046d4: 4618 mov r0, r3 + 80046d6: 3720 adds r7, #32 + 80046d8: 46bd mov sp, r7 + 80046da: bd80 pop {r7, pc} + 80046dc: 200006c8 .word 0x200006c8 + +080046e0 <SPI_WaitFifoStateUntilTimeout>: + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, + uint32_t Timeout, uint32_t Tickstart) +{ + 80046e0: b580 push {r7, lr} + 80046e2: b08a sub sp, #40 @ 0x28 + 80046e4: af00 add r7, sp, #0 + 80046e6: 60f8 str r0, [r7, #12] + 80046e8: 60b9 str r1, [r7, #8] + 80046ea: 607a str r2, [r7, #4] + 80046ec: 603b str r3, [r7, #0] + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + __IO const uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; + 80046ee: 2300 movs r3, #0 + 80046f0: 75fb strb r3, [r7, #23] + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + 80046f2: f7fc fdbb bl 800126c <HAL_GetTick> + 80046f6: 4602 mov r2, r0 + 80046f8: 6b3b ldr r3, [r7, #48] @ 0x30 + 80046fa: 1a9b subs r3, r3, r2 + 80046fc: 683a ldr r2, [r7, #0] + 80046fe: 4413 add r3, r2 + 8004700: 627b str r3, [r7, #36] @ 0x24 + tmp_tickstart = HAL_GetTick(); + 8004702: f7fc fdb3 bl 800126c <HAL_GetTick> + 8004706: 6238 str r0, [r7, #32] + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + 8004708: 68fb ldr r3, [r7, #12] + 800470a: 681b ldr r3, [r3, #0] + 800470c: 330c adds r3, #12 + 800470e: 61fb str r3, [r7, #28] + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U); + 8004710: 4b3d ldr r3, [pc, #244] @ (8004808 <SPI_WaitFifoStateUntilTimeout+0x128>) + 8004712: 681a ldr r2, [r3, #0] + 8004714: 4613 mov r3, r2 + 8004716: 009b lsls r3, r3, #2 + 8004718: 4413 add r3, r2 + 800471a: 00da lsls r2, r3, #3 + 800471c: 1ad3 subs r3, r2, r3 + 800471e: 0d1b lsrs r3, r3, #20 + 8004720: 6a7a ldr r2, [r7, #36] @ 0x24 + 8004722: fb02 f303 mul.w r3, r2, r3 + 8004726: 61bb str r3, [r7, #24] + + while ((hspi->Instance->SR & Fifo) != State) + 8004728: e061 b.n 80047ee <SPI_WaitFifoStateUntilTimeout+0x10e> + { + if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) + 800472a: 68bb ldr r3, [r7, #8] + 800472c: f5b3 6fc0 cmp.w r3, #1536 @ 0x600 + 8004730: d107 bne.n 8004742 <SPI_WaitFifoStateUntilTimeout+0x62> + 8004732: 687b ldr r3, [r7, #4] + 8004734: 2b00 cmp r3, #0 + 8004736: d104 bne.n 8004742 <SPI_WaitFifoStateUntilTimeout+0x62> + { + /* Flush Data Register by a blank read */ + tmpreg8 = *ptmpreg8; + 8004738: 69fb ldr r3, [r7, #28] + 800473a: 781b ldrb r3, [r3, #0] + 800473c: b2db uxtb r3, r3 + 800473e: 75fb strb r3, [r7, #23] + /* To avoid GCC warning */ + UNUSED(tmpreg8); + 8004740: 7dfb ldrb r3, [r7, #23] + } + + if (Timeout != HAL_MAX_DELAY) + 8004742: 683b ldr r3, [r7, #0] + 8004744: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8004748: d051 beq.n 80047ee <SPI_WaitFifoStateUntilTimeout+0x10e> + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + 800474a: f7fc fd8f bl 800126c <HAL_GetTick> + 800474e: 4602 mov r2, r0 + 8004750: 6a3b ldr r3, [r7, #32] + 8004752: 1ad3 subs r3, r2, r3 + 8004754: 6a7a ldr r2, [r7, #36] @ 0x24 + 8004756: 429a cmp r2, r3 + 8004758: d902 bls.n 8004760 <SPI_WaitFifoStateUntilTimeout+0x80> + 800475a: 6a7b ldr r3, [r7, #36] @ 0x24 + 800475c: 2b00 cmp r3, #0 + 800475e: d13d bne.n 80047dc <SPI_WaitFifoStateUntilTimeout+0xfc> + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 8004760: 68fb ldr r3, [r7, #12] + 8004762: 681b ldr r3, [r3, #0] + 8004764: 685a ldr r2, [r3, #4] + 8004766: 68fb ldr r3, [r7, #12] + 8004768: 681b ldr r3, [r3, #0] + 800476a: f022 02e0 bic.w r2, r2, #224 @ 0xe0 + 800476e: 605a str r2, [r3, #4] + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 8004770: 68fb ldr r3, [r7, #12] + 8004772: 685b ldr r3, [r3, #4] + 8004774: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8004778: d111 bne.n 800479e <SPI_WaitFifoStateUntilTimeout+0xbe> + 800477a: 68fb ldr r3, [r7, #12] + 800477c: 689b ldr r3, [r3, #8] + 800477e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 8004782: d004 beq.n 800478e <SPI_WaitFifoStateUntilTimeout+0xae> + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + 8004784: 68fb ldr r3, [r7, #12] + 8004786: 689b ldr r3, [r3, #8] + 8004788: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 800478c: d107 bne.n 800479e <SPI_WaitFifoStateUntilTimeout+0xbe> + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 800478e: 68fb ldr r3, [r7, #12] + 8004790: 681b ldr r3, [r3, #0] + 8004792: 681a ldr r2, [r3, #0] + 8004794: 68fb ldr r3, [r7, #12] + 8004796: 681b ldr r3, [r3, #0] + 8004798: f022 0240 bic.w r2, r2, #64 @ 0x40 + 800479c: 601a str r2, [r3, #0] + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 800479e: 68fb ldr r3, [r7, #12] + 80047a0: 6a9b ldr r3, [r3, #40] @ 0x28 + 80047a2: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 80047a6: d10f bne.n 80047c8 <SPI_WaitFifoStateUntilTimeout+0xe8> + { + SPI_RESET_CRC(hspi); + 80047a8: 68fb ldr r3, [r7, #12] + 80047aa: 681b ldr r3, [r3, #0] + 80047ac: 681a ldr r2, [r3, #0] + 80047ae: 68fb ldr r3, [r7, #12] + 80047b0: 681b ldr r3, [r3, #0] + 80047b2: f422 5200 bic.w r2, r2, #8192 @ 0x2000 + 80047b6: 601a str r2, [r3, #0] + 80047b8: 68fb ldr r3, [r7, #12] + 80047ba: 681b ldr r3, [r3, #0] + 80047bc: 681a ldr r2, [r3, #0] + 80047be: 68fb ldr r3, [r7, #12] + 80047c0: 681b ldr r3, [r3, #0] + 80047c2: f442 5200 orr.w r2, r2, #8192 @ 0x2000 + 80047c6: 601a str r2, [r3, #0] + } + + hspi->State = HAL_SPI_STATE_READY; + 80047c8: 68fb ldr r3, [r7, #12] + 80047ca: 2201 movs r2, #1 + 80047cc: f883 205d strb.w r2, [r3, #93] @ 0x5d + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 80047d0: 68fb ldr r3, [r7, #12] + 80047d2: 2200 movs r2, #0 + 80047d4: f883 205c strb.w r2, [r3, #92] @ 0x5c + + return HAL_TIMEOUT; + 80047d8: 2303 movs r3, #3 + 80047da: e011 b.n 8004800 <SPI_WaitFifoStateUntilTimeout+0x120> + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if (count == 0U) + 80047dc: 69bb ldr r3, [r7, #24] + 80047de: 2b00 cmp r3, #0 + 80047e0: d102 bne.n 80047e8 <SPI_WaitFifoStateUntilTimeout+0x108> + { + tmp_timeout = 0U; + 80047e2: 2300 movs r3, #0 + 80047e4: 627b str r3, [r7, #36] @ 0x24 + 80047e6: e002 b.n 80047ee <SPI_WaitFifoStateUntilTimeout+0x10e> + } + else + { + count--; + 80047e8: 69bb ldr r3, [r7, #24] + 80047ea: 3b01 subs r3, #1 + 80047ec: 61bb str r3, [r7, #24] + while ((hspi->Instance->SR & Fifo) != State) + 80047ee: 68fb ldr r3, [r7, #12] + 80047f0: 681b ldr r3, [r3, #0] + 80047f2: 689a ldr r2, [r3, #8] + 80047f4: 68bb ldr r3, [r7, #8] + 80047f6: 4013 ands r3, r2 + 80047f8: 687a ldr r2, [r7, #4] + 80047fa: 429a cmp r2, r3 + 80047fc: d195 bne.n 800472a <SPI_WaitFifoStateUntilTimeout+0x4a> + } + } + } + + return HAL_OK; + 80047fe: 2300 movs r3, #0 +} + 8004800: 4618 mov r0, r3 + 8004802: 3728 adds r7, #40 @ 0x28 + 8004804: 46bd mov sp, r7 + 8004806: bd80 pop {r7, pc} + 8004808: 200006c8 .word 0x200006c8 + +0800480c <SPI_EndRxTxTransaction>: + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + 800480c: b580 push {r7, lr} + 800480e: b086 sub sp, #24 + 8004810: af02 add r7, sp, #8 + 8004812: 60f8 str r0, [r7, #12] + 8004814: 60b9 str r1, [r7, #8] + 8004816: 607a str r2, [r7, #4] + /* Control if the TX fifo is empty */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK) + 8004818: 687b ldr r3, [r7, #4] + 800481a: 9300 str r3, [sp, #0] + 800481c: 68bb ldr r3, [r7, #8] + 800481e: 2200 movs r2, #0 + 8004820: f44f 51c0 mov.w r1, #6144 @ 0x1800 + 8004824: 68f8 ldr r0, [r7, #12] + 8004826: f7ff ff5b bl 80046e0 <SPI_WaitFifoStateUntilTimeout> + 800482a: 4603 mov r3, r0 + 800482c: 2b00 cmp r3, #0 + 800482e: d007 beq.n 8004840 <SPI_EndRxTxTransaction+0x34> + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 8004830: 68fb ldr r3, [r7, #12] + 8004832: 6e1b ldr r3, [r3, #96] @ 0x60 + 8004834: f043 0220 orr.w r2, r3, #32 + 8004838: 68fb ldr r3, [r7, #12] + 800483a: 661a str r2, [r3, #96] @ 0x60 + return HAL_TIMEOUT; + 800483c: 2303 movs r3, #3 + 800483e: e027 b.n 8004890 <SPI_EndRxTxTransaction+0x84> + } + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + 8004840: 687b ldr r3, [r7, #4] + 8004842: 9300 str r3, [sp, #0] + 8004844: 68bb ldr r3, [r7, #8] + 8004846: 2200 movs r2, #0 + 8004848: 2180 movs r1, #128 @ 0x80 + 800484a: 68f8 ldr r0, [r7, #12] + 800484c: f7ff fec0 bl 80045d0 <SPI_WaitFlagStateUntilTimeout> + 8004850: 4603 mov r3, r0 + 8004852: 2b00 cmp r3, #0 + 8004854: d007 beq.n 8004866 <SPI_EndRxTxTransaction+0x5a> + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 8004856: 68fb ldr r3, [r7, #12] + 8004858: 6e1b ldr r3, [r3, #96] @ 0x60 + 800485a: f043 0220 orr.w r2, r3, #32 + 800485e: 68fb ldr r3, [r7, #12] + 8004860: 661a str r2, [r3, #96] @ 0x60 + return HAL_TIMEOUT; + 8004862: 2303 movs r3, #3 + 8004864: e014 b.n 8004890 <SPI_EndRxTxTransaction+0x84> + } + + /* Control if the RX fifo is empty */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) + 8004866: 687b ldr r3, [r7, #4] + 8004868: 9300 str r3, [sp, #0] + 800486a: 68bb ldr r3, [r7, #8] + 800486c: 2200 movs r2, #0 + 800486e: f44f 61c0 mov.w r1, #1536 @ 0x600 + 8004872: 68f8 ldr r0, [r7, #12] + 8004874: f7ff ff34 bl 80046e0 <SPI_WaitFifoStateUntilTimeout> + 8004878: 4603 mov r3, r0 + 800487a: 2b00 cmp r3, #0 + 800487c: d007 beq.n 800488e <SPI_EndRxTxTransaction+0x82> + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 800487e: 68fb ldr r3, [r7, #12] + 8004880: 6e1b ldr r3, [r3, #96] @ 0x60 + 8004882: f043 0220 orr.w r2, r3, #32 + 8004886: 68fb ldr r3, [r7, #12] + 8004888: 661a str r2, [r3, #96] @ 0x60 + return HAL_TIMEOUT; + 800488a: 2303 movs r3, #3 + 800488c: e000 b.n 8004890 <SPI_EndRxTxTransaction+0x84> + } + + return HAL_OK; + 800488e: 2300 movs r3, #0 +} + 8004890: 4618 mov r0, r3 + 8004892: 3710 adds r7, #16 + 8004894: 46bd mov sp, r7 + 8004896: bd80 pop {r7, pc} + +08004898 <malloc>: + 8004898: 4b02 ldr r3, [pc, #8] @ (80048a4 <malloc+0xc>) + 800489a: 4601 mov r1, r0 + 800489c: 6818 ldr r0, [r3, #0] + 800489e: f000 b825 b.w 80048ec <_malloc_r> + 80048a2: bf00 nop + 80048a4: 200006d4 .word 0x200006d4 + +080048a8 <sbrk_aligned>: + 80048a8: b570 push {r4, r5, r6, lr} + 80048aa: 4e0f ldr r6, [pc, #60] @ (80048e8 <sbrk_aligned+0x40>) + 80048ac: 460c mov r4, r1 + 80048ae: 6831 ldr r1, [r6, #0] + 80048b0: 4605 mov r5, r0 + 80048b2: b911 cbnz r1, 80048ba <sbrk_aligned+0x12> + 80048b4: f000 f8d0 bl 8004a58 <_sbrk_r> + 80048b8: 6030 str r0, [r6, #0] + 80048ba: 4621 mov r1, r4 + 80048bc: 4628 mov r0, r5 + 80048be: f000 f8cb bl 8004a58 <_sbrk_r> + 80048c2: 1c43 adds r3, r0, #1 + 80048c4: d103 bne.n 80048ce <sbrk_aligned+0x26> + 80048c6: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff + 80048ca: 4620 mov r0, r4 + 80048cc: bd70 pop {r4, r5, r6, pc} + 80048ce: 1cc4 adds r4, r0, #3 + 80048d0: f024 0403 bic.w r4, r4, #3 + 80048d4: 42a0 cmp r0, r4 + 80048d6: d0f8 beq.n 80048ca <sbrk_aligned+0x22> + 80048d8: 1a21 subs r1, r4, r0 + 80048da: 4628 mov r0, r5 + 80048dc: f000 f8bc bl 8004a58 <_sbrk_r> + 80048e0: 3001 adds r0, #1 + 80048e2: d1f2 bne.n 80048ca <sbrk_aligned+0x22> + 80048e4: e7ef b.n 80048c6 <sbrk_aligned+0x1e> + 80048e6: bf00 nop + 80048e8: 200008a8 .word 0x200008a8 + +080048ec <_malloc_r>: + 80048ec: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 80048f0: 1ccd adds r5, r1, #3 + 80048f2: f025 0503 bic.w r5, r5, #3 + 80048f6: 3508 adds r5, #8 + 80048f8: 2d0c cmp r5, #12 + 80048fa: bf38 it cc + 80048fc: 250c movcc r5, #12 + 80048fe: 2d00 cmp r5, #0 + 8004900: 4606 mov r6, r0 + 8004902: db01 blt.n 8004908 <_malloc_r+0x1c> + 8004904: 42a9 cmp r1, r5 + 8004906: d904 bls.n 8004912 <_malloc_r+0x26> + 8004908: 230c movs r3, #12 + 800490a: 6033 str r3, [r6, #0] + 800490c: 2000 movs r0, #0 + 800490e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 8004912: f8df 80d4 ldr.w r8, [pc, #212] @ 80049e8 <_malloc_r+0xfc> + 8004916: f000 f869 bl 80049ec <__malloc_lock> + 800491a: f8d8 3000 ldr.w r3, [r8] + 800491e: 461c mov r4, r3 + 8004920: bb44 cbnz r4, 8004974 <_malloc_r+0x88> + 8004922: 4629 mov r1, r5 + 8004924: 4630 mov r0, r6 + 8004926: f7ff ffbf bl 80048a8 <sbrk_aligned> + 800492a: 1c43 adds r3, r0, #1 + 800492c: 4604 mov r4, r0 + 800492e: d158 bne.n 80049e2 <_malloc_r+0xf6> + 8004930: f8d8 4000 ldr.w r4, [r8] + 8004934: 4627 mov r7, r4 + 8004936: 2f00 cmp r7, #0 + 8004938: d143 bne.n 80049c2 <_malloc_r+0xd6> + 800493a: 2c00 cmp r4, #0 + 800493c: d04b beq.n 80049d6 <_malloc_r+0xea> + 800493e: 6823 ldr r3, [r4, #0] + 8004940: 4639 mov r1, r7 + 8004942: 4630 mov r0, r6 + 8004944: eb04 0903 add.w r9, r4, r3 + 8004948: f000 f886 bl 8004a58 <_sbrk_r> + 800494c: 4581 cmp r9, r0 + 800494e: d142 bne.n 80049d6 <_malloc_r+0xea> + 8004950: 6821 ldr r1, [r4, #0] + 8004952: 1a6d subs r5, r5, r1 + 8004954: 4629 mov r1, r5 + 8004956: 4630 mov r0, r6 + 8004958: f7ff ffa6 bl 80048a8 <sbrk_aligned> + 800495c: 3001 adds r0, #1 + 800495e: d03a beq.n 80049d6 <_malloc_r+0xea> + 8004960: 6823 ldr r3, [r4, #0] + 8004962: 442b add r3, r5 + 8004964: 6023 str r3, [r4, #0] + 8004966: f8d8 3000 ldr.w r3, [r8] + 800496a: 685a ldr r2, [r3, #4] + 800496c: bb62 cbnz r2, 80049c8 <_malloc_r+0xdc> + 800496e: f8c8 7000 str.w r7, [r8] + 8004972: e00f b.n 8004994 <_malloc_r+0xa8> + 8004974: 6822 ldr r2, [r4, #0] + 8004976: 1b52 subs r2, r2, r5 + 8004978: d420 bmi.n 80049bc <_malloc_r+0xd0> + 800497a: 2a0b cmp r2, #11 + 800497c: d917 bls.n 80049ae <_malloc_r+0xc2> + 800497e: 1961 adds r1, r4, r5 + 8004980: 42a3 cmp r3, r4 + 8004982: 6025 str r5, [r4, #0] + 8004984: bf18 it ne + 8004986: 6059 strne r1, [r3, #4] + 8004988: 6863 ldr r3, [r4, #4] + 800498a: bf08 it eq + 800498c: f8c8 1000 streq.w r1, [r8] + 8004990: 5162 str r2, [r4, r5] + 8004992: 604b str r3, [r1, #4] + 8004994: 4630 mov r0, r6 + 8004996: f000 f82f bl 80049f8 <__malloc_unlock> + 800499a: f104 000b add.w r0, r4, #11 + 800499e: 1d23 adds r3, r4, #4 + 80049a0: f020 0007 bic.w r0, r0, #7 + 80049a4: 1ac2 subs r2, r0, r3 + 80049a6: bf1c itt ne + 80049a8: 1a1b subne r3, r3, r0 + 80049aa: 50a3 strne r3, [r4, r2] + 80049ac: e7af b.n 800490e <_malloc_r+0x22> + 80049ae: 6862 ldr r2, [r4, #4] + 80049b0: 42a3 cmp r3, r4 + 80049b2: bf0c ite eq + 80049b4: f8c8 2000 streq.w r2, [r8] + 80049b8: 605a strne r2, [r3, #4] + 80049ba: e7eb b.n 8004994 <_malloc_r+0xa8> + 80049bc: 4623 mov r3, r4 + 80049be: 6864 ldr r4, [r4, #4] + 80049c0: e7ae b.n 8004920 <_malloc_r+0x34> + 80049c2: 463c mov r4, r7 + 80049c4: 687f ldr r7, [r7, #4] + 80049c6: e7b6 b.n 8004936 <_malloc_r+0x4a> + 80049c8: 461a mov r2, r3 + 80049ca: 685b ldr r3, [r3, #4] + 80049cc: 42a3 cmp r3, r4 + 80049ce: d1fb bne.n 80049c8 <_malloc_r+0xdc> + 80049d0: 2300 movs r3, #0 + 80049d2: 6053 str r3, [r2, #4] + 80049d4: e7de b.n 8004994 <_malloc_r+0xa8> + 80049d6: 230c movs r3, #12 + 80049d8: 6033 str r3, [r6, #0] + 80049da: 4630 mov r0, r6 + 80049dc: f000 f80c bl 80049f8 <__malloc_unlock> + 80049e0: e794 b.n 800490c <_malloc_r+0x20> + 80049e2: 6005 str r5, [r0, #0] + 80049e4: e7d6 b.n 8004994 <_malloc_r+0xa8> + 80049e6: bf00 nop + 80049e8: 200008ac .word 0x200008ac + +080049ec <__malloc_lock>: + 80049ec: 4801 ldr r0, [pc, #4] @ (80049f4 <__malloc_lock+0x8>) + 80049ee: f000 b86d b.w 8004acc <__retarget_lock_acquire_recursive> + 80049f2: bf00 nop + 80049f4: 200009ec .word 0x200009ec + +080049f8 <__malloc_unlock>: + 80049f8: 4801 ldr r0, [pc, #4] @ (8004a00 <__malloc_unlock+0x8>) + 80049fa: f000 b868 b.w 8004ace <__retarget_lock_release_recursive> + 80049fe: bf00 nop + 8004a00: 200009ec .word 0x200009ec + +08004a04 <siprintf>: + 8004a04: b40e push {r1, r2, r3} + 8004a06: b510 push {r4, lr} + 8004a08: b09d sub sp, #116 @ 0x74 + 8004a0a: ab1f add r3, sp, #124 @ 0x7c + 8004a0c: 9002 str r0, [sp, #8] + 8004a0e: 9006 str r0, [sp, #24] + 8004a10: f06f 4100 mvn.w r1, #2147483648 @ 0x80000000 + 8004a14: 480a ldr r0, [pc, #40] @ (8004a40 <siprintf+0x3c>) + 8004a16: 9107 str r1, [sp, #28] + 8004a18: 9104 str r1, [sp, #16] + 8004a1a: 490a ldr r1, [pc, #40] @ (8004a44 <siprintf+0x40>) + 8004a1c: f853 2b04 ldr.w r2, [r3], #4 + 8004a20: 9105 str r1, [sp, #20] + 8004a22: 2400 movs r4, #0 + 8004a24: a902 add r1, sp, #8 + 8004a26: 6800 ldr r0, [r0, #0] + 8004a28: 9301 str r3, [sp, #4] + 8004a2a: 941b str r4, [sp, #108] @ 0x6c + 8004a2c: f000 f904 bl 8004c38 <_svfiprintf_r> + 8004a30: 9b02 ldr r3, [sp, #8] + 8004a32: 701c strb r4, [r3, #0] + 8004a34: b01d add sp, #116 @ 0x74 + 8004a36: e8bd 4010 ldmia.w sp!, {r4, lr} + 8004a3a: b003 add sp, #12 + 8004a3c: 4770 bx lr + 8004a3e: bf00 nop + 8004a40: 200006d4 .word 0x200006d4 + 8004a44: ffff0208 .word 0xffff0208 + +08004a48 <memset>: + 8004a48: 4402 add r2, r0 + 8004a4a: 4603 mov r3, r0 + 8004a4c: 4293 cmp r3, r2 + 8004a4e: d100 bne.n 8004a52 <memset+0xa> + 8004a50: 4770 bx lr + 8004a52: f803 1b01 strb.w r1, [r3], #1 + 8004a56: e7f9 b.n 8004a4c <memset+0x4> + +08004a58 <_sbrk_r>: + 8004a58: b538 push {r3, r4, r5, lr} + 8004a5a: 4d06 ldr r5, [pc, #24] @ (8004a74 <_sbrk_r+0x1c>) + 8004a5c: 2300 movs r3, #0 + 8004a5e: 4604 mov r4, r0 + 8004a60: 4608 mov r0, r1 + 8004a62: 602b str r3, [r5, #0] + 8004a64: f7fc fad2 bl 800100c <_sbrk> + 8004a68: 1c43 adds r3, r0, #1 + 8004a6a: d102 bne.n 8004a72 <_sbrk_r+0x1a> + 8004a6c: 682b ldr r3, [r5, #0] + 8004a6e: b103 cbz r3, 8004a72 <_sbrk_r+0x1a> + 8004a70: 6023 str r3, [r4, #0] + 8004a72: bd38 pop {r3, r4, r5, pc} + 8004a74: 200009e8 .word 0x200009e8 + +08004a78 <__errno>: + 8004a78: 4b01 ldr r3, [pc, #4] @ (8004a80 <__errno+0x8>) + 8004a7a: 6818 ldr r0, [r3, #0] + 8004a7c: 4770 bx lr + 8004a7e: bf00 nop + 8004a80: 200006d4 .word 0x200006d4 + +08004a84 <__libc_init_array>: + 8004a84: b570 push {r4, r5, r6, lr} + 8004a86: 4d0d ldr r5, [pc, #52] @ (8004abc <__libc_init_array+0x38>) + 8004a88: 4c0d ldr r4, [pc, #52] @ (8004ac0 <__libc_init_array+0x3c>) + 8004a8a: 1b64 subs r4, r4, r5 + 8004a8c: 10a4 asrs r4, r4, #2 + 8004a8e: 2600 movs r6, #0 + 8004a90: 42a6 cmp r6, r4 + 8004a92: d109 bne.n 8004aa8 <__libc_init_array+0x24> + 8004a94: 4d0b ldr r5, [pc, #44] @ (8004ac4 <__libc_init_array+0x40>) + 8004a96: 4c0c ldr r4, [pc, #48] @ (8004ac8 <__libc_init_array+0x44>) + 8004a98: f000 fba6 bl 80051e8 <_init> + 8004a9c: 1b64 subs r4, r4, r5 + 8004a9e: 10a4 asrs r4, r4, #2 + 8004aa0: 2600 movs r6, #0 + 8004aa2: 42a6 cmp r6, r4 + 8004aa4: d105 bne.n 8004ab2 <__libc_init_array+0x2e> + 8004aa6: bd70 pop {r4, r5, r6, pc} + 8004aa8: f855 3b04 ldr.w r3, [r5], #4 + 8004aac: 4798 blx r3 + 8004aae: 3601 adds r6, #1 + 8004ab0: e7ee b.n 8004a90 <__libc_init_array+0xc> + 8004ab2: f855 3b04 ldr.w r3, [r5], #4 + 8004ab6: 4798 blx r3 + 8004ab8: 3601 adds r6, #1 + 8004aba: e7f2 b.n 8004aa2 <__libc_init_array+0x1e> + 8004abc: 080052f4 .word 0x080052f4 + 8004ac0: 080052f4 .word 0x080052f4 + 8004ac4: 080052f4 .word 0x080052f4 + 8004ac8: 080052f8 .word 0x080052f8 + +08004acc <__retarget_lock_acquire_recursive>: + 8004acc: 4770 bx lr + +08004ace <__retarget_lock_release_recursive>: + 8004ace: 4770 bx lr + +08004ad0 <memcpy>: + 8004ad0: 440a add r2, r1 + 8004ad2: 4291 cmp r1, r2 + 8004ad4: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff + 8004ad8: d100 bne.n 8004adc <memcpy+0xc> + 8004ada: 4770 bx lr + 8004adc: b510 push {r4, lr} + 8004ade: f811 4b01 ldrb.w r4, [r1], #1 + 8004ae2: f803 4f01 strb.w r4, [r3, #1]! + 8004ae6: 4291 cmp r1, r2 + 8004ae8: d1f9 bne.n 8004ade <memcpy+0xe> + 8004aea: bd10 pop {r4, pc} + +08004aec <_free_r>: + 8004aec: b538 push {r3, r4, r5, lr} + 8004aee: 4605 mov r5, r0 + 8004af0: 2900 cmp r1, #0 + 8004af2: d041 beq.n 8004b78 <_free_r+0x8c> + 8004af4: f851 3c04 ldr.w r3, [r1, #-4] + 8004af8: 1f0c subs r4, r1, #4 + 8004afa: 2b00 cmp r3, #0 + 8004afc: bfb8 it lt + 8004afe: 18e4 addlt r4, r4, r3 + 8004b00: f7ff ff74 bl 80049ec <__malloc_lock> + 8004b04: 4a1d ldr r2, [pc, #116] @ (8004b7c <_free_r+0x90>) + 8004b06: 6813 ldr r3, [r2, #0] + 8004b08: b933 cbnz r3, 8004b18 <_free_r+0x2c> + 8004b0a: 6063 str r3, [r4, #4] + 8004b0c: 6014 str r4, [r2, #0] + 8004b0e: 4628 mov r0, r5 + 8004b10: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 8004b14: f7ff bf70 b.w 80049f8 <__malloc_unlock> + 8004b18: 42a3 cmp r3, r4 + 8004b1a: d908 bls.n 8004b2e <_free_r+0x42> + 8004b1c: 6820 ldr r0, [r4, #0] + 8004b1e: 1821 adds r1, r4, r0 + 8004b20: 428b cmp r3, r1 + 8004b22: bf01 itttt eq + 8004b24: 6819 ldreq r1, [r3, #0] + 8004b26: 685b ldreq r3, [r3, #4] + 8004b28: 1809 addeq r1, r1, r0 + 8004b2a: 6021 streq r1, [r4, #0] + 8004b2c: e7ed b.n 8004b0a <_free_r+0x1e> + 8004b2e: 461a mov r2, r3 + 8004b30: 685b ldr r3, [r3, #4] + 8004b32: b10b cbz r3, 8004b38 <_free_r+0x4c> + 8004b34: 42a3 cmp r3, r4 + 8004b36: d9fa bls.n 8004b2e <_free_r+0x42> + 8004b38: 6811 ldr r1, [r2, #0] + 8004b3a: 1850 adds r0, r2, r1 + 8004b3c: 42a0 cmp r0, r4 + 8004b3e: d10b bne.n 8004b58 <_free_r+0x6c> + 8004b40: 6820 ldr r0, [r4, #0] + 8004b42: 4401 add r1, r0 + 8004b44: 1850 adds r0, r2, r1 + 8004b46: 4283 cmp r3, r0 + 8004b48: 6011 str r1, [r2, #0] + 8004b4a: d1e0 bne.n 8004b0e <_free_r+0x22> + 8004b4c: 6818 ldr r0, [r3, #0] + 8004b4e: 685b ldr r3, [r3, #4] + 8004b50: 6053 str r3, [r2, #4] + 8004b52: 4408 add r0, r1 + 8004b54: 6010 str r0, [r2, #0] + 8004b56: e7da b.n 8004b0e <_free_r+0x22> + 8004b58: d902 bls.n 8004b60 <_free_r+0x74> + 8004b5a: 230c movs r3, #12 + 8004b5c: 602b str r3, [r5, #0] + 8004b5e: e7d6 b.n 8004b0e <_free_r+0x22> + 8004b60: 6820 ldr r0, [r4, #0] + 8004b62: 1821 adds r1, r4, r0 + 8004b64: 428b cmp r3, r1 + 8004b66: bf04 itt eq + 8004b68: 6819 ldreq r1, [r3, #0] + 8004b6a: 685b ldreq r3, [r3, #4] + 8004b6c: 6063 str r3, [r4, #4] + 8004b6e: bf04 itt eq + 8004b70: 1809 addeq r1, r1, r0 + 8004b72: 6021 streq r1, [r4, #0] + 8004b74: 6054 str r4, [r2, #4] + 8004b76: e7ca b.n 8004b0e <_free_r+0x22> + 8004b78: bd38 pop {r3, r4, r5, pc} + 8004b7a: bf00 nop + 8004b7c: 200008ac .word 0x200008ac + +08004b80 <__ssputs_r>: + 8004b80: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8004b84: 688e ldr r6, [r1, #8] + 8004b86: 461f mov r7, r3 + 8004b88: 42be cmp r6, r7 + 8004b8a: 680b ldr r3, [r1, #0] + 8004b8c: 4682 mov sl, r0 + 8004b8e: 460c mov r4, r1 + 8004b90: 4690 mov r8, r2 + 8004b92: d82d bhi.n 8004bf0 <__ssputs_r+0x70> + 8004b94: f9b1 200c ldrsh.w r2, [r1, #12] + 8004b98: f412 6f90 tst.w r2, #1152 @ 0x480 + 8004b9c: d026 beq.n 8004bec <__ssputs_r+0x6c> + 8004b9e: 6965 ldr r5, [r4, #20] + 8004ba0: 6909 ldr r1, [r1, #16] + 8004ba2: eb05 0545 add.w r5, r5, r5, lsl #1 + 8004ba6: eba3 0901 sub.w r9, r3, r1 + 8004baa: eb05 75d5 add.w r5, r5, r5, lsr #31 + 8004bae: 1c7b adds r3, r7, #1 + 8004bb0: 444b add r3, r9 + 8004bb2: 106d asrs r5, r5, #1 + 8004bb4: 429d cmp r5, r3 + 8004bb6: bf38 it cc + 8004bb8: 461d movcc r5, r3 + 8004bba: 0553 lsls r3, r2, #21 + 8004bbc: d527 bpl.n 8004c0e <__ssputs_r+0x8e> + 8004bbe: 4629 mov r1, r5 + 8004bc0: f7ff fe94 bl 80048ec <_malloc_r> + 8004bc4: 4606 mov r6, r0 + 8004bc6: b360 cbz r0, 8004c22 <__ssputs_r+0xa2> + 8004bc8: 6921 ldr r1, [r4, #16] + 8004bca: 464a mov r2, r9 + 8004bcc: f7ff ff80 bl 8004ad0 <memcpy> + 8004bd0: 89a3 ldrh r3, [r4, #12] + 8004bd2: f423 6390 bic.w r3, r3, #1152 @ 0x480 + 8004bd6: f043 0380 orr.w r3, r3, #128 @ 0x80 + 8004bda: 81a3 strh r3, [r4, #12] + 8004bdc: 6126 str r6, [r4, #16] + 8004bde: 6165 str r5, [r4, #20] + 8004be0: 444e add r6, r9 + 8004be2: eba5 0509 sub.w r5, r5, r9 + 8004be6: 6026 str r6, [r4, #0] + 8004be8: 60a5 str r5, [r4, #8] + 8004bea: 463e mov r6, r7 + 8004bec: 42be cmp r6, r7 + 8004bee: d900 bls.n 8004bf2 <__ssputs_r+0x72> + 8004bf0: 463e mov r6, r7 + 8004bf2: 6820 ldr r0, [r4, #0] + 8004bf4: 4632 mov r2, r6 + 8004bf6: 4641 mov r1, r8 + 8004bf8: f000 faa6 bl 8005148 <memmove> + 8004bfc: 68a3 ldr r3, [r4, #8] + 8004bfe: 1b9b subs r3, r3, r6 + 8004c00: 60a3 str r3, [r4, #8] + 8004c02: 6823 ldr r3, [r4, #0] + 8004c04: 4433 add r3, r6 + 8004c06: 6023 str r3, [r4, #0] + 8004c08: 2000 movs r0, #0 + 8004c0a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8004c0e: 462a mov r2, r5 + 8004c10: f000 fab4 bl 800517c <_realloc_r> + 8004c14: 4606 mov r6, r0 + 8004c16: 2800 cmp r0, #0 + 8004c18: d1e0 bne.n 8004bdc <__ssputs_r+0x5c> + 8004c1a: 6921 ldr r1, [r4, #16] + 8004c1c: 4650 mov r0, sl + 8004c1e: f7ff ff65 bl 8004aec <_free_r> + 8004c22: 230c movs r3, #12 + 8004c24: f8ca 3000 str.w r3, [sl] + 8004c28: 89a3 ldrh r3, [r4, #12] + 8004c2a: f043 0340 orr.w r3, r3, #64 @ 0x40 + 8004c2e: 81a3 strh r3, [r4, #12] + 8004c30: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8004c34: e7e9 b.n 8004c0a <__ssputs_r+0x8a> + ... + +08004c38 <_svfiprintf_r>: + 8004c38: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8004c3c: 4698 mov r8, r3 + 8004c3e: 898b ldrh r3, [r1, #12] + 8004c40: 061b lsls r3, r3, #24 + 8004c42: b09d sub sp, #116 @ 0x74 + 8004c44: 4607 mov r7, r0 + 8004c46: 460d mov r5, r1 + 8004c48: 4614 mov r4, r2 + 8004c4a: d510 bpl.n 8004c6e <_svfiprintf_r+0x36> + 8004c4c: 690b ldr r3, [r1, #16] + 8004c4e: b973 cbnz r3, 8004c6e <_svfiprintf_r+0x36> + 8004c50: 2140 movs r1, #64 @ 0x40 + 8004c52: f7ff fe4b bl 80048ec <_malloc_r> + 8004c56: 6028 str r0, [r5, #0] + 8004c58: 6128 str r0, [r5, #16] + 8004c5a: b930 cbnz r0, 8004c6a <_svfiprintf_r+0x32> + 8004c5c: 230c movs r3, #12 + 8004c5e: 603b str r3, [r7, #0] + 8004c60: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8004c64: b01d add sp, #116 @ 0x74 + 8004c66: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8004c6a: 2340 movs r3, #64 @ 0x40 + 8004c6c: 616b str r3, [r5, #20] + 8004c6e: 2300 movs r3, #0 + 8004c70: 9309 str r3, [sp, #36] @ 0x24 + 8004c72: 2320 movs r3, #32 + 8004c74: f88d 3029 strb.w r3, [sp, #41] @ 0x29 + 8004c78: f8cd 800c str.w r8, [sp, #12] + 8004c7c: 2330 movs r3, #48 @ 0x30 + 8004c7e: f8df 819c ldr.w r8, [pc, #412] @ 8004e1c <_svfiprintf_r+0x1e4> + 8004c82: f88d 302a strb.w r3, [sp, #42] @ 0x2a + 8004c86: f04f 0901 mov.w r9, #1 + 8004c8a: 4623 mov r3, r4 + 8004c8c: 469a mov sl, r3 + 8004c8e: f813 2b01 ldrb.w r2, [r3], #1 + 8004c92: b10a cbz r2, 8004c98 <_svfiprintf_r+0x60> + 8004c94: 2a25 cmp r2, #37 @ 0x25 + 8004c96: d1f9 bne.n 8004c8c <_svfiprintf_r+0x54> + 8004c98: ebba 0b04 subs.w fp, sl, r4 + 8004c9c: d00b beq.n 8004cb6 <_svfiprintf_r+0x7e> + 8004c9e: 465b mov r3, fp + 8004ca0: 4622 mov r2, r4 + 8004ca2: 4629 mov r1, r5 + 8004ca4: 4638 mov r0, r7 + 8004ca6: f7ff ff6b bl 8004b80 <__ssputs_r> + 8004caa: 3001 adds r0, #1 + 8004cac: f000 80a7 beq.w 8004dfe <_svfiprintf_r+0x1c6> + 8004cb0: 9a09 ldr r2, [sp, #36] @ 0x24 + 8004cb2: 445a add r2, fp + 8004cb4: 9209 str r2, [sp, #36] @ 0x24 + 8004cb6: f89a 3000 ldrb.w r3, [sl] + 8004cba: 2b00 cmp r3, #0 + 8004cbc: f000 809f beq.w 8004dfe <_svfiprintf_r+0x1c6> + 8004cc0: 2300 movs r3, #0 + 8004cc2: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8004cc6: e9cd 2305 strd r2, r3, [sp, #20] + 8004cca: f10a 0a01 add.w sl, sl, #1 + 8004cce: 9304 str r3, [sp, #16] + 8004cd0: 9307 str r3, [sp, #28] + 8004cd2: f88d 3053 strb.w r3, [sp, #83] @ 0x53 + 8004cd6: 931a str r3, [sp, #104] @ 0x68 + 8004cd8: 4654 mov r4, sl + 8004cda: 2205 movs r2, #5 + 8004cdc: f814 1b01 ldrb.w r1, [r4], #1 + 8004ce0: 484e ldr r0, [pc, #312] @ (8004e1c <_svfiprintf_r+0x1e4>) + 8004ce2: f7fb fa55 bl 8000190 <memchr> + 8004ce6: 9a04 ldr r2, [sp, #16] + 8004ce8: b9d8 cbnz r0, 8004d22 <_svfiprintf_r+0xea> + 8004cea: 06d0 lsls r0, r2, #27 + 8004cec: bf44 itt mi + 8004cee: 2320 movmi r3, #32 + 8004cf0: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 + 8004cf4: 0711 lsls r1, r2, #28 + 8004cf6: bf44 itt mi + 8004cf8: 232b movmi r3, #43 @ 0x2b + 8004cfa: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 + 8004cfe: f89a 3000 ldrb.w r3, [sl] + 8004d02: 2b2a cmp r3, #42 @ 0x2a + 8004d04: d015 beq.n 8004d32 <_svfiprintf_r+0xfa> + 8004d06: 9a07 ldr r2, [sp, #28] + 8004d08: 4654 mov r4, sl + 8004d0a: 2000 movs r0, #0 + 8004d0c: f04f 0c0a mov.w ip, #10 + 8004d10: 4621 mov r1, r4 + 8004d12: f811 3b01 ldrb.w r3, [r1], #1 + 8004d16: 3b30 subs r3, #48 @ 0x30 + 8004d18: 2b09 cmp r3, #9 + 8004d1a: d94b bls.n 8004db4 <_svfiprintf_r+0x17c> + 8004d1c: b1b0 cbz r0, 8004d4c <_svfiprintf_r+0x114> + 8004d1e: 9207 str r2, [sp, #28] + 8004d20: e014 b.n 8004d4c <_svfiprintf_r+0x114> + 8004d22: eba0 0308 sub.w r3, r0, r8 + 8004d26: fa09 f303 lsl.w r3, r9, r3 + 8004d2a: 4313 orrs r3, r2 + 8004d2c: 9304 str r3, [sp, #16] + 8004d2e: 46a2 mov sl, r4 + 8004d30: e7d2 b.n 8004cd8 <_svfiprintf_r+0xa0> + 8004d32: 9b03 ldr r3, [sp, #12] + 8004d34: 1d19 adds r1, r3, #4 + 8004d36: 681b ldr r3, [r3, #0] + 8004d38: 9103 str r1, [sp, #12] + 8004d3a: 2b00 cmp r3, #0 + 8004d3c: bfbb ittet lt + 8004d3e: 425b neglt r3, r3 + 8004d40: f042 0202 orrlt.w r2, r2, #2 + 8004d44: 9307 strge r3, [sp, #28] + 8004d46: 9307 strlt r3, [sp, #28] + 8004d48: bfb8 it lt + 8004d4a: 9204 strlt r2, [sp, #16] + 8004d4c: 7823 ldrb r3, [r4, #0] + 8004d4e: 2b2e cmp r3, #46 @ 0x2e + 8004d50: d10a bne.n 8004d68 <_svfiprintf_r+0x130> + 8004d52: 7863 ldrb r3, [r4, #1] + 8004d54: 2b2a cmp r3, #42 @ 0x2a + 8004d56: d132 bne.n 8004dbe <_svfiprintf_r+0x186> + 8004d58: 9b03 ldr r3, [sp, #12] + 8004d5a: 1d1a adds r2, r3, #4 + 8004d5c: 681b ldr r3, [r3, #0] + 8004d5e: 9203 str r2, [sp, #12] + 8004d60: ea43 73e3 orr.w r3, r3, r3, asr #31 + 8004d64: 3402 adds r4, #2 + 8004d66: 9305 str r3, [sp, #20] + 8004d68: f8df a0c0 ldr.w sl, [pc, #192] @ 8004e2c <_svfiprintf_r+0x1f4> + 8004d6c: 7821 ldrb r1, [r4, #0] + 8004d6e: 2203 movs r2, #3 + 8004d70: 4650 mov r0, sl + 8004d72: f7fb fa0d bl 8000190 <memchr> + 8004d76: b138 cbz r0, 8004d88 <_svfiprintf_r+0x150> + 8004d78: 9b04 ldr r3, [sp, #16] + 8004d7a: eba0 000a sub.w r0, r0, sl + 8004d7e: 2240 movs r2, #64 @ 0x40 + 8004d80: 4082 lsls r2, r0 + 8004d82: 4313 orrs r3, r2 + 8004d84: 3401 adds r4, #1 + 8004d86: 9304 str r3, [sp, #16] + 8004d88: f814 1b01 ldrb.w r1, [r4], #1 + 8004d8c: 4824 ldr r0, [pc, #144] @ (8004e20 <_svfiprintf_r+0x1e8>) + 8004d8e: f88d 1028 strb.w r1, [sp, #40] @ 0x28 + 8004d92: 2206 movs r2, #6 + 8004d94: f7fb f9fc bl 8000190 <memchr> + 8004d98: 2800 cmp r0, #0 + 8004d9a: d036 beq.n 8004e0a <_svfiprintf_r+0x1d2> + 8004d9c: 4b21 ldr r3, [pc, #132] @ (8004e24 <_svfiprintf_r+0x1ec>) + 8004d9e: bb1b cbnz r3, 8004de8 <_svfiprintf_r+0x1b0> + 8004da0: 9b03 ldr r3, [sp, #12] + 8004da2: 3307 adds r3, #7 + 8004da4: f023 0307 bic.w r3, r3, #7 + 8004da8: 3308 adds r3, #8 + 8004daa: 9303 str r3, [sp, #12] + 8004dac: 9b09 ldr r3, [sp, #36] @ 0x24 + 8004dae: 4433 add r3, r6 + 8004db0: 9309 str r3, [sp, #36] @ 0x24 + 8004db2: e76a b.n 8004c8a <_svfiprintf_r+0x52> + 8004db4: fb0c 3202 mla r2, ip, r2, r3 + 8004db8: 460c mov r4, r1 + 8004dba: 2001 movs r0, #1 + 8004dbc: e7a8 b.n 8004d10 <_svfiprintf_r+0xd8> + 8004dbe: 2300 movs r3, #0 + 8004dc0: 3401 adds r4, #1 + 8004dc2: 9305 str r3, [sp, #20] + 8004dc4: 4619 mov r1, r3 + 8004dc6: f04f 0c0a mov.w ip, #10 + 8004dca: 4620 mov r0, r4 + 8004dcc: f810 2b01 ldrb.w r2, [r0], #1 + 8004dd0: 3a30 subs r2, #48 @ 0x30 + 8004dd2: 2a09 cmp r2, #9 + 8004dd4: d903 bls.n 8004dde <_svfiprintf_r+0x1a6> + 8004dd6: 2b00 cmp r3, #0 + 8004dd8: d0c6 beq.n 8004d68 <_svfiprintf_r+0x130> + 8004dda: 9105 str r1, [sp, #20] + 8004ddc: e7c4 b.n 8004d68 <_svfiprintf_r+0x130> + 8004dde: fb0c 2101 mla r1, ip, r1, r2 + 8004de2: 4604 mov r4, r0 + 8004de4: 2301 movs r3, #1 + 8004de6: e7f0 b.n 8004dca <_svfiprintf_r+0x192> + 8004de8: ab03 add r3, sp, #12 + 8004dea: 9300 str r3, [sp, #0] + 8004dec: 462a mov r2, r5 + 8004dee: 4b0e ldr r3, [pc, #56] @ (8004e28 <_svfiprintf_r+0x1f0>) + 8004df0: a904 add r1, sp, #16 + 8004df2: 4638 mov r0, r7 + 8004df4: f3af 8000 nop.w + 8004df8: 1c42 adds r2, r0, #1 + 8004dfa: 4606 mov r6, r0 + 8004dfc: d1d6 bne.n 8004dac <_svfiprintf_r+0x174> + 8004dfe: 89ab ldrh r3, [r5, #12] + 8004e00: 065b lsls r3, r3, #25 + 8004e02: f53f af2d bmi.w 8004c60 <_svfiprintf_r+0x28> + 8004e06: 9809 ldr r0, [sp, #36] @ 0x24 + 8004e08: e72c b.n 8004c64 <_svfiprintf_r+0x2c> + 8004e0a: ab03 add r3, sp, #12 + 8004e0c: 9300 str r3, [sp, #0] + 8004e0e: 462a mov r2, r5 + 8004e10: 4b05 ldr r3, [pc, #20] @ (8004e28 <_svfiprintf_r+0x1f0>) + 8004e12: a904 add r1, sp, #16 + 8004e14: 4638 mov r0, r7 + 8004e16: f000 f879 bl 8004f0c <_printf_i> + 8004e1a: e7ed b.n 8004df8 <_svfiprintf_r+0x1c0> + 8004e1c: 080052b8 .word 0x080052b8 + 8004e20: 080052c2 .word 0x080052c2 + 8004e24: 00000000 .word 0x00000000 + 8004e28: 08004b81 .word 0x08004b81 + 8004e2c: 080052be .word 0x080052be + +08004e30 <_printf_common>: + 8004e30: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8004e34: 4616 mov r6, r2 + 8004e36: 4698 mov r8, r3 + 8004e38: 688a ldr r2, [r1, #8] + 8004e3a: 690b ldr r3, [r1, #16] + 8004e3c: f8dd 9020 ldr.w r9, [sp, #32] + 8004e40: 4293 cmp r3, r2 + 8004e42: bfb8 it lt + 8004e44: 4613 movlt r3, r2 + 8004e46: 6033 str r3, [r6, #0] + 8004e48: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 + 8004e4c: 4607 mov r7, r0 + 8004e4e: 460c mov r4, r1 + 8004e50: b10a cbz r2, 8004e56 <_printf_common+0x26> + 8004e52: 3301 adds r3, #1 + 8004e54: 6033 str r3, [r6, #0] + 8004e56: 6823 ldr r3, [r4, #0] + 8004e58: 0699 lsls r1, r3, #26 + 8004e5a: bf42 ittt mi + 8004e5c: 6833 ldrmi r3, [r6, #0] + 8004e5e: 3302 addmi r3, #2 + 8004e60: 6033 strmi r3, [r6, #0] + 8004e62: 6825 ldr r5, [r4, #0] + 8004e64: f015 0506 ands.w r5, r5, #6 + 8004e68: d106 bne.n 8004e78 <_printf_common+0x48> + 8004e6a: f104 0a19 add.w sl, r4, #25 + 8004e6e: 68e3 ldr r3, [r4, #12] + 8004e70: 6832 ldr r2, [r6, #0] + 8004e72: 1a9b subs r3, r3, r2 + 8004e74: 42ab cmp r3, r5 + 8004e76: dc26 bgt.n 8004ec6 <_printf_common+0x96> + 8004e78: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 + 8004e7c: 6822 ldr r2, [r4, #0] + 8004e7e: 3b00 subs r3, #0 + 8004e80: bf18 it ne + 8004e82: 2301 movne r3, #1 + 8004e84: 0692 lsls r2, r2, #26 + 8004e86: d42b bmi.n 8004ee0 <_printf_common+0xb0> + 8004e88: f104 0243 add.w r2, r4, #67 @ 0x43 + 8004e8c: 4641 mov r1, r8 + 8004e8e: 4638 mov r0, r7 + 8004e90: 47c8 blx r9 + 8004e92: 3001 adds r0, #1 + 8004e94: d01e beq.n 8004ed4 <_printf_common+0xa4> + 8004e96: 6823 ldr r3, [r4, #0] + 8004e98: 6922 ldr r2, [r4, #16] + 8004e9a: f003 0306 and.w r3, r3, #6 + 8004e9e: 2b04 cmp r3, #4 + 8004ea0: bf02 ittt eq + 8004ea2: 68e5 ldreq r5, [r4, #12] + 8004ea4: 6833 ldreq r3, [r6, #0] + 8004ea6: 1aed subeq r5, r5, r3 + 8004ea8: 68a3 ldr r3, [r4, #8] + 8004eaa: bf0c ite eq + 8004eac: ea25 75e5 biceq.w r5, r5, r5, asr #31 + 8004eb0: 2500 movne r5, #0 + 8004eb2: 4293 cmp r3, r2 + 8004eb4: bfc4 itt gt + 8004eb6: 1a9b subgt r3, r3, r2 + 8004eb8: 18ed addgt r5, r5, r3 + 8004eba: 2600 movs r6, #0 + 8004ebc: 341a adds r4, #26 + 8004ebe: 42b5 cmp r5, r6 + 8004ec0: d11a bne.n 8004ef8 <_printf_common+0xc8> + 8004ec2: 2000 movs r0, #0 + 8004ec4: e008 b.n 8004ed8 <_printf_common+0xa8> + 8004ec6: 2301 movs r3, #1 + 8004ec8: 4652 mov r2, sl + 8004eca: 4641 mov r1, r8 + 8004ecc: 4638 mov r0, r7 + 8004ece: 47c8 blx r9 + 8004ed0: 3001 adds r0, #1 + 8004ed2: d103 bne.n 8004edc <_printf_common+0xac> + 8004ed4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8004ed8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8004edc: 3501 adds r5, #1 + 8004ede: e7c6 b.n 8004e6e <_printf_common+0x3e> + 8004ee0: 18e1 adds r1, r4, r3 + 8004ee2: 1c5a adds r2, r3, #1 + 8004ee4: 2030 movs r0, #48 @ 0x30 + 8004ee6: f881 0043 strb.w r0, [r1, #67] @ 0x43 + 8004eea: 4422 add r2, r4 + 8004eec: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 + 8004ef0: f882 1043 strb.w r1, [r2, #67] @ 0x43 + 8004ef4: 3302 adds r3, #2 + 8004ef6: e7c7 b.n 8004e88 <_printf_common+0x58> + 8004ef8: 2301 movs r3, #1 + 8004efa: 4622 mov r2, r4 + 8004efc: 4641 mov r1, r8 + 8004efe: 4638 mov r0, r7 + 8004f00: 47c8 blx r9 + 8004f02: 3001 adds r0, #1 + 8004f04: d0e6 beq.n 8004ed4 <_printf_common+0xa4> + 8004f06: 3601 adds r6, #1 + 8004f08: e7d9 b.n 8004ebe <_printf_common+0x8e> + ... + +08004f0c <_printf_i>: + 8004f0c: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} + 8004f10: 7e0f ldrb r7, [r1, #24] + 8004f12: 9e0c ldr r6, [sp, #48] @ 0x30 + 8004f14: 2f78 cmp r7, #120 @ 0x78 + 8004f16: 4691 mov r9, r2 + 8004f18: 4680 mov r8, r0 + 8004f1a: 460c mov r4, r1 + 8004f1c: 469a mov sl, r3 + 8004f1e: f101 0243 add.w r2, r1, #67 @ 0x43 + 8004f22: d807 bhi.n 8004f34 <_printf_i+0x28> + 8004f24: 2f62 cmp r7, #98 @ 0x62 + 8004f26: d80a bhi.n 8004f3e <_printf_i+0x32> + 8004f28: 2f00 cmp r7, #0 + 8004f2a: f000 80d1 beq.w 80050d0 <_printf_i+0x1c4> + 8004f2e: 2f58 cmp r7, #88 @ 0x58 + 8004f30: f000 80b8 beq.w 80050a4 <_printf_i+0x198> + 8004f34: f104 0642 add.w r6, r4, #66 @ 0x42 + 8004f38: f884 7042 strb.w r7, [r4, #66] @ 0x42 + 8004f3c: e03a b.n 8004fb4 <_printf_i+0xa8> + 8004f3e: f1a7 0363 sub.w r3, r7, #99 @ 0x63 + 8004f42: 2b15 cmp r3, #21 + 8004f44: d8f6 bhi.n 8004f34 <_printf_i+0x28> + 8004f46: a101 add r1, pc, #4 @ (adr r1, 8004f4c <_printf_i+0x40>) + 8004f48: f851 f023 ldr.w pc, [r1, r3, lsl #2] + 8004f4c: 08004fa5 .word 0x08004fa5 + 8004f50: 08004fb9 .word 0x08004fb9 + 8004f54: 08004f35 .word 0x08004f35 + 8004f58: 08004f35 .word 0x08004f35 + 8004f5c: 08004f35 .word 0x08004f35 + 8004f60: 08004f35 .word 0x08004f35 + 8004f64: 08004fb9 .word 0x08004fb9 + 8004f68: 08004f35 .word 0x08004f35 + 8004f6c: 08004f35 .word 0x08004f35 + 8004f70: 08004f35 .word 0x08004f35 + 8004f74: 08004f35 .word 0x08004f35 + 8004f78: 080050b7 .word 0x080050b7 + 8004f7c: 08004fe3 .word 0x08004fe3 + 8004f80: 08005071 .word 0x08005071 + 8004f84: 08004f35 .word 0x08004f35 + 8004f88: 08004f35 .word 0x08004f35 + 8004f8c: 080050d9 .word 0x080050d9 + 8004f90: 08004f35 .word 0x08004f35 + 8004f94: 08004fe3 .word 0x08004fe3 + 8004f98: 08004f35 .word 0x08004f35 + 8004f9c: 08004f35 .word 0x08004f35 + 8004fa0: 08005079 .word 0x08005079 + 8004fa4: 6833 ldr r3, [r6, #0] + 8004fa6: 1d1a adds r2, r3, #4 + 8004fa8: 681b ldr r3, [r3, #0] + 8004faa: 6032 str r2, [r6, #0] + 8004fac: f104 0642 add.w r6, r4, #66 @ 0x42 + 8004fb0: f884 3042 strb.w r3, [r4, #66] @ 0x42 + 8004fb4: 2301 movs r3, #1 + 8004fb6: e09c b.n 80050f2 <_printf_i+0x1e6> + 8004fb8: 6833 ldr r3, [r6, #0] + 8004fba: 6820 ldr r0, [r4, #0] + 8004fbc: 1d19 adds r1, r3, #4 + 8004fbe: 6031 str r1, [r6, #0] + 8004fc0: 0606 lsls r6, r0, #24 + 8004fc2: d501 bpl.n 8004fc8 <_printf_i+0xbc> + 8004fc4: 681d ldr r5, [r3, #0] + 8004fc6: e003 b.n 8004fd0 <_printf_i+0xc4> + 8004fc8: 0645 lsls r5, r0, #25 + 8004fca: d5fb bpl.n 8004fc4 <_printf_i+0xb8> + 8004fcc: f9b3 5000 ldrsh.w r5, [r3] + 8004fd0: 2d00 cmp r5, #0 + 8004fd2: da03 bge.n 8004fdc <_printf_i+0xd0> + 8004fd4: 232d movs r3, #45 @ 0x2d + 8004fd6: 426d negs r5, r5 + 8004fd8: f884 3043 strb.w r3, [r4, #67] @ 0x43 + 8004fdc: 4858 ldr r0, [pc, #352] @ (8005140 <_printf_i+0x234>) + 8004fde: 230a movs r3, #10 + 8004fe0: e011 b.n 8005006 <_printf_i+0xfa> + 8004fe2: 6821 ldr r1, [r4, #0] + 8004fe4: 6833 ldr r3, [r6, #0] + 8004fe6: 0608 lsls r0, r1, #24 + 8004fe8: f853 5b04 ldr.w r5, [r3], #4 + 8004fec: d402 bmi.n 8004ff4 <_printf_i+0xe8> + 8004fee: 0649 lsls r1, r1, #25 + 8004ff0: bf48 it mi + 8004ff2: b2ad uxthmi r5, r5 + 8004ff4: 2f6f cmp r7, #111 @ 0x6f + 8004ff6: 4852 ldr r0, [pc, #328] @ (8005140 <_printf_i+0x234>) + 8004ff8: 6033 str r3, [r6, #0] + 8004ffa: bf14 ite ne + 8004ffc: 230a movne r3, #10 + 8004ffe: 2308 moveq r3, #8 + 8005000: 2100 movs r1, #0 + 8005002: f884 1043 strb.w r1, [r4, #67] @ 0x43 + 8005006: 6866 ldr r6, [r4, #4] + 8005008: 60a6 str r6, [r4, #8] + 800500a: 2e00 cmp r6, #0 + 800500c: db05 blt.n 800501a <_printf_i+0x10e> + 800500e: 6821 ldr r1, [r4, #0] + 8005010: 432e orrs r6, r5 + 8005012: f021 0104 bic.w r1, r1, #4 + 8005016: 6021 str r1, [r4, #0] + 8005018: d04b beq.n 80050b2 <_printf_i+0x1a6> + 800501a: 4616 mov r6, r2 + 800501c: fbb5 f1f3 udiv r1, r5, r3 + 8005020: fb03 5711 mls r7, r3, r1, r5 + 8005024: 5dc7 ldrb r7, [r0, r7] + 8005026: f806 7d01 strb.w r7, [r6, #-1]! + 800502a: 462f mov r7, r5 + 800502c: 42bb cmp r3, r7 + 800502e: 460d mov r5, r1 + 8005030: d9f4 bls.n 800501c <_printf_i+0x110> + 8005032: 2b08 cmp r3, #8 + 8005034: d10b bne.n 800504e <_printf_i+0x142> + 8005036: 6823 ldr r3, [r4, #0] + 8005038: 07df lsls r7, r3, #31 + 800503a: d508 bpl.n 800504e <_printf_i+0x142> + 800503c: 6923 ldr r3, [r4, #16] + 800503e: 6861 ldr r1, [r4, #4] + 8005040: 4299 cmp r1, r3 + 8005042: bfde ittt le + 8005044: 2330 movle r3, #48 @ 0x30 + 8005046: f806 3c01 strble.w r3, [r6, #-1] + 800504a: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff + 800504e: 1b92 subs r2, r2, r6 + 8005050: 6122 str r2, [r4, #16] + 8005052: f8cd a000 str.w sl, [sp] + 8005056: 464b mov r3, r9 + 8005058: aa03 add r2, sp, #12 + 800505a: 4621 mov r1, r4 + 800505c: 4640 mov r0, r8 + 800505e: f7ff fee7 bl 8004e30 <_printf_common> + 8005062: 3001 adds r0, #1 + 8005064: d14a bne.n 80050fc <_printf_i+0x1f0> + 8005066: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 800506a: b004 add sp, #16 + 800506c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8005070: 6823 ldr r3, [r4, #0] + 8005072: f043 0320 orr.w r3, r3, #32 + 8005076: 6023 str r3, [r4, #0] + 8005078: 4832 ldr r0, [pc, #200] @ (8005144 <_printf_i+0x238>) + 800507a: 2778 movs r7, #120 @ 0x78 + 800507c: f884 7045 strb.w r7, [r4, #69] @ 0x45 + 8005080: 6823 ldr r3, [r4, #0] + 8005082: 6831 ldr r1, [r6, #0] + 8005084: 061f lsls r7, r3, #24 + 8005086: f851 5b04 ldr.w r5, [r1], #4 + 800508a: d402 bmi.n 8005092 <_printf_i+0x186> + 800508c: 065f lsls r7, r3, #25 + 800508e: bf48 it mi + 8005090: b2ad uxthmi r5, r5 + 8005092: 6031 str r1, [r6, #0] + 8005094: 07d9 lsls r1, r3, #31 + 8005096: bf44 itt mi + 8005098: f043 0320 orrmi.w r3, r3, #32 + 800509c: 6023 strmi r3, [r4, #0] + 800509e: b11d cbz r5, 80050a8 <_printf_i+0x19c> + 80050a0: 2310 movs r3, #16 + 80050a2: e7ad b.n 8005000 <_printf_i+0xf4> + 80050a4: 4826 ldr r0, [pc, #152] @ (8005140 <_printf_i+0x234>) + 80050a6: e7e9 b.n 800507c <_printf_i+0x170> + 80050a8: 6823 ldr r3, [r4, #0] + 80050aa: f023 0320 bic.w r3, r3, #32 + 80050ae: 6023 str r3, [r4, #0] + 80050b0: e7f6 b.n 80050a0 <_printf_i+0x194> + 80050b2: 4616 mov r6, r2 + 80050b4: e7bd b.n 8005032 <_printf_i+0x126> + 80050b6: 6833 ldr r3, [r6, #0] + 80050b8: 6825 ldr r5, [r4, #0] + 80050ba: 6961 ldr r1, [r4, #20] + 80050bc: 1d18 adds r0, r3, #4 + 80050be: 6030 str r0, [r6, #0] + 80050c0: 062e lsls r6, r5, #24 + 80050c2: 681b ldr r3, [r3, #0] + 80050c4: d501 bpl.n 80050ca <_printf_i+0x1be> + 80050c6: 6019 str r1, [r3, #0] + 80050c8: e002 b.n 80050d0 <_printf_i+0x1c4> + 80050ca: 0668 lsls r0, r5, #25 + 80050cc: d5fb bpl.n 80050c6 <_printf_i+0x1ba> + 80050ce: 8019 strh r1, [r3, #0] + 80050d0: 2300 movs r3, #0 + 80050d2: 6123 str r3, [r4, #16] + 80050d4: 4616 mov r6, r2 + 80050d6: e7bc b.n 8005052 <_printf_i+0x146> + 80050d8: 6833 ldr r3, [r6, #0] + 80050da: 1d1a adds r2, r3, #4 + 80050dc: 6032 str r2, [r6, #0] + 80050de: 681e ldr r6, [r3, #0] + 80050e0: 6862 ldr r2, [r4, #4] + 80050e2: 2100 movs r1, #0 + 80050e4: 4630 mov r0, r6 + 80050e6: f7fb f853 bl 8000190 <memchr> + 80050ea: b108 cbz r0, 80050f0 <_printf_i+0x1e4> + 80050ec: 1b80 subs r0, r0, r6 + 80050ee: 6060 str r0, [r4, #4] + 80050f0: 6863 ldr r3, [r4, #4] + 80050f2: 6123 str r3, [r4, #16] + 80050f4: 2300 movs r3, #0 + 80050f6: f884 3043 strb.w r3, [r4, #67] @ 0x43 + 80050fa: e7aa b.n 8005052 <_printf_i+0x146> + 80050fc: 6923 ldr r3, [r4, #16] + 80050fe: 4632 mov r2, r6 + 8005100: 4649 mov r1, r9 + 8005102: 4640 mov r0, r8 + 8005104: 47d0 blx sl + 8005106: 3001 adds r0, #1 + 8005108: d0ad beq.n 8005066 <_printf_i+0x15a> + 800510a: 6823 ldr r3, [r4, #0] + 800510c: 079b lsls r3, r3, #30 + 800510e: d413 bmi.n 8005138 <_printf_i+0x22c> + 8005110: 68e0 ldr r0, [r4, #12] + 8005112: 9b03 ldr r3, [sp, #12] + 8005114: 4298 cmp r0, r3 + 8005116: bfb8 it lt + 8005118: 4618 movlt r0, r3 + 800511a: e7a6 b.n 800506a <_printf_i+0x15e> + 800511c: 2301 movs r3, #1 + 800511e: 4632 mov r2, r6 + 8005120: 4649 mov r1, r9 + 8005122: 4640 mov r0, r8 + 8005124: 47d0 blx sl + 8005126: 3001 adds r0, #1 + 8005128: d09d beq.n 8005066 <_printf_i+0x15a> + 800512a: 3501 adds r5, #1 + 800512c: 68e3 ldr r3, [r4, #12] + 800512e: 9903 ldr r1, [sp, #12] + 8005130: 1a5b subs r3, r3, r1 + 8005132: 42ab cmp r3, r5 + 8005134: dcf2 bgt.n 800511c <_printf_i+0x210> + 8005136: e7eb b.n 8005110 <_printf_i+0x204> + 8005138: 2500 movs r5, #0 + 800513a: f104 0619 add.w r6, r4, #25 + 800513e: e7f5 b.n 800512c <_printf_i+0x220> + 8005140: 080052c9 .word 0x080052c9 + 8005144: 080052da .word 0x080052da + +08005148 <memmove>: + 8005148: 4288 cmp r0, r1 + 800514a: b510 push {r4, lr} + 800514c: eb01 0402 add.w r4, r1, r2 + 8005150: d902 bls.n 8005158 <memmove+0x10> + 8005152: 4284 cmp r4, r0 + 8005154: 4623 mov r3, r4 + 8005156: d807 bhi.n 8005168 <memmove+0x20> + 8005158: 1e43 subs r3, r0, #1 + 800515a: 42a1 cmp r1, r4 + 800515c: d008 beq.n 8005170 <memmove+0x28> + 800515e: f811 2b01 ldrb.w r2, [r1], #1 + 8005162: f803 2f01 strb.w r2, [r3, #1]! + 8005166: e7f8 b.n 800515a <memmove+0x12> + 8005168: 4402 add r2, r0 + 800516a: 4601 mov r1, r0 + 800516c: 428a cmp r2, r1 + 800516e: d100 bne.n 8005172 <memmove+0x2a> + 8005170: bd10 pop {r4, pc} + 8005172: f813 4d01 ldrb.w r4, [r3, #-1]! + 8005176: f802 4d01 strb.w r4, [r2, #-1]! + 800517a: e7f7 b.n 800516c <memmove+0x24> + +0800517c <_realloc_r>: + 800517c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8005180: 4607 mov r7, r0 + 8005182: 4614 mov r4, r2 + 8005184: 460d mov r5, r1 + 8005186: b921 cbnz r1, 8005192 <_realloc_r+0x16> + 8005188: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 800518c: 4611 mov r1, r2 + 800518e: f7ff bbad b.w 80048ec <_malloc_r> + 8005192: b92a cbnz r2, 80051a0 <_realloc_r+0x24> + 8005194: f7ff fcaa bl 8004aec <_free_r> + 8005198: 4625 mov r5, r4 + 800519a: 4628 mov r0, r5 + 800519c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 80051a0: f000 f81a bl 80051d8 <_malloc_usable_size_r> + 80051a4: 4284 cmp r4, r0 + 80051a6: 4606 mov r6, r0 + 80051a8: d802 bhi.n 80051b0 <_realloc_r+0x34> + 80051aa: ebb4 0f50 cmp.w r4, r0, lsr #1 + 80051ae: d8f4 bhi.n 800519a <_realloc_r+0x1e> + 80051b0: 4621 mov r1, r4 + 80051b2: 4638 mov r0, r7 + 80051b4: f7ff fb9a bl 80048ec <_malloc_r> + 80051b8: 4680 mov r8, r0 + 80051ba: b908 cbnz r0, 80051c0 <_realloc_r+0x44> + 80051bc: 4645 mov r5, r8 + 80051be: e7ec b.n 800519a <_realloc_r+0x1e> + 80051c0: 42b4 cmp r4, r6 + 80051c2: 4622 mov r2, r4 + 80051c4: 4629 mov r1, r5 + 80051c6: bf28 it cs + 80051c8: 4632 movcs r2, r6 + 80051ca: f7ff fc81 bl 8004ad0 <memcpy> + 80051ce: 4629 mov r1, r5 + 80051d0: 4638 mov r0, r7 + 80051d2: f7ff fc8b bl 8004aec <_free_r> + 80051d6: e7f1 b.n 80051bc <_realloc_r+0x40> + +080051d8 <_malloc_usable_size_r>: + 80051d8: f851 3c04 ldr.w r3, [r1, #-4] + 80051dc: 1f18 subs r0, r3, #4 + 80051de: 2b00 cmp r3, #0 + 80051e0: bfbc itt lt + 80051e2: 580b ldrlt r3, [r1, r0] + 80051e4: 18c0 addlt r0, r0, r3 + 80051e6: 4770 bx lr + +080051e8 <_init>: + 80051e8: b5f8 push {r3, r4, r5, r6, r7, lr} + 80051ea: bf00 nop + 80051ec: bcf8 pop {r3, r4, r5, r6, r7} + 80051ee: bc08 pop {r3} + 80051f0: 469e mov lr, r3 + 80051f2: 4770 bx lr + +080051f4 <_fini>: + 80051f4: b5f8 push {r3, r4, r5, r6, r7, lr} + 80051f6: bf00 nop + 80051f8: bcf8 pop {r3, r4, r5, r6, r7} + 80051fa: bc08 pop {r3} + 80051fc: 469e mov lr, r3 + 80051fe: 4770 bx lr |